From patchwork Tue Aug 13 10:19:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1146178 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506796-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="B2jfOI57"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4677xy1r6xz9sND for ; Tue, 13 Aug 2019 20:20:04 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=Hkksc3l2a04GEOLitTRkf3oxo4+Kf7jPZy9G4a7zaOO7PsG2OeEr+ ItkTlM6rLjBVDvA6yD2C5hMs58wwCucLCqknWyhDLCJJrBmLcd10W57sNw8GIU/F bQME1zKWfzrFn/zS4e6MDh6oCzDFjJj3jJNO+hxjz6xMxKf571c0cU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=TT897GHeJPyKUb+t6PUNrw6nA1A=; b=B2jfOI57fEnul9nykXv1 nVB8RDlvkqBim5UB+lINKusPqBJFKQTRF9F+D+w5bsHckmdbvQboIYZppOy6cKus Nr4MJcaikZafGfHWW50Js51c2f5n/LLljasxIuOvk9314UTTSqqSpTI+qF2NPsfT pDtI7X0JxFF9iNVT1YLf7xc= Received: (qmail 96834 invoked by alias); 13 Aug 2019 10:19:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 96822 invoked by uid 89); 13 Aug 2019 10:19:57 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=MOV X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 13 Aug 2019 10:19:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AD144344 for ; Tue, 13 Aug 2019 03:19:53 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 550FC3F694 for ; Tue, 13 Aug 2019 03:19:53 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Make simd_immediate_info INDEX explicit Date: Tue, 13 Aug 2019 11:19:52 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes This patch tweaks the representation of SVE INDEX instructions in simd_immediate_info so that it's easier to add new types of constant on top. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied as r274371. Richard 2019-08-13 Richard Sandiford gcc/ * config/aarch64/aarch64.c (simd_immediate_info::insn_type): Add INDEX. (simd_immediate_info::value, simd_immediate_info::step) (simd_immediate_info::modifier, simd_immediate_info::shift): Replace with... (simd_immediate_info::u): ...this new union. (simd_immediate_info::simd_immediate_info): Update accordingly. (aarch64_output_simd_mov_immediate): Likewise. (aarch64_output_sve_mov_immediate): Likewise. Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2019-08-13 10:50:31.050777017 +0100 +++ gcc/config/aarch64/aarch64.c 2019-08-13 11:16:57.723336150 +0100 @@ -83,7 +83,7 @@ #define POINTER_BYTES (POINTER_SIZE / BI /* Information about a legitimate vector immediate operand. */ struct simd_immediate_info { - enum insn_type { MOV, MVN }; + enum insn_type { MOV, MVN, INDEX }; enum modifier_type { LSL, MSL }; simd_immediate_info () {} @@ -96,29 +96,43 @@ struct simd_immediate_info /* The mode of the elements. */ scalar_mode elt_mode; - /* The value of each element if all elements are the same, or the - first value if the constant is a series. */ - rtx value; - - /* The value of the step if the constant is a series, null otherwise. */ - rtx step; - /* The instruction to use to move the immediate into a vector. */ insn_type insn; - /* The kind of shift modifier to use, and the number of bits to shift. - This is (LSL, 0) if no shift is needed. */ - modifier_type modifier; - unsigned int shift; + union + { + /* For MOV and MVN. */ + struct + { + /* The value of each element. */ + rtx value; + + /* The kind of shift modifier to use, and the number of bits to shift. + This is (LSL, 0) if no shift is needed. */ + modifier_type modifier; + unsigned int shift; + } mov; + + /* For INDEX. */ + struct + { + /* The value of the first element and the step to be added for each + subsequent element. */ + rtx base, step; + } index; + } u; }; /* Construct a floating-point immediate in which each element has mode ELT_MODE_IN and value VALUE_IN. */ inline simd_immediate_info ::simd_immediate_info (scalar_float_mode elt_mode_in, rtx value_in) - : elt_mode (elt_mode_in), value (value_in), step (NULL_RTX), insn (MOV), - modifier (LSL), shift (0) -{} + : elt_mode (elt_mode_in), insn (MOV) +{ + u.mov.value = value_in; + u.mov.modifier = LSL; + u.mov.shift = 0; +} /* Construct an integer immediate in which each element has mode ELT_MODE_IN and value VALUE_IN. The other parameters are as for the structure @@ -128,17 +142,22 @@ struct simd_immediate_info unsigned HOST_WIDE_INT value_in, insn_type insn_in, modifier_type modifier_in, unsigned int shift_in) - : elt_mode (elt_mode_in), value (gen_int_mode (value_in, elt_mode_in)), - step (NULL_RTX), insn (insn_in), modifier (modifier_in), shift (shift_in) -{} + : elt_mode (elt_mode_in), insn (insn_in) +{ + u.mov.value = gen_int_mode (value_in, elt_mode_in); + u.mov.modifier = modifier_in; + u.mov.shift = shift_in; +} /* Construct an integer immediate in which each element has mode ELT_MODE_IN - and where element I is equal to VALUE_IN + I * STEP_IN. */ + and where element I is equal to BASE_IN + I * STEP_IN. */ inline simd_immediate_info -::simd_immediate_info (scalar_mode elt_mode_in, rtx value_in, rtx step_in) - : elt_mode (elt_mode_in), value (value_in), step (step_in), insn (MOV), - modifier (LSL), shift (0) -{} +::simd_immediate_info (scalar_mode elt_mode_in, rtx base_in, rtx step_in) + : elt_mode (elt_mode_in), insn (INDEX) +{ + u.index.base = base_in; + u.index.step = step_in; +} /* The current code model. */ enum aarch64_code_model aarch64_cmodel; @@ -16275,17 +16294,18 @@ aarch64_output_simd_mov_immediate (rtx c if (GET_MODE_CLASS (info.elt_mode) == MODE_FLOAT) { - gcc_assert (info.shift == 0 && info.insn == simd_immediate_info::MOV); + gcc_assert (info.insn == simd_immediate_info::MOV + && info.u.mov.shift == 0); /* For FP zero change it to a CONST_INT 0 and use the integer SIMD move immediate path. */ - if (aarch64_float_const_zero_rtx_p (info.value)) - info.value = GEN_INT (0); + if (aarch64_float_const_zero_rtx_p (info.u.mov.value)) + info.u.mov.value = GEN_INT (0); else { const unsigned int buf_size = 20; char float_buf[buf_size] = {'\0'}; real_to_decimal_for_mode (float_buf, - CONST_DOUBLE_REAL_VALUE (info.value), + CONST_DOUBLE_REAL_VALUE (info.u.mov.value), buf_size, buf_size, 1, info.elt_mode); if (lane_count == 1) @@ -16297,36 +16317,39 @@ aarch64_output_simd_mov_immediate (rtx c } } - gcc_assert (CONST_INT_P (info.value)); + gcc_assert (CONST_INT_P (info.u.mov.value)); if (which == AARCH64_CHECK_MOV) { mnemonic = info.insn == simd_immediate_info::MVN ? "mvni" : "movi"; - shift_op = info.modifier == simd_immediate_info::MSL ? "msl" : "lsl"; + shift_op = (info.u.mov.modifier == simd_immediate_info::MSL + ? "msl" : "lsl"); if (lane_count == 1) snprintf (templ, sizeof (templ), "%s\t%%d0, " HOST_WIDE_INT_PRINT_HEX, - mnemonic, UINTVAL (info.value)); - else if (info.shift) + mnemonic, UINTVAL (info.u.mov.value)); + else if (info.u.mov.shift) snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX ", %s %d", mnemonic, lane_count, - element_char, UINTVAL (info.value), shift_op, info.shift); + element_char, UINTVAL (info.u.mov.value), shift_op, + info.u.mov.shift); else snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX, mnemonic, lane_count, - element_char, UINTVAL (info.value)); + element_char, UINTVAL (info.u.mov.value)); } else { /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */ mnemonic = info.insn == simd_immediate_info::MVN ? "bic" : "orr"; - if (info.shift) + if (info.u.mov.shift) snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, #" HOST_WIDE_INT_PRINT_DEC ", %s #%d", mnemonic, lane_count, - element_char, UINTVAL (info.value), "lsl", info.shift); + element_char, UINTVAL (info.u.mov.value), "lsl", + info.u.mov.shift); else snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, #" HOST_WIDE_INT_PRINT_DEC, mnemonic, lane_count, - element_char, UINTVAL (info.value)); + element_char, UINTVAL (info.u.mov.value)); } return templ; } @@ -16370,24 +16393,25 @@ aarch64_output_sve_mov_immediate (rtx co element_char = sizetochar (GET_MODE_BITSIZE (info.elt_mode)); - if (info.step) + if (info.insn == simd_immediate_info::INDEX) { snprintf (templ, sizeof (templ), "index\t%%0.%c, #" HOST_WIDE_INT_PRINT_DEC ", #" HOST_WIDE_INT_PRINT_DEC, - element_char, INTVAL (info.value), INTVAL (info.step)); + element_char, INTVAL (info.u.index.base), + INTVAL (info.u.index.step)); return templ; } if (GET_MODE_CLASS (info.elt_mode) == MODE_FLOAT) { - if (aarch64_float_const_zero_rtx_p (info.value)) - info.value = GEN_INT (0); + if (aarch64_float_const_zero_rtx_p (info.u.mov.value)) + info.u.mov.value = GEN_INT (0); else { const int buf_size = 20; char float_buf[buf_size] = {}; real_to_decimal_for_mode (float_buf, - CONST_DOUBLE_REAL_VALUE (info.value), + CONST_DOUBLE_REAL_VALUE (info.u.mov.value), buf_size, buf_size, 1, info.elt_mode); snprintf (templ, sizeof (templ), "fmov\t%%0.%c, #%s", @@ -16397,7 +16421,7 @@ aarch64_output_sve_mov_immediate (rtx co } snprintf (templ, sizeof (templ), "mov\t%%0.%c, #" HOST_WIDE_INT_PRINT_DEC, - element_char, INTVAL (info.value)); + element_char, INTVAL (info.u.mov.value)); return templ; }