From patchwork Tue Aug 13 04:47:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1146013 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506747-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="pDZWXbQE"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vGK58FIL"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4670bs4nc1z9sNF for ; Tue, 13 Aug 2019 14:48:55 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=XpirMVRA48sobMLq5QArJg+Wq3EM5ENdh9rsr+Ru1pnHfR MaC5EJmgKtMqGr/vQOqfBZ9cEftHeswYzIXDrlE8xKMaDULb1eqzRWsWWXNV/rzt kvrRWiJWdUr+hEm0z0Bfaodmd3BRGlIJYqp+TkOB4XiUenMDwZQClfN/C+D48= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=T3HDYFNDxJkk4K7ykMdkI1KFET0=; b=pDZWXbQEVhzMwgyHYA9T fKWmaUhNXOrNdC9zMIO1z05tWrxvy+/nefm0ez6aNGZ6Fx1pCC130cn9KN6JibkD +e+4a5ehjlAzNo5/eGTTKTDBS5HEFkQYw/4NsWKzwliPs4bqz04lS7iPZXxGoYgX wM5DNbu6Zv94c1H/pGL7Bv4= Received: (qmail 110226 invoked by alias); 13 Aug 2019 04:48:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 110034 invoked by uid 89); 13 Aug 2019 04:48:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-7.2 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=2019-08-13, xyv, qd, xYv X-HELO: mail-ot1-f42.google.com Received: from mail-ot1-f42.google.com (HELO mail-ot1-f42.google.com) (209.85.210.42) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 13 Aug 2019 04:48:05 +0000 Received: by mail-ot1-f42.google.com with SMTP id e12so23466764otp.10 for ; Mon, 12 Aug 2019 21:48:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=+yg/q753k9RPnFj2BS2mljx3rXNx/ZWaFdhA8JN8EPw=; b=vGK58FILU/T4FTiCrXQlPsSnXnA9nPY08nzPpScp691rm7a1rreP/7pT5ILoZeUCQO iEKgRbyoiFyQIEx6tWm+ps9ypEySVvB/bcibT1n63UzXW6XKTY+QDLyFy0CuCu8UHGBn FvD1vgMEzNVZKmU7BliA9EhYcQREDQM0nG2fKoN1eAud7uB1odwgr+pVx0/XvVK++IkO io0iR+qrjMqOnMS4s96YmLXSk7hmmITvnA7dKmuZWBD7mW/dGif7JqHfmi3aViDmp8mg W2XNPmeH93abQEB2E9YCBCBDGh/A1c3FGpEpfJEdvz4X4pa8rrtN9E2Z3BQ/0MBvN+02 vABA== MIME-Version: 1.0 From: Uros Bizjak Date: Tue, 13 Aug 2019 06:47:52 +0200 Message-ID: Subject: [PATCH, i386]: Add missing *mmx_pinsr{q,d} patterns To: "gcc-patches@gcc.gnu.org" We can implement these for TARGET_MMX_WITH_SSE and TARGET_SSE4_1. 2019-08-13 Uroš Bizjak * config/i386/i386.md (ix86_expand_vector_set) : Use vec_merge path for TARGET_MMX_WITH_SSE && TARGET_SSE4_1. : Ditto. * config/i386/mmx.md (*mmx_pinsrd): New insn pattern. (*mmx_pinsrb): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/i386-expand.c =================================================================== --- config/i386/i386-expand.c (revision 274317) +++ config/i386/i386-expand.c (working copy) @@ -14243,8 +14243,13 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, r switch (mode) { + case E_V2SImode: + use_vec_merge = TARGET_MMX_WITH_SSE && TARGET_SSE4_1; + if (use_vec_merge) + break; + /* FALLTHRU */ + case E_V2SFmode: - case E_V2SImode: if (mmx_ok) { tmp = gen_reg_rtx (GET_MODE_INNER (mode)); @@ -14409,6 +14414,7 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, r break; case E_V8QImode: + use_vec_merge = TARGET_MMX_WITH_SSE && TARGET_SSE4_1; break; case E_V32QImode: Index: config/i386/mmx.md =================================================================== --- config/i386/mmx.md (revision 274317) +++ config/i386/mmx.md (working copy) @@ -1394,6 +1394,36 @@ (set_attr "type" "mmxcvt,sselog,sselog") (set_attr "mode" "DI,TI,TI")]) +(define_insn "*mmx_pinsrd" + [(set (match_operand:V2SI 0 "register_operand" "=x,Yv") + (vec_merge:V2SI + (vec_duplicate:V2SI + (match_operand:SI 2 "nonimmediate_operand" "rm,rm")) + (match_operand:V2SI 1 "register_operand" "0,Yv") + (match_operand:SI 3 "const_int_operand")))] + "TARGET_MMX_WITH_SSE && TARGET_SSE4_1 + && ((unsigned) exact_log2 (INTVAL (operands[3])) + < GET_MODE_NUNITS (V2SImode))" +{ + operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); + switch (which_alternative) + { + case 1: + return "vpinsrd\t{%3, %2, %1, %0|%0, %1, %2, %3}"; + case 0: + return "pinsrd\t{%3, %2, %0|%0, %2, %3}"; + default: + gcc_unreachable (); + } +} + [(set_attr "isa" "noavx,avx") + (set_attr "prefix_data16" "1") + (set_attr "prefix_extra" "1") + (set_attr "type" "sselog") + (set_attr "length_immediate" "1") + (set_attr "prefix" "orig,vex") + (set_attr "mode" "TI")]) + (define_expand "mmx_pinsrw" [(set (match_operand:V4HI 0 "register_operand") (vec_merge:V4HI @@ -1444,6 +1474,42 @@ (set_attr "length_immediate" "1") (set_attr "mode" "DI,TI,TI")]) +(define_insn "*mmx_pinsrb" + [(set (match_operand:V8QI 0 "register_operand" "=x,Yv") + (vec_merge:V8QI + (vec_duplicate:V8QI + (match_operand:QI 2 "nonimmediate_operand" "rm,rm")) + (match_operand:V8QI 1 "register_operand" "0,Yv") + (match_operand:SI 3 "const_int_operand")))] + "TARGET_MMX_WITH_SSE && TARGET_SSE4_1 + && ((unsigned) exact_log2 (INTVAL (operands[3])) + < GET_MODE_NUNITS (V8QImode))" +{ + operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); + switch (which_alternative) + { + case 1: + if (MEM_P (operands[2])) + return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}"; + else + return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}"; + case 0: + if (MEM_P (operands[2])) + return "pinsrb\t{%3, %2, %0|%0, %2, %3}"; + else + return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}"; + default: + gcc_unreachable (); + } +} + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog") + (set_attr "prefix_data16" "1") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "orig,vex") + (set_attr "mode" "TI")]) + (define_insn "mmx_pextrw" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI