From patchwork Wed Aug 7 19:02:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1143628 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506452-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="g9cCoDdl"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463gqg5d0yz9sN6 for ; Thu, 8 Aug 2019 05:02:39 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=BWfRwW2LUnzPNn8+kfAdcDoKe1/I6CG26XwO8qnjnkAPa8MQJJYlW WZu/ilXqExJueBfaeGhVUzogWJxZEzOeV3G55F2bvCB77O8mWeEdrXsFMOyEz+8M eqpSv9dd43+ybJZ2rKHuqo/x0gPgRu2cj7YxJ+SSr9a3MiaLp8dNno= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=1a4BE74FtExU2z8BVdpfuPV61Fo=; b=g9cCoDdl8kEHMA7xzQ6U 4HmKg/KA9i2nLyHN4QJfOv+l6hkqEti7J4+2j8V2DyG/CFkAK9bZFot1uqVVZoLX dj1JDcX0Q5f4u4EuQrCT44o3c8AfImRCnxVRQIh5Hhn3V+w2ES8ZyIoFh0GSgxLq ZhAkeu6YWIL20Ko1sdc7nqk= Received: (qmail 55737 invoked by alias); 7 Aug 2019 19:02:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 55726 invoked by uid 89); 7 Aug 2019 19:02:30 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.1 spammy=25678 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Aug 2019 19:02:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D770828 for ; Wed, 7 Aug 2019 12:02:26 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7E5873F575 for ; Wed, 7 Aug 2019 12:02:26 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Merge SVE ternary FP operations Date: Wed, 07 Aug 2019 20:02:25 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes This patch combines the four individual fused multiply-add optabs into one pattern and uses unspecs instead of rtx codes. This is part of a series of patches that change the SVE FP patterns so that they can describe cases in which the predicate isn't all-true. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied as r274189. Richard 2019-08-07 Richard Sandiford gcc/ * config/aarch64/aarch64-sve.md (fma4, *fma4) (fnma4, *fnma4, fnms4, *fnms4) (fms4, *fms4): Replace with... (4) (*4): ...these new patterns. Use unspecs instead of rtx codes. (cond_, *cond__2, *cond__4) (*cond__any): Add the predicate to SVE_COND_FP_TERNARY. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-08-07 19:56:41.377879110 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-08-07 19:58:39.608999273 +0100 @@ -85,10 +85,6 @@ ;; ---- [INT] Dot product ;; ---- [INT] Sum of absolute differences ;; ---- [FP] General ternary arithmetic corresponding to unspecs -;; ---- [FP] FMLA and FMAD -;; ---- [FP] FMLS and FMSB -;; ---- [FP] FNMLA and FNMAD -;; ---- [FP] FNMLS and FNMSB ;; ;; == Comparisons and selects ;; ---- [INT,FP] Select based on predicates @@ -2469,13 +2465,46 @@ (define_expand "sad" ;; - FNMSB ;; ------------------------------------------------------------------------- +;; Unpredicated floating-point ternary operations. +(define_expand "4" + [(set (match_operand:SVE_F 0 "register_operand") + (unspec:SVE_F + [(match_dup 4) + (match_operand:SVE_F 1 "register_operand") + (match_operand:SVE_F 2 "register_operand") + (match_operand:SVE_F 3 "register_operand")] + SVE_COND_FP_TERNARY))] + "TARGET_SVE" + { + operands[4] = aarch64_ptrue_reg (mode); + } +) + +;; Predicated floating-point ternary operations. +(define_insn "*4" + [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") + (unspec:SVE_F + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (match_operand:SVE_F 2 "register_operand" "%w, 0, w") + (match_operand:SVE_F 3 "register_operand" "w, w, w") + (match_operand:SVE_F 4 "register_operand" "0, w, w")] + SVE_COND_FP_TERNARY))] + "TARGET_SVE" + "@ + \t%0., %1/m, %2., %3. + \t%0., %1/m, %3., %4. + movprfx\t%0, %4\;\t%0., %1/m, %2., %3." + [(set_attr "movprfx" "*,*,yes")] +) + ;; Predicated floating-point ternary operations with merging. (define_expand "cond_" [(set (match_operand:SVE_F 0 "register_operand") (unspec:SVE_F [(match_operand: 1 "register_operand") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand") (match_operand:SVE_F 3 "register_operand") (match_operand:SVE_F 4 "register_operand")] SVE_COND_FP_TERNARY) @@ -2496,7 +2525,8 @@ (define_insn "*cond__2" (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "0, w") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand" "0, w") (match_operand:SVE_F 3 "register_operand" "w, w") (match_operand:SVE_F 4 "register_operand" "w, w")] SVE_COND_FP_TERNARY) @@ -2516,7 +2546,8 @@ (define_insn "*cond__4" (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "w, w") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand" "w, w") (match_operand:SVE_F 3 "register_operand" "w, w") (match_operand:SVE_F 4 "register_operand" "0, w")] SVE_COND_FP_TERNARY) @@ -2536,7 +2567,8 @@ (define_insn_and_rewrite "*cond_< (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl, Upl") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "w, w, w") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand" "w, w, w") (match_operand:SVE_F 3 "register_operand" "w, w, w") (match_operand:SVE_F 4 "register_operand" "w, w, w")] SVE_COND_FP_TERNARY) @@ -2561,174 +2593,6 @@ (define_insn_and_rewrite "*cond_< [(set_attr "movprfx" "yes")] ) -;; ------------------------------------------------------------------------- -;; ---- [FP] FMLA and FMAD -;; ------------------------------------------------------------------------- -;; Includes: -;; - FMAD -;; - FMLA -;; ------------------------------------------------------------------------- - -;; Unpredicated fma (%0 = (%1 * %2) + %3). -(define_expand "fma4" - [(set (match_operand:SVE_F 0 "register_operand") - (unspec:SVE_F - [(match_dup 4) - (fma:SVE_F (match_operand:SVE_F 1 "register_operand") - (match_operand:SVE_F 2 "register_operand") - (match_operand:SVE_F 3 "register_operand"))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - { - operands[4] = aarch64_ptrue_reg (mode); - } -) - -;; fma predicated with a PTRUE. -(define_insn "*fma4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") - (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (fma:SVE_F (match_operand:SVE_F 3 "register_operand" "%0, w, w") - (match_operand:SVE_F 4 "register_operand" "w, w, w") - (match_operand:SVE_F 2 "register_operand" "w, 0, w"))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - "@ - fmad\t%0., %1/m, %4., %2. - fmla\t%0., %1/m, %3., %4. - movprfx\t%0, %2\;fmla\t%0., %1/m, %3., %4." - [(set_attr "movprfx" "*,*,yes")] -) - -;; ------------------------------------------------------------------------- -;; ---- [FP] FMLS and FMSB -;; ------------------------------------------------------------------------- -;; Includes: -;; - FMLS -;; - FMSB -;; ------------------------------------------------------------------------- - -;; Unpredicated fnma (%0 = (-%1 * %2) + %3). -(define_expand "fnma4" - [(set (match_operand:SVE_F 0 "register_operand") - (unspec:SVE_F - [(match_dup 4) - (fma:SVE_F (neg:SVE_F - (match_operand:SVE_F 1 "register_operand")) - (match_operand:SVE_F 2 "register_operand") - (match_operand:SVE_F 3 "register_operand"))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - { - operands[4] = aarch64_ptrue_reg (mode); - } -) - -;; fnma predicated with a PTRUE. -(define_insn "*fnma4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") - (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (fma:SVE_F (neg:SVE_F - (match_operand:SVE_F 3 "register_operand" "%0, w, w")) - (match_operand:SVE_F 4 "register_operand" "w, w, w") - (match_operand:SVE_F 2 "register_operand" "w, 0, w"))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - "@ - fmsb\t%0., %1/m, %4., %2. - fmls\t%0., %1/m, %3., %4. - movprfx\t%0, %2\;fmls\t%0., %1/m, %3., %4." - [(set_attr "movprfx" "*,*,yes")] -) - -;; ------------------------------------------------------------------------- -;; ---- [FP] FNMLA and FNMAD -;; ------------------------------------------------------------------------- -;; Includes: -;; - FNMAD -;; - FNMLA -;; ------------------------------------------------------------------------- - -;; Unpredicated fnms (%0 = (-%1 * %2) - %3). -(define_expand "fnms4" - [(set (match_operand:SVE_F 0 "register_operand") - (unspec:SVE_F - [(match_dup 4) - (fma:SVE_F (neg:SVE_F - (match_operand:SVE_F 1 "register_operand")) - (match_operand:SVE_F 2 "register_operand") - (neg:SVE_F - (match_operand:SVE_F 3 "register_operand")))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - { - operands[4] = aarch64_ptrue_reg (mode); - } -) - -;; fnms predicated with a PTRUE. -(define_insn "*fnms4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") - (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (fma:SVE_F (neg:SVE_F - (match_operand:SVE_F 3 "register_operand" "%0, w, w")) - (match_operand:SVE_F 4 "register_operand" "w, w, w") - (neg:SVE_F - (match_operand:SVE_F 2 "register_operand" "w, 0, w")))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - "@ - fnmad\t%0., %1/m, %4., %2. - fnmla\t%0., %1/m, %3., %4. - movprfx\t%0, %2\;fnmla\t%0., %1/m, %3., %4." - [(set_attr "movprfx" "*,*,yes")] -) - -;; ------------------------------------------------------------------------- -;; ---- [FP] FNMLS and FNMSB -;; ------------------------------------------------------------------------- -;; Includes: -;; - FNMLS -;; - FNMSB -;; ------------------------------------------------------------------------- - -;; Unpredicated fms (%0 = (%1 * %2) - %3). -(define_expand "fms4" - [(set (match_operand:SVE_F 0 "register_operand") - (unspec:SVE_F - [(match_dup 4) - (fma:SVE_F (match_operand:SVE_F 1 "register_operand") - (match_operand:SVE_F 2 "register_operand") - (neg:SVE_F - (match_operand:SVE_F 3 "register_operand")))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - { - operands[4] = aarch64_ptrue_reg (mode); - } -) - -;; fms predicated with a PTRUE. -(define_insn "*fms4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") - (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (fma:SVE_F (match_operand:SVE_F 3 "register_operand" "%0, w, w") - (match_operand:SVE_F 4 "register_operand" "w, w, w") - (neg:SVE_F - (match_operand:SVE_F 2 "register_operand" "w, 0, w")))] - UNSPEC_MERGE_PTRUE))] - "TARGET_SVE" - "@ - fnmsb\t%0., %1/m, %4., %2. - fnmls\t%0., %1/m, %3., %4. - movprfx\t%0, %2\;fnmls\t%0., %1/m, %3., %4." - [(set_attr "movprfx" "*,*,yes")] -) - ;; ========================================================================= ;; == Comparisons and selects ;; =========================================================================