From patchwork Wed Aug 7 18:24:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1143618 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506442-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="lLmRdN42"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463g070R9gz9sNf for ; Thu, 8 Aug 2019 04:24:52 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=m2A5LBeiPykfA+uST9bQuxsq/CM2VP362PBalSChVL5xGFz4AW YVP6y6Guyt4aTGyQRHrr3Gjr8rU/8PuwDhlEIFvlUkFTBCf7z9DoD9MGC3vAjQUo 3xR/GLjDxNY083yfvufpSqVlU7KIeePDDZz0bAlu9niA7beZAogs3lumE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=rnldsDBt6lB/X1LfTR+LxPS9Lts=; b=lLmRdN42O3d0RI9X4slR cyU1FeI0IrY8qWgYqi3V6u4l8n+LQS0zrV32JhrHIjwzQlsU2x4leT2T+/eA0h7B 7eYMiQbsO/ZInVKd7ZW/YfN0o8Ns/rN4Ocu4tgRxGpyDnOKdIJ4GPg2pPeO/Agl8 CuPSVICC+sEc2efi5zMeMlw= Received: (qmail 57063 invoked by alias); 7 Aug 2019 18:24:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 51302 invoked by uid 89); 7 Aug 2019 18:24:32 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=quarter X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Aug 2019 18:24:30 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7A9CD28; Wed, 7 Aug 2019 11:24:20 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BAEA33F575; Wed, 7 Aug 2019 11:24:19 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, richard.sandiford@arm.com Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [AArch64] Make aarch64_classify_vector_mode use a switch statement Date: Wed, 07 Aug 2019 19:24:18 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes aarch64_classify_vector_mode used properties of a mode to test whether the mode was a single Advanced SIMD vector, a single SVE vector, or a tuple of SVE vectors. That works well for current trunk and is simpler than checking for modes by name. However, for the ACLE and for planned autovec improvements, we also need partial SVE vector modes that hold: - half of the available 32-bit elements - a half or quarter of the available 16-bit elements - a half, quarter, or eighth of the available 8-bit elements These should be packed in memory and unpacked in registers. E.g. VNx2SI has half the number of elements of VNx4SI, and so is half the size in memory. When stored in registers, each VNx2SI element occupies the low 32 bits of a VNx2DI element, with the upper bits being undefined. The upshot is that: GET_MODE_SIZE (VNx4SImode) == 2 * GET_MODE_SIZE (VNx2SImode) since GET_MODE_SIZE must always be the memory size. This in turn means that for fixed-length SVE, some partial modes can have the same size as Advanced SIMD modes. We then need to be specific about which mode we're dealing with. This patch prepares for that by switching based on the mode instead of querying properties. A later patch makes sure that Advanced SIMD modes always win over partial SVE vector modes in normal queries. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. OK to install? Richard 2019-08-07 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Switch based on the mode instead of testing properties of it. Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2019-08-07 19:17:05.931537111 +0100 +++ gcc/config/aarch64/aarch64.c 2019-08-07 19:19:52.018305243 +0100 @@ -1474,34 +1474,68 @@ aarch64_classify_vector_mode (machine_mo if (aarch64_sve_pred_mode_p (mode)) return VEC_SVE_PRED; - scalar_mode inner = GET_MODE_INNER (mode); - if (VECTOR_MODE_P (mode) - && (inner == QImode - || inner == HImode - || inner == HFmode - || inner == SImode - || inner == SFmode - || inner == DImode - || inner == DFmode)) + /* Make the decision based on the mode's enum value rather than its + properties, so that we keep the correct classification regardless + of -msve-vector-bits. */ + switch (mode) { - if (TARGET_SVE) - { - if (known_eq (GET_MODE_BITSIZE (mode), BITS_PER_SVE_VECTOR)) - return VEC_SVE_DATA; - if (known_eq (GET_MODE_BITSIZE (mode), BITS_PER_SVE_VECTOR * 2) - || known_eq (GET_MODE_BITSIZE (mode), BITS_PER_SVE_VECTOR * 3) - || known_eq (GET_MODE_BITSIZE (mode), BITS_PER_SVE_VECTOR * 4)) - return VEC_SVE_DATA | VEC_STRUCT; - } + /* Single SVE vectors. */ + case E_VNx16QImode: + case E_VNx8HImode: + case E_VNx4SImode: + case E_VNx2DImode: + case E_VNx8HFmode: + case E_VNx4SFmode: + case E_VNx2DFmode: + return TARGET_SVE ? VEC_SVE_DATA : 0; - /* This includes V1DF but not V1DI (which doesn't exist). */ - if (TARGET_SIMD - && (known_eq (GET_MODE_BITSIZE (mode), 64) - || known_eq (GET_MODE_BITSIZE (mode), 128))) - return VEC_ADVSIMD; - } + /* x2 SVE vectors. */ + case E_VNx32QImode: + case E_VNx16HImode: + case E_VNx8SImode: + case E_VNx4DImode: + case E_VNx16HFmode: + case E_VNx8SFmode: + case E_VNx4DFmode: + /* x3 SVE vectors. */ + case E_VNx48QImode: + case E_VNx24HImode: + case E_VNx12SImode: + case E_VNx6DImode: + case E_VNx24HFmode: + case E_VNx12SFmode: + case E_VNx6DFmode: + /* x4 SVE vectors. */ + case E_VNx64QImode: + case E_VNx32HImode: + case E_VNx16SImode: + case E_VNx8DImode: + case E_VNx32HFmode: + case E_VNx16SFmode: + case E_VNx8DFmode: + return TARGET_SVE ? VEC_SVE_DATA | VEC_STRUCT : 0; + + /* 64-bit Advanced SIMD vectors. */ + case E_V8QImode: + case E_V4HImode: + case E_V2SImode: + /* ...E_V1DImode doesn't exist. */ + case E_V4HFmode: + case E_V2SFmode: + case E_V1DFmode: + /* 128-bit Advanced SIMD vectors. */ + case E_V16QImode: + case E_V8HImode: + case E_V4SImode: + case E_V2DImode: + case E_V8HFmode: + case E_V4SFmode: + case E_V2DFmode: + return TARGET_SIMD ? VEC_ADVSIMD : 0; - return 0; + default: + return 0; + } } /* Return true if MODE is any of the data vector modes, including