From patchwork Wed Aug 7 18:19:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1143617 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506441-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="R9CVTn/r"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463fsr4w6Kz9sN6 for ; Thu, 8 Aug 2019 04:19:26 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=xSVN/Ul+xcdFEUPLNw30CElYbML/Sc7FqLwbyCvvAsJd+AXxcx RN28iYv/apsDb75SLL7vhWivGv1g1jA4FHBNfnrg4Ji+td47MLIH9ryLPWPYNGO/ jYzCZWlu0TZcthXFSMknNnsLFLch0AJSjeXqB1K2KTQSc7V3S6G4Qp5AM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=A4fMnbULZyLAVulDAdAv8pxErVI=; b=R9CVTn/rcE6160XUL4cu yAy0vHklQxTtAJqEnIKyIG1/KTSaoUoEbBYYkzygcdDUGwGT/7lEZYDPuLBxnvWK zOjAlHp7si1VoSWeWGTYm5xxIj2IuldXkhJ5ecjVxsmJiVXo+adkQjECOaIE+Vkc koHn6QILTrvWfczPoaN5ojY= Received: (qmail 25399 invoked by alias); 7 Aug 2019 18:19:19 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25307 invoked by uid 89); 7 Aug 2019 18:19:17 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_NUMSUBJECT, SPF_PASS autolearn=ham version=3.3.1 spammy=UD:constraints.md, predicates.md, constraints.md, constraintsmd X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Aug 2019 18:19:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E72E028; Wed, 7 Aug 2019 11:19:13 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 398413F575; Wed, 7 Aug 2019 11:19:13 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, richard.sandiford@arm.com Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [AArch64] Add a "y" constraint for V0-V7 Date: Wed, 07 Aug 2019 19:19:12 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes Some indexed SVE FCMLA operations have a 3-bit register field that requires one of Z0-Z7. This patch adds a public "y" constraint for that. The patch also documents "x", which is again intended to be a public constraint. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. OK to install? Richard 2019-08-07 Richard Sandiford gcc/ * doc/md.texi: Document the x and y constraints for AArch64. * config/aarch64/aarch64.h (FP_LO8_REGNUM_P): New macro. (FP_LO8_REGS): New reg_class. (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add an entry for FP_LO8_REGS. * config/aarch64/aarch64.c (aarch64_hard_regno_nregs) (aarch64_regno_regclass, aarch64_class_max_nregs): Handle FP_LO8_REGS. * config/aarch64/predicates.md (aarch64_simd_register): Use FP_REGNUM_P instead of checking the classes manually. * config/aarch64/constraints.md (y): New constraint. gcc/testsuite/ * gcc.target/aarch64/asm-x-constraint-1.c: New test. * gcc.target/aarch64/asm-y-constraint-1.c: Likewise. Index: gcc/doc/md.texi =================================================================== --- gcc/doc/md.texi 2019-07-12 08:54:11.881445730 +0100 +++ gcc/doc/md.texi 2019-08-07 19:17:05.935537080 +0100 @@ -1748,6 +1748,12 @@ The stack pointer register (@code{SP}) @item w Floating point register, Advanced SIMD vector register or SVE vector register +@item x +Like @code{w}, but restricted to registers 0 to 15 inclusive. + +@item y +Like @code{w}, but restricted to registers 0 to 7 inclusive. + @item Upl One of the low eight SVE predicate registers (@code{P0} to @code{P7}) Index: gcc/config/aarch64/aarch64.h =================================================================== --- gcc/config/aarch64/aarch64.h 2019-08-05 17:46:20.717723584 +0100 +++ gcc/config/aarch64/aarch64.h 2019-08-07 19:17:05.931537111 +0100 @@ -563,6 +563,9 @@ #define FP_REGNUM_P(REGNO) \ #define FP_LO_REGNUM_P(REGNO) \ (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) +#define FP_LO8_REGNUM_P(REGNO) \ + (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM)) + #define PR_REGNUM_P(REGNO)\ (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM)) @@ -581,6 +584,7 @@ enum reg_class GENERAL_REGS, STACK_REG, POINTER_REGS, + FP_LO8_REGS, FP_LO_REGS, FP_REGS, POINTER_AND_FP_REGS, @@ -600,6 +604,7 @@ #define REG_CLASS_NAMES \ "GENERAL_REGS", \ "STACK_REG", \ "POINTER_REGS", \ + "FP_LO8_REGS", \ "FP_LO_REGS", \ "FP_REGS", \ "POINTER_AND_FP_REGS", \ @@ -616,6 +621,7 @@ #define REG_CLASS_CONTENTS \ { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ + { 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \ { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2019-08-07 19:07:38.203739735 +0100 +++ gcc/config/aarch64/aarch64.c 2019-08-07 19:17:05.931537111 +0100 @@ -1610,6 +1610,7 @@ aarch64_hard_regno_nregs (unsigned regno { case FP_REGS: case FP_LO_REGS: + case FP_LO8_REGS: if (aarch64_sve_data_mode_p (mode)) return exact_div (GET_MODE_SIZE (mode), BYTES_PER_SVE_VECTOR).to_constant (); @@ -8295,7 +8296,8 @@ aarch64_regno_regclass (unsigned regno) return POINTER_REGS; if (FP_REGNUM_P (regno)) - return FP_LO_REGNUM_P (regno) ? FP_LO_REGS : FP_REGS; + return (FP_LO8_REGNUM_P (regno) ? FP_LO8_REGS + : FP_LO_REGNUM_P (regno) ? FP_LO_REGS : FP_REGS); if (PR_REGNUM_P (regno)) return PR_LO_REGNUM_P (regno) ? PR_LO_REGS : PR_HI_REGS; @@ -8585,6 +8587,7 @@ aarch64_class_max_nregs (reg_class_t reg case POINTER_AND_FP_REGS: case FP_REGS: case FP_LO_REGS: + case FP_LO8_REGS: if (aarch64_sve_data_mode_p (mode) && constant_multiple_p (GET_MODE_SIZE (mode), BYTES_PER_SVE_VECTOR, &nregs)) Index: gcc/config/aarch64/predicates.md =================================================================== --- gcc/config/aarch64/predicates.md 2019-05-12 12:27:15.753897237 +0100 +++ gcc/config/aarch64/predicates.md 2019-08-07 19:17:05.931537111 +0100 @@ -53,8 +53,7 @@ (define_predicate "aarch64_ccmp_operand" (define_predicate "aarch64_simd_register" (and (match_code "reg") - (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS") - (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS")))) + (match_test "FP_REGNUM_P (REGNO (op))"))) (define_predicate "aarch64_reg_or_zero" (and (match_code "reg,subreg,const_int") Index: gcc/config/aarch64/constraints.md =================================================================== --- gcc/config/aarch64/constraints.md 2019-03-08 18:15:38.224734558 +0000 +++ gcc/config/aarch64/constraints.md 2019-08-07 19:17:05.931537111 +0100 @@ -36,6 +36,9 @@ (define_register_constraint "Upl" "PR_LO (define_register_constraint "x" "FP_LO_REGS" "Floating point and SIMD vector registers V0 - V15.") +(define_register_constraint "y" "FP_LO8_REGS" + "Floating point and SIMD vector registers V0 - V7.") + (define_constraint "I" "A constant that can be used with an ADD operation." (and (match_code "const_int") Index: gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c 2019-08-07 19:17:05.935537080 +0100 @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +void +f (void) +{ + register float s0 asm ("s0"); + register float s7 asm ("s7"); + register float s8 asm ("s8"); + register float s15 asm ("s15"); + register float s16 asm ("s16"); + register float s31 asm ("s31"); + asm volatile ("// s0 out: %s0" : "=w" (s0)); + asm volatile ("// s0 in: %s0" :: "x" (s0)); + asm volatile ("// s7 out: %s0" : "=w" (s7)); + asm volatile ("// s7 in: %s0" :: "x" (s7)); + asm volatile ("// s8 out: %s0" : "=w" (s8)); + asm volatile ("// s8 in: %s0" :: "x" (s8)); + asm volatile ("// s15 out: %s0" : "=w" (s15)); + asm volatile ("// s15 in: %s0" :: "x" (s15)); + asm volatile ("// s16 out: %s0" : "=w" (s16)); + asm volatile ("// s16 in: %s0" :: "x" (s16)); + asm volatile ("// s31 out: %s0" : "=w" (s31)); + asm volatile ("// s31 in: %s0" :: "x" (s31)); +} + +/* { dg-final { scan-assembler {\t// s0 out: s0\n.*[/]/ s0 in: s0\n} } } */ +/* { dg-final { scan-assembler {\t// s7 out: s7\n.*[/]/ s7 in: s7\n} } } */ +/* { dg-final { scan-assembler {\t// s8 out: s8\n.*[/]/ s8 in: s8\n} } } */ +/* { dg-final { scan-assembler {\t// s15 out: s15\n.*[/]/ s15 in: s15\n} } } */ +/* { dg-final { scan-assembler {\t// s16 out: s16\n.*\tfmov\t(s[0-7]), s16\n.*[/]/ s16 in: \1\n} } } */ +/* { dg-final { scan-assembler {\t// s31 out: s31\n.*\tfmov\t(s[0-7]), s31\n.*[/]/ s31 in: \1\n} } } */ +/* { dg-final { scan-assembler-not {\t// s16 in: s16\n} } } */ +/* { dg-final { scan-assembler-not {\t// s31 in: s31\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/asm-y-constraint-1.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/asm-y-constraint-1.c 2019-08-07 19:17:05.935537080 +0100 @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +void +f (void) +{ + register float s0 asm ("s0"); + register float s7 asm ("s7"); + register float s8 asm ("s8"); + register float s15 asm ("s15"); + register float s16 asm ("s16"); + register float s31 asm ("s31"); + asm volatile ("// s0 out: %s0" : "=w" (s0)); + asm volatile ("// s0 in: %s0" :: "y" (s0)); + asm volatile ("// s7 out: %s0" : "=w" (s7)); + asm volatile ("// s7 in: %s0" :: "y" (s7)); + asm volatile ("// s8 out: %s0" : "=w" (s8)); + asm volatile ("// s8 in: %s0" :: "y" (s8)); + asm volatile ("// s15 out: %s0" : "=w" (s15)); + asm volatile ("// s15 in: %s0" :: "y" (s15)); + asm volatile ("// s16 out: %s0" : "=w" (s16)); + asm volatile ("// s16 in: %s0" :: "y" (s16)); + asm volatile ("// s31 out: %s0" : "=w" (s31)); + asm volatile ("// s31 in: %s0" :: "y" (s31)); +} + +/* { dg-final { scan-assembler {\t// s0 out: s0\n.*[/]/ s0 in: s0\n} } } */ +/* { dg-final { scan-assembler {\t// s7 out: s7\n.*[/]/ s7 in: s7\n} } } */ +/* { dg-final { scan-assembler {\t// s8 out: s8\n.*\tfmov\t(s[0-7]), s8\n.*[/]/ s8 in: \1\n} } } */ +/* { dg-final { scan-assembler {\t// s15 out: s15\n.*\tfmov\t(s[0-7]), s15\n.*[/]/ s15 in: \1\n} } } */ +/* { dg-final { scan-assembler {\t// s16 out: s16\n.*\tfmov\t(s[0-7]), s16\n.*[/]/ s16 in: \1\n} } } */ +/* { dg-final { scan-assembler {\t// s31 out: s31\n.*\tfmov\t(s[0-7]), s31\n.*[/]/ s31 in: \1\n} } } */ +/* { dg-final { scan-assembler-not {\t// s8 in: s8\n} } } */ +/* { dg-final { scan-assembler-not {\t// s15 in: s15\n} } } */ +/* { dg-final { scan-assembler-not {\t// s16 in: s16\n} } } */ +/* { dg-final { scan-assembler-not {\t// s31 in: s31\n} } } */