From patchwork Wed Aug 7 07:44:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143338 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="bWfnujpI"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463NqS1gLJz9sBF for ; Wed, 7 Aug 2019 17:46:28 +1000 (AEST) Received: from localhost ([::1]:37722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGeQ-0000tL-3O for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:46:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36393) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdZ-0000t3-L2 for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdY-0007yi-In for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:33 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:36149) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdY-0007yH-9x; Wed, 07 Aug 2019 03:45:32 -0400 Received: by mail-pl1-x641.google.com with SMTP id k8so39498441plt.3; Wed, 07 Aug 2019 00:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=LJ6f/334HjDkyHf6tr18VXYShBQB2ljOf/vOuSocRMM=; b=bWfnujpIlECRZZk9c0Gog+nCQpYrDg0Qd5MlPWmqGfL1Td3DwPEsH8Ge7RqJNG7Q4G TkS3ykvOw0sdBFPqRBRQTZyngAu/yX90RammDeETsUEdbo94ckMRjQsoO3Dgcz9C73VZ Gc0x0sOd5PqV2IyiygZQlayc2ud/DLTmrsrCWL1palBXyRRopJffYzW26GbMsOoSB/j2 dJwTnqL3QKoy8mnVg6ioIyZXtHSx2Og/OxbmUq2XQ69/5xMeeYE/m6yR+aobrOIK/GbK GoRMT3phLncXGbNbrPSMQWM8Ph24natZ9VavGctUdppKYALBC6nIwgIkCaMr1FGzd+qr EJEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=LJ6f/334HjDkyHf6tr18VXYShBQB2ljOf/vOuSocRMM=; b=F0scszN2iLjjjiBbD+6KfdFayEcIinbk2iYWnBmPrQylhk9TJmy3MUHmrgEPA+27dZ vMHy2VjwaTYT8Jv3mWgshlefEtI6HYMPQ7QZILIfSt1s8Wcq7UaRB0l6ILi70nlkSy57 JxrzQ6/WqwMhHpCQmZO8X12gfbs3307d7LnsEGKyhJuEP4XM6FYfUkSts8dHzrwUQT+V vni+gpaFoxRHmyCzfRAEd2R0zNNA84NserZOecaXq9PiUwBwTfYLJT49iqPqXSJf2XlC c9pWITqO5eCF22DVgKLaOZsGPD7fladX+p6/oeI+k77PCqzz1i/Vqs8HrWJGe1Yf4BwU +FWQ== X-Gm-Message-State: APjAAAUHcEUjW+iyPIYjpGe3gvPxrXeaqKk++XQy0jWP1uwImFok0h3x 82KG+fIOPMm6K03y9ENpQBA= X-Google-Smtp-Source: APXvYqzY/sdDffk4N1U/QWqTNfYtQFDpS+8pScQ9K+0bI6u34C8LSQAgXAcO6zcLpWMC65CnfkgKkw== X-Received: by 2002:a65:430b:: with SMTP id j11mr6489300pgq.383.1565163931129; Wed, 07 Aug 2019 00:45:31 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.30 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:30 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:44:57 -0700 Message-Id: <1565163924-18621-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 01/28] riscv: hw: Remove superfluous "linux, phandle" property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" "linux,phandle" property is optional. Remove all instances in the sifive_u and virt machine device tree. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: None hw/riscv/sifive_u.c | 3 --- hw/riscv/virt.c | 3 --- 2 files changed, 6 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 71b8083..ef36948 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -125,7 +125,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); qemu_fdt_add_subnode(fdt, intc); qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); @@ -184,7 +183,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); @@ -197,7 +195,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_GEM_CLOCK_FREQ); qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle); ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(nodename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 25faf3b..00be05a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -170,11 +170,9 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle); intc_phandle = phandle++; qemu_fdt_add_subnode(fdt, intc); qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle); - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); @@ -250,7 +248,6 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); From patchwork Wed Aug 7 07:44:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143343 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CvtGGlBy"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463NsV06vnz9s7T for ; Wed, 7 Aug 2019 17:48:12 +1000 (AEST) Received: from localhost ([::1]:37750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGg5-0004YY-MF for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:48:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36425) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdg-0000tG-KN for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdZ-0007z7-KC for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:38 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:33383) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdZ-0007yp-Cf; Wed, 07 Aug 2019 03:45:33 -0400 Received: by mail-pl1-x642.google.com with SMTP id c14so39396543plo.0; Wed, 07 Aug 2019 00:45:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=7tM4xyVOestSy3kBBPd9mEl6R57iljWAvX9IxFasqLI=; b=CvtGGlByuMjwBDXU2z72nhvl20lLeXkTMoLdSRXbJHycmPcvAH9pjEe1GkpZ/LWMXF uCio8hSNc2FBC4YIUxAJzVcgOEpS8NQ2pfnGm1i+BVlhyAAQhQ5LLGwj6TgEufSzRuAd 1mhrICUR5HaEzihVVHXMHNZknhcXs9n2GoOcNjfqZ2YRC4lYTkR7Ry+mQ7i6GHq3JFZb 4QzQr1tzNxSU3DmT59Ye4WwRjKfAH3oViPtJwZGZr5nXJfj5nqc831KS2BGKjusN5d4N VyBTMjzALOgRTEgXsm6+k6jvaT7S8cFhoTWNIvn6BWsuQrXGHJEymPskBQak4VXPs/6D Tu0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=7tM4xyVOestSy3kBBPd9mEl6R57iljWAvX9IxFasqLI=; b=QOF+3Z9UfKLQfes8S/Ddw4hR5NBizOugrxaO/R0jhSliwNaOK502FTyBFWLFbzQgjQ SSoDFFz6/e7L0IiC34CjUf6eVI+UNcS8DO8n/RA6qt3mPbvwTlSMkY2V9MPZEqb/kvo5 pjpo4XriJnLc8rEBU1r4m/TkzRteZHnGszxt9yKajwqMMnRAXaesMU1GoZu7jrCKEOou 6Ejw401sHlP06okeLckB9i3J1u7mhimBb0spvUtLfi8J6Qe95mPwesJGT9L7HQLUidm9 5pM/yiYIaSCBaEAHYIZyRO4yUzfpDh5CrIjaEVMM3GCZnmHZTZz+m4/Y9Rgo2jAU6jxM Cl9A== X-Gm-Message-State: APjAAAUSWvsxGvYByzGG9BqNj0x///mvw/LVigGng/Q4JjGSUCjhO+eZ rTXPBIMzaxU6q5LZNl9GDeBqzFXF X-Google-Smtp-Source: APXvYqwUHSLbgKcRdYLjHr3uiZjckqTXrNbHfne40zmwKlts7H/Mi2q9F1nNWWCScDhoUi/WUpj+Mw== X-Received: by 2002:a17:90a:db42:: with SMTP id u2mr7109687pjx.48.1565163932460; Wed, 07 Aug 2019 00:45:32 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.31 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:31 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:44:58 -0700 Message-Id: <1565163924-18621-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Some of the properties only have 1 cell so we should use qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells(). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: None hw/riscv/sifive_u.c | 16 ++++++++-------- hw/riscv/virt.c | 24 ++++++++++++------------ 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ef36948..623ee64 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -182,7 +182,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); - qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); @@ -207,20 +207,20 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 0x0, memmap[SIFIVE_U_GEM].size); qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", ethclk_phandle, ethclk_phandle, ethclk_phandle); qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, sizeof(ethclk_names)); - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1); - qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); g_free(nodename); nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0); + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); nodename = g_strdup_printf("/soc/uart@%lx", @@ -232,8 +232,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 0x0, memmap[SIFIVE_U_UART0].size); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_CLOCK_FREQ / 2); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 00be05a..127f005 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -233,8 +233,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, nodename = g_strdup_printf("/soc/interrupt-controller@%lx", (long)memmap[VIRT_PLIC].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", - FDT_PLIC_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", + FDT_PLIC_ADDR_CELLS); qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", FDT_PLIC_INT_CELLS); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); @@ -247,7 +247,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); - qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); @@ -260,19 +260,19 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i); g_free(nodename); } nodename = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", - FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", - FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", + FDT_PCI_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", + FDT_PCI_INT_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2); qemu_fdt_setprop_string(fdt, nodename, "compatible", "pci-host-ecam-generic"); qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); @@ -309,8 +309,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); From patchwork Wed Aug 7 07:44:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143340 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fvkrT86a"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463NqS5xQjz9sNk for ; Wed, 7 Aug 2019 17:46:28 +1000 (AEST) Received: from localhost ([::1]:37726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGeQ-0000wx-T0 for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:46:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36428) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdg-0000tI-Ke for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGda-0007zd-Ix for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:38 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:39909) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGda-0007zQ-D2; Wed, 07 Aug 2019 03:45:34 -0400 Received: by mail-pl1-x641.google.com with SMTP id b7so39533936pls.6; Wed, 07 Aug 2019 00:45:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=nQ7UK1OKdebQtMPrsxLYHhQvl+uZqfEzMCrn6Fn3aRs=; b=fvkrT86aKLCi637bZxch4mA0FiY3iGkyn5bogmAP5xLRv7NQKq+waoeBeuYDVCdUUQ 5U0YVPEwVa1cHeRyi5Eee4MDFqVWkxIUyPl6MrW6hOU+JY5rrkKF20vBIkgZFZObtu9T HieJA3+ZL2wddqlhZFdRf+vvX1Wdfg3/PCjh25LupC7cxWNCKurxa8aRdAv9FQYicOyZ zwYHrihQRoHkgTvbcBszDaWfK8QTWQEDYFupFNPdqDG2WC1rr9dGGUh58fNisa7+18o4 z2RWCigaLuT1VDIfruHQ6Ean3JojiKIJnIeC8tmP4QQRTxp4Qm54+u6JKwqxEefnEtR1 DE+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=nQ7UK1OKdebQtMPrsxLYHhQvl+uZqfEzMCrn6Fn3aRs=; b=NhLNFfJ7WcRkLFVTN93IKQt9t4K4ClbRKUyxkrqeY6pdtHxmAMQVdsJS2HtKQNDInJ bWqYI83sSIgn86je8O2Ns6FmOZPvkBZkzdkoNNFa9zs9lRlqqv3Ba13yHJlMu49iUUA3 ukxWEkyUgLfCUFuhFr/QQb98lbRXOzu3v7kTZufuc58zd7rN8Bf0hkfZbzmewMV88skn fePRYKwNUvoaYiMutO9MaqEZKgfaVQxWZaeVBaxRmMn5uW86NKfHJU7B+p5kH8+fbCoV bM3TjriCHfHNP6VTjjzT9oF18RHhy7gDQU1AQm9lVIHGiTiP55pRxCqzirL745W2C2tq 2I0g== X-Gm-Message-State: APjAAAWynFlQG2EhK9M6WgvmCrO6PC80otOCYIOOGo4CECQrewFiLAQr 9sGMx4PdxF9LF9HWX72AQ4k= X-Google-Smtp-Source: APXvYqzcFdDt9ASY+OKSmoqE0CHmxCu9w6Fz5QOpEHtXEAQOKxalBQ8r07tAdn10y8+62Wtgp7N9Vw== X-Received: by 2002:a63:1908:: with SMTP id z8mr6375517pgl.433.1565163933582; Wed, 07 Aug 2019 00:45:33 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.32 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:33 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:44:59 -0700 Message-Id: <1565163924-18621-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Group SiFive E and U cpu type defines into one header file. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- Changes in v2: None include/hw/riscv/sifive_cpu.h | 31 +++++++++++++++++++++++++++++++ include/hw/riscv/sifive_e.h | 7 +------ include/hw/riscv/sifive_u.h | 7 +------ 3 files changed, 33 insertions(+), 12 deletions(-) create mode 100644 include/hw/riscv/sifive_cpu.h diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h new file mode 100644 index 0000000..1367996 --- /dev/null +++ b/include/hw/riscv/sifive_cpu.h @@ -0,0 +1,31 @@ +/* + * SiFive CPU types + * + * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_CPU_H +#define HW_SIFIVE_CPU_H + +#if defined(TARGET_RISCV32) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 +#elif defined(TARGET_RISCV64) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 +#endif + +#endif /* HW_SIFIVE_CPU_H */ diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index d175b24..e17cdfd 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -19,6 +19,7 @@ #ifndef HW_SIFIVE_E_H #define HW_SIFIVE_E_H +#include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_gpio.h" #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" @@ -83,10 +84,4 @@ enum { #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 -#elif defined(TARGET_RISCV64) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 -#endif - #endif diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 892f0ee..4abc621 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -20,6 +20,7 @@ #define HW_SIFIVE_U_H #include "hw/net/cadence_gem.h" +#include "hw/riscv/sifive_cpu.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -77,10 +78,4 @@ enum { #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 -#elif defined(TARGET_RISCV64) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 -#endif - #endif From patchwork Wed Aug 7 07:45:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XMH7W6qw"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463NqW2P5fz9s7T for ; Wed, 7 Aug 2019 17:46:31 +1000 (AEST) Received: from localhost ([::1]:37728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGeT-00015L-CR for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:46:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36468) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdm-0000vs-7G for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdh-000824-KT for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:44 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:43738) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdg-000801-Kc; Wed, 07 Aug 2019 03:45:41 -0400 Received: by mail-pl1-x642.google.com with SMTP id 4so32482411pld.10; Wed, 07 Aug 2019 00:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=wTN0AJDzcERVkn+yvVdNI7HBH2sovcZsKQNHe872tF4=; b=XMH7W6qwjpSSKOl150eRcDqd4aHYQw+VdTaQhelobpvqSoBc76DzJ57nS+xY29n7bv pwFAmg6uGVT6WGkLBHCmYoWVUjiNOOVE8Fe6tnodjmdJToUzeTqB7oAMJez1Ia0Nx2Su G5kvoSqcNeXyTWXNNlGNoyGTijHxcy4LZI5EHzyUgcQEG3HlHpphoFKIFchvcg0cujqn yfRldpZ1iV/mc0BLgxsq7Kcb+kMjS46KTBB/TuwQp9zeb7YhdGwNtEVit0rJUv0Tktst q3MTyyoS0/r3mQGIY+OWD2vOPOhnj6+5W4ktzgX5mewNYFN045RW5xY3WkRZXIdr4mR8 eVcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=wTN0AJDzcERVkn+yvVdNI7HBH2sovcZsKQNHe872tF4=; b=oEhfzJvJa0bT+p9NfAJhJZvrYRXafnJFcC3RfpG/94YCDGks8CXVWa/8CJqnP4/pQO tZLjWyOt6lEP9KwQpP7PeaT2uOuYgFAchU0MRcF0l0nsRxKn0ZIYQHXx9cwVYJeCPF6b lePmOo7Z5k2Ya98cyaQ2vJnoNdw+N7XNi3kZLaGpsyXnoFYF10FbsnnwZ8oTKBFn5KOe CWw9wk5BCSJyBjr5cq4htFy713Z8RR3uGqQ+yYm3vDAFrD17slGxpHy3ReuKjHPySHTU SbPwNRj3nsrVUYE/g1xz7GAldgy4BeM482UaJdg8gQhhM3lQWWhKt9GNLrZt1dBhHPTR MQMA== X-Gm-Message-State: APjAAAVhlPcDTxVvTB6iD6Ot/DytLeNPqsZ5OJMOZz1Z0lf1MqLaNDfh FBBHribNqTCuFOQPt6VgOOI= X-Google-Smtp-Source: APXvYqxxt2NFe5K+T0zQPxKtv3EyjhEN8m5SdIDCdU0hwNCX15mXWinwA8Umm3MBuizWCHlQtxCcjw== X-Received: by 2002:a65:49cc:: with SMTP id t12mr6113507pgs.83.1565163934781; Wed, 07 Aug 2019 00:45:34 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.33 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:34 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:00 -0700 Message-Id: <1565163924-18621-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 04/28] riscv: hart: Extract hart realize to a separate routine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Currently riscv_harts_realize() creates all harts based on the same cpu type given in the hart array property. With current implementation it can only create symmetric harts. Exact the hart realize to a separate routine in preparation for supporting heterogeneous hart arrays. Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/riscv_hart.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index ca69a1b..3dd1c6a 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -37,26 +37,33 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } +static void riscv_hart_realize(RISCVHartArrayState *s, int hart, + char *cpu_type, Error **errp) +{ + Error *err = NULL; + + object_initialize_child(OBJECT(s), "harts[*]", &s->harts[hart], + sizeof(RISCVCPU), cpu_type, + &error_abort, NULL); + s->harts[hart].env.mhartid = hart; + qemu_register_reset(riscv_harts_cpu_reset, &s->harts[hart]); + object_property_set_bool(OBJECT(&s->harts[hart]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } +} + static void riscv_harts_realize(DeviceState *dev, Error **errp) { RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); - Error *err = NULL; int n; s->harts = g_new0(RISCVCPU, s->num_harts); for (n = 0; n < s->num_harts; n++) { - object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n], - sizeof(RISCVCPU), s->cpu_type, - &error_abort, NULL); - s->harts[n].env.mhartid = n; - qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]); - object_property_set_bool(OBJECT(&s->harts[n]), true, - "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } + riscv_hart_realize(s, n, s->cpu_type, errp); } } From patchwork Wed Aug 7 07:45:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Qp6ocBe+"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463NsV0JVCz9sBF for ; Wed, 7 Aug 2019 17:48:12 +1000 (AEST) Received: from localhost ([::1]:37746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGg5-0004Vx-4N for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:48:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36467) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdm-0000vp-70 for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdh-00082G-Lt for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:44 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:45768) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdg-00080J-Kk; Wed, 07 Aug 2019 03:45:41 -0400 Received: by mail-pl1-x642.google.com with SMTP id y8so39496546plr.12; Wed, 07 Aug 2019 00:45:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=w8z+Z4JIG+PWumqx562TA113JQMp/d8qY1uXo2FuR58=; b=Qp6ocBe+A0yFSeaPRyk8LBxHpK8z53/LlVBWJlWy3hNSHNDKoaVIPqwF4XH+tZV8wW OPv3wqCgD8QOHddsQuhFkB4LAf20XRogfWQBW8OW/CrTiOKd6whax4M2wMZw6phNVLQL LzQqu9XwWZWoVvv5HKGqa1RdMk5Yl9BTvVkPErTzKNU638BtovYeEnpD9nmw3rAL9+Qf MJGkqTUJWQGe5SEZ674Fj50Q9F3XvdG0FIqW1Rua3nBQlVreBOEvtbBIm2N3oIIiUTuB 7Tawy1ospEW1GgIGg8Yks/WQY5bMmrA5ry+nbJLWOl0nTVWXv+wqIOdunmy4UGofokpY pwxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=w8z+Z4JIG+PWumqx562TA113JQMp/d8qY1uXo2FuR58=; b=lWquDoj9T7NFYkQq9C3bu3Vxk/bhmAP0qTJUxheLybt6iVIcwofaEiP7zdAvjKS8ZV 72gSK/d0l30usWOSCTwgpYV8/QGkw0OjCjyuwc6U8A3GQyy/wIFNBN/dFp3b0KKwemqC OZyKCLxpIHRSoi4d3jfx/u8ZdfQLSwckw2DXeS/uZ36qR8zlJ1usndRf1zCHhoghuLSE 38y/4FcNIElZ0WmzpvM+GjYKJH9ngb3jvOMd9NK0oo2vXfgXOuOIhh0NB4Jo2C7uv5Dy MNlD9f0BnZ8zz5pLAToUd598wyXwPhmYpkL0Ndxs+/Y1puhbjRV2NPDHCNXfJprMPbKu RyBQ== X-Gm-Message-State: APjAAAXa2ovA1ZFcxuD2A0ug4Z2b5DpRuk6+sc1zNgFq+1BVyoV0F2DO 2swaO/vgn9ltgppopG64UVk= X-Google-Smtp-Source: APXvYqyI7/yTkpFbY00iRzjYj7OM5NbhxAL2qed5+OVOQA4LT2SCRmsJ0iSqvVINH00Uxx8Okg7cbQ== X-Received: by 2002:a17:902:8649:: with SMTP id y9mr6869661plt.289.1565163935911; Wed, 07 Aug 2019 00:45:35 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.34 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:35 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:01 -0700 Message-Id: <1565163924-18621-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts population X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" At present we only allow symmetric harts to be created. In order to support heterogeneous harts like SiFive FU540, update hart array's "cpu-type" property to allow cpu type to be set per hart, separated by delimiter ",". The frist cpu type before the delimiter is assigned to hart 0, and the second cpu type before delimiter is assigned to hart 1, and so on. If the total number of cpu types supplied in "cpu-type" property is less than number of maximum harts, the last cpu type in the property will be used to populate remaining harts. Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/riscv_hart.c | 48 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 3dd1c6a..27093e0 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -58,13 +58,55 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int hart, static void riscv_harts_realize(DeviceState *dev, Error **errp) { RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); - int n; + char *cpu_types; + char *first_type, *last_type, *tmp_type; + int n = 0; s->harts = g_new0(RISCVCPU, s->num_harts); - for (n = 0; n < s->num_harts; n++) { - riscv_hart_realize(s, n, s->cpu_type, errp); + /* we should not touch the original s->cpu_type */ + cpu_types = g_strdup(s->cpu_type); + + /* + * Expect s->cpu_type property was initialized this way: + * + * "cpu-type-a": symmetric harts + * "cpu-type-a,cpu-type-b,cpu-type-c": heterogeneous harts + * + * For heterogeneous harts, hart cpu types are separated by delimiter ",". + * The frist cpu type before the delimiter is assigned to hart 0, and the + * second cpu type before delimiter is assigned to hart 1, and so on. + * + * If the total number of cpu types is less than s->num_harts, the last + * cpu type in s->cpu_type will be used to populate remaining harts. + */ + + first_type = strtok(cpu_types, ","); + riscv_hart_realize(s, n++, first_type, errp); + tmp_type = strtok(NULL, ","); + if (!tmp_type) { + /* symmetric harts */ + for (; n < s->num_harts; n++) { + riscv_hart_realize(s, n, first_type, errp); + } + } else { + /* heterogeneous harts */ + while (tmp_type) { + if (n >= s->num_harts) { + break; + } + riscv_hart_realize(s, n++, tmp_type, errp); + last_type = tmp_type; + tmp_type = strtok(NULL, ","); + } + + /* populate remaining harts using the last cpu type in s->cpu_type */ + for (; n < s->num_harts; n++) { + riscv_hart_realize(s, n, last_type, errp); + } } + + g_free(cpu_types); } static void riscv_harts_class_init(ObjectClass *klass, void *data) From patchwork Wed Aug 7 07:45:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rgq9VRSn"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463Nv60D7lz9s7T for ; Wed, 7 Aug 2019 17:49:37 +1000 (AEST) Received: from localhost ([::1]:37774 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGhT-0007zb-S2 for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:49:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36526) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdo-0000xv-NN for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdm-00083v-7L for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:48 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:42811) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdh-00080f-Kc; Wed, 07 Aug 2019 03:45:44 -0400 Received: by mail-pl1-x644.google.com with SMTP id ay6so39528890plb.9; Wed, 07 Aug 2019 00:45:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=a1+dgctFYeYPIqDhGZ2ZM4HbB/6UXgiwmP8EAP0bHbM=; b=rgq9VRSnkSKPG07D1jg2rDxWY4EPyqp1s1BugPW9Bg49oUaJkz6hcaOjvnW0s7Wqim OsvoewlDT4IbGeTp2Ju/1xYS1JRQAyX73vzFSOc7kY7jzaZkb9IbSxLziKJUip7aq4UB 7g83T4YZ8FMNkXwcqBn2FcqGHKb0mbAvsngoNQJTzyt/9TasHaaTqUazSbrVzoAfT5Ug bXETcmn/AMjx6F4RkWfvp+l/sdTJu4b8Y4tI6MVQfgMyN+ReGjYpsgzbctKrCQ7uujLy HS2fQcWXcLdzmiosX/L7e5NcrvY8tOx2J79ozBPZT0EPhPjukQnAZKOQzv+6vj9IanKn BYWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=a1+dgctFYeYPIqDhGZ2ZM4HbB/6UXgiwmP8EAP0bHbM=; b=MSuD6PoauIABK+I7Ggsxjtc/v7XbV6xnFJmGk7zVkORNx8uea3r/3J9oGc9x7xcl0z Xd54C6biWzCOL3iWx3/E9pmT2Dlo0oyrtwL0h5dADGl5pofQcD6rA6+3UvCgq7I85Yv6 i5A5vMdN8yV2zWQXTQ7YDSc7d+YTCFs4SWZr8/dsc4dEjJ4roXzAQ49hJPGBa5fo7bHz 23PQAdwpdAybp51Axw4XXwtRPhdbcHqXr3lUTudHy4xfZEMqHB7BQoj2wukLOCX1dm4V UyAt6nOif+cAUwiCl81TR4HJ0gs/OP0IwvGRCdNCE4y+em3YVEmSuwLK+fdIQ6n+y+qN RAOQ== X-Gm-Message-State: APjAAAUDEbcvZZWhbc9OllNSv7TGr78ynQXh14WaiJjd0c9YU4VkOOtZ TP43qWOyDaLwKMqFoFT7FxU= X-Google-Smtp-Source: APXvYqyLNtEIvyokci+YzAH2Hxe+0jqB56nVUJx8TIDlVmuJwk84Fkh12VOqTzqYU/8psJH8JoPJ6w== X-Received: by 2002:a17:902:aa83:: with SMTP id d3mr6756941plr.74.1565163936971; Wed, 07 Aug 2019 00:45:36 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.35 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:36 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:02 -0700 Message-Id: <1565163924-18621-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, and pass "cpu-type" to populate heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng --- Changes in v2: - fixed the "interrupts-extended" property size hw/riscv/sifive_u.c | 40 +++++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 623ee64..821f1d5 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -10,7 +10,8 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * - * This board currently uses a hardcoded devicetree that indicates one hart. + * This board currently generates devicetree dynamically that indicates at most + * five harts. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -26,6 +27,7 @@ */ #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" @@ -117,7 +119,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_CLOCK_FREQ); - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + /* cpu 0 is the management hart that does not have mmu */ + if (cpu != 0) { + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + } qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); @@ -157,15 +162,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(nodename); plic_phandle = phandle++; - cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); + cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4 - 2); for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { nodename = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); - cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); - cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); - cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); - cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); + /* cpu 0 is the management hart that does not have S-mode */ + if (cpu == 0) { + cells[0] = cpu_to_be32(intc_phandle); + cells[1] = cpu_to_be32(IRQ_M_EXT); + } else { + cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); + cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); + cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); + cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); + } g_free(nodename); } nodename = g_strdup_printf("/soc/interrupt-controller@%lx", @@ -175,7 +186,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); + cells, (s->soc.cpus.num_harts * 4 - 2) * sizeof(uint32_t)); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_PLIC].base, 0x0, memmap[SIFIVE_U_PLIC].size); @@ -315,10 +326,16 @@ static void riscv_sifive_u_soc_init(Object *obj) { MachineState *ms = MACHINE(qdev_get_machine()); SiFiveUSoCState *s = RISCV_U_SOC(obj); + char cpu_type[64]; + + /* create cpu type representing SiFive FU540 SoC */ + pstrcpy(cpu_type, sizeof(cpu_type), SIFIVE_E_CPU); + pstrcat(cpu_type, sizeof(cpu_type), ","); + pstrcat(cpu_type, sizeof(cpu_type), SIFIVE_U_CPU); object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", + object_property_set_str(OBJECT(&s->cpus), cpu_type, "cpu-type", &error_abort); object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", &error_abort); @@ -407,10 +424,11 @@ static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc = "RISC-V Board compatible with SiFive U SDK"; mc->init = riscv_sifive_u_init; - /* The real hardware has 5 CPUs, but one of them is a small embedded power + /* + * The real hardware has 5 CPUs, but one of them is a small embedded power * management CPU. */ - mc->max_cpus = 4; + mc->max_cpus = 5; } DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) From patchwork Wed Aug 7 07:45:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143347 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="W0iEAelg"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463Nv73HyTz9sP3 for ; Wed, 7 Aug 2019 17:49:39 +1000 (AEST) Received: from localhost ([::1]:37778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGhV-00084j-GN for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:49:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36522) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdo-0000xl-Lv for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdm-00083f-6Q for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:48 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:37592) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdh-000810-K5; Wed, 07 Aug 2019 03:45:44 -0400 Received: by mail-pl1-x644.google.com with SMTP id b3so39516904plr.4; Wed, 07 Aug 2019 00:45:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=cG6I8erel++wAP2MikuwJespmoehSIDTEb7AfduoiHo=; b=W0iEAelgPtLvE+1e+xm1vXYD0S2mx4In7xWnT2ZV+Q+ae63GVMWgLo8lTzIA5vfWEG ANUUxiet8nfJHcBBJ23bXgx1Osvs3wDFuE6V2uAb3rgAzUTdcAwF1dlztZhqextMFeUx zdfG32I8wBLbjTvaM3z2088rW4hnAtANUjLUHXzh2G93bEOzXFp5yW7if1W6HQQ63DzY EMAxfmtmUeCML083UYMlqKswaItq7hx5cBQoDj093FwuN20zvgZnKvWqCkdR4i/UqaoC 6l19UIHhoM4tPYy+pekfLlxPjQYrMKVvFGwLdLcMAd7Bcj3OaMWmA1dc3oB2FJk8cFCp 6KVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=cG6I8erel++wAP2MikuwJespmoehSIDTEb7AfduoiHo=; b=tfsOcVng9bwh5osakulE0PPHeBXd3v/UHiz6eOlEe7uzisJqArvMp8bgaviRsaLW2d 7Y4759muZ9Ig21lX+pB41Vz1LioY3ukZLLTKYfO8JtQRP26xu/omTQssIdUhfF+ScX0h +WuLk24D44QrxFYyCbLtGRNYnn9qzDV3qk2Hwo46ISbQ1dCqWSvlhM3tvzlgICMP9Utu E/rkhlNmM3U9svOE3s4dnIGyoFTItsx/sxGN2Pth7x/6FPZczdbcoD1BMfbAbMmScsw4 uRFp/ZjPGg/I4tVqEq9hl+/fIRTs8aeb4iFrjN9uedq4fLlwfO2bTqfDLpaCmDJ/4FKR vSgw== X-Gm-Message-State: APjAAAXul2mtD1QGgQxMmounVLLBsyNXG8KNxl+BpaKUYTzi2JtGLRH9 TIOtEM2W+fbysLbLa1iLX+c= X-Google-Smtp-Source: APXvYqzAoEpwLOWps4JiF+uxJZ6czs+3dl8TQ1usqseWmTpOZRcJ3WzKtx1KbC3WNnLeiddBioKTaQ== X-Received: by 2002:a17:90a:3651:: with SMTP id s75mr6936754pjb.13.1565163938079; Wed, 07 Aug 2019 00:45:38 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.37 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:37 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:03 -0700 Message-Id: <1565163924-18621-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" It is not useful if we only have one management CPU. Signed-off-by: Bin Meng --- Changes in v2: - update the file header to indicate at least 2 harts are created hw/riscv/sifive_u.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 821f1d5..91f3c76 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -10,8 +10,8 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * - * This board currently generates devicetree dynamically that indicates at most - * five harts. + * This board currently generates devicetree dynamically that indicates at least + * two harts and up to five harts. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -429,6 +429,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc) * management CPU. */ mc->max_cpus = 5; + /* It is not useful if we only have one management CPU */ + mc->min_cpus = 2; } DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) From patchwork Wed Aug 7 07:45:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143354 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hoGEkF4u"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463NwS2LLBz9sBF for ; Wed, 7 Aug 2019 17:50:48 +1000 (AEST) Received: from localhost ([::1]:37806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGic-00033Z-CF for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:50:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36521) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdo-0000xj-Lt for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdm-000841-9f for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:48 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:46624) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdh-00081E-LY; Wed, 07 Aug 2019 03:45:44 -0400 Received: by mail-pl1-x643.google.com with SMTP id c2so39457513plz.13; Wed, 07 Aug 2019 00:45:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=Wi1uWTJXrzaEQAGgBpmZ9b82tg3gieSlyDYiCRVFIX8=; b=hoGEkF4u64ZPEoACNDcZREc56ok/796NVXYm3nOQ6+EOvoAUQ3BFeKIlHZIvCOshaj OY0AN1e0Hc6dnG2fiqjjTIIrC4Hm+icPVLlAK4D5I6aJjZaajvxtgmWetdABtbPXSDCy RoPvKl+LuQat8Fyx0A/hCvjbDVxZsVp8H34xk1RI0Gh6h3iEpw/kzyXmySieMn33I0mj 9j8tDd9kxpLXf4r8DGrLh4/mpoXC6/Xn/ue3xVhTiMW9zEClh7EyhAidvVDj8n3rvIJw eOiWyMjODMH+EHM9uDiqXGg+munPGn/I2HUTCp6I/br4IXi+/+edveXKZricUBBv8wbI 51Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Wi1uWTJXrzaEQAGgBpmZ9b82tg3gieSlyDYiCRVFIX8=; b=hFZHpsEORIABS0m7wQmCtR/VYnyZxzRQe+7CgB9zfWtDv4owEuzDgoRcv5tTzWBaQ7 x0qPKrer2J9LiFhM6PxpF/XEn6qtz6+XWjprbtXDbhLHR2Aah9wPcwoSwyMhREepLpnW QuBJwvvxWTXRdTXnAIkmr+XDgoQGqbD7FoGoeur5UtYsQQvpf4gJZ3k1Sum8ZAHNb+iq PKa0LXdX/jzhl35jnGF5M57Bj60UH9h2lWXeqKhNMZrGNm6fI4Dy4ZEGwCf8s8Dwy+/M XgZ4++UQaYSKcTsgcM3sKQ30E555TFyzpPTR5rw2CSqRIwGsMTIPZ8uIfF5ZeW1Hm+JC 06+Q== X-Gm-Message-State: APjAAAXoiWvLiizeJdwVjru4+QbLzbOKKwddG3iLH/AQmxwtzH2a7lw6 4Kk4n2j8ojHIe2wNSkF2fZA= X-Google-Smtp-Source: APXvYqxHEiOIhVpgpFEGYS8/ABYKXr4zkiwiZ4ehBzKOwiOkH65cVRfJSHY2hAfr4/I8rTJ2/8RcXg== X-Received: by 2002:a17:902:694a:: with SMTP id k10mr6861035plt.255.1565163939165; Wed, 07 Aug 2019 00:45:39 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.38 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:38 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:04 -0700 Message-Id: <1565163924-18621-9-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 08/28] riscv: sifive_u: Update PLIC hart topology configuration string X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" With heterogeneous harts config, the PLIC hart topology configuration string are "M,MS,.." because of the monitor hart #0. Suggested-by: Fabien Chouteau Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: None hw/riscv/sifive_u.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 91f3c76..fe8dd3e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -373,10 +373,11 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) plic_hart_config = g_malloc0(plic_hart_config_len); for (i = 0; i < ms->smp.cpus; i++) { if (i != 0) { - strncat(plic_hart_config, ",", plic_hart_config_len); + strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, + plic_hart_config_len); + } else { + strncat(plic_hart_config, "M", plic_hart_config_len); } - strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG, - plic_hart_config_len); plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); } From patchwork Wed Aug 7 07:45:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143345 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZiEnnFg1"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463NsV0rMNz9sNk for ; Wed, 7 Aug 2019 17:48:12 +1000 (AEST) Received: from localhost ([::1]:37754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGg6-0004eS-MI for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:48:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36516) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdo-0000xd-Le for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdm-000849-AL for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:48 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:34039) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdk-00081S-8N; Wed, 07 Aug 2019 03:45:46 -0400 Received: by mail-pl1-x643.google.com with SMTP id i2so39504631plt.1; Wed, 07 Aug 2019 00:45:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=GVXXIEJLxuexj6x8Bo13FQpkNePBMHrwRpuPxXgKVL8=; b=ZiEnnFg1aRBARd4kOvaJ509yBILbWWDizd927b5JSxGEW5a22TKJ9zcVyR2c6LCUR8 jkUe42aJEMUJ7yjDAsdUJvQl7z8iZDl+4WL2++5msFBE2AQXow5O1IXUEEGBBOF+cu9W c8FGQaPL3QpYvTVWLSxe//DCH8bKzoMDH9gwpfTxT2foHjvFYIriPw9ksq9K8++09dD1 y96PlfwjhQH/Sa3FOlUt4RD8TbqfyIhXL/ShcCkJCv0C+veie+DXmud7cZE3/Drpko4P MBLzbD5+sMcRtu11G2LV+YGJBH18GIO1lNSjmzYGa4AOCX7KTt8wHW4Miy94fYx+fl1w 7CXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=GVXXIEJLxuexj6x8Bo13FQpkNePBMHrwRpuPxXgKVL8=; b=Fl2AcxizCBNkG6wHTr81vgGTmfr6TJmX6p1Kk52ukxYBpJ361QZUGR0n0icpL+YS9j 1MOv8fvmZqrvG6uad2O6lUSTYK6zh7OCdub9eiyIrcM5sul+0JzMX7qDrRjl7ZSvzoXS Cao3NikK/PKEafg2FvRykqKx9iXSVrr8+DVpvAcIsvcIzCM0odw+0Q6PyUmf1zx2P9Mm eFtL+wrUocOW+b6peWhWoLMT1qWiRwqf5vAr4+LGHKhM57mDjudCyX+s4MxXsrUB65gn wTyYECj820bkc6JTIQvtsRmgyJN+ZobF3cm8PRu/eXsrVISKBBaGk7r7Af/DyQWe2UTr lhCQ== X-Gm-Message-State: APjAAAWXjc5ihTFT0OvNkEWw563sfNTsXVvQLX1c3Q3xM9flWczzUu+D KihtlqNDd3b+io2AhYoAT/E= X-Google-Smtp-Source: APXvYqzgTqd02lTb442Yp18DMKONZrCGD0PdSm27yBJOlqtvB+2miRGt/Jfz52UBUn+OBaTGeCvPQw== X-Received: by 2002:a63:2148:: with SMTP id s8mr6453028pgm.336.1565163940243; Wed, 07 Aug 2019 00:45:40 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.39 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:39 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:05 -0700 Message-Id: <1565163924-18621-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This updates the UART base address to match the hardware. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao --- Changes in v2: None hw/riscv/sifive_u.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index fe8dd3e..ea45e77 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -61,8 +61,8 @@ static const struct MemmapEntry { [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, }; From patchwork Wed Aug 7 07:45:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143353 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="RyRxYnK2"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463NwR3k6Kz9s7T for ; Wed, 7 Aug 2019 17:50:47 +1000 (AEST) Received: from localhost ([::1]:37804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGib-00031H-Io for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:50:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36584) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdq-0000yz-MR for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdo-00085W-Hi for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:50 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:43740) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdm-00082B-DA; Wed, 07 Aug 2019 03:45:46 -0400 Received: by mail-pl1-x642.google.com with SMTP id 4so32482884pld.10; Wed, 07 Aug 2019 00:45:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=+kkIV9Pb3fWIlgocrgzv3WCYT64zAV7oz/qm/72ONo8=; b=RyRxYnK2NdyVA4uMD2xs+wJlTgGMcWd289X2W1Q4vq8zoknUS5PWCWCis9nerNsWyf gkqF4Kfev/uypEIifGnq0/HhunobnufFJokqkQQoJHPwJ8QqQtJSncBx46G5djOTh232 iQHhqAL4xcTRDbnh5OVBUdHDo0gdPcyp6yp7S6FvEab6VZt08ubGZnYoMa44BfeLJcrB oVHt4Ipo5ZTMX/PgBkOyNWTtM9R7b88xkMCLFp1/xISfKPGFfNxIaSXFU4TAJcoVPZxz p0PKpmHwkcZlGuRs7VZH++plkhiqBHUZJiNgVHzOJg+x0KmQCEptj9HSI4kivIA3cT26 +qcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=+kkIV9Pb3fWIlgocrgzv3WCYT64zAV7oz/qm/72ONo8=; b=sNoYcVYhq09oIWgZepNflJidu6vffY8PdDnuGMFDiSDtROYycOlHiDlrcdohbrZwNj 2BRNZlrev5D44mGTFuJEkhNABdoEmiH0SRo/0Xe2OZHIAIk8rnUjlITAqMpezjf+tEHf b0OUWAyruk6/v8Sz6LfHb9FtjroVle5fwY6Q492OUZUKc5NUdKQZKoSOyl1neGduq2Md EIpJqS/YrLeVTGei8t3VfW9a0kjU9j0inBQhjsoWr/7cPYuVpFdMktvy69TFhuq/VY1M Z4O5j7iS4l8K6qifPng6+NYALyLzGFGFDS1pkowIj9vmArY+ai0cdEyX8gDB9ck9j3VN zc+A== X-Gm-Message-State: APjAAAV5/+U64mld4cVxD72LhKpblhdc51geT4I3hECq50ezNlZ2ybeB vVeKHO7Xg8qqXHM2Xt83lkw= X-Google-Smtp-Source: APXvYqwalnIBuczyjai0BeEtrANKbzrvAtIkD0pZT95K6jxsxwqKycJhG+BeMUITRNha95ojwH2TOQ== X-Received: by 2002:a17:90a:36a7:: with SMTP id t36mr6990707pjb.34.1565163941418; Wed, 07 Aug 2019 00:45:41 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.40 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:40 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:06 -0700 Message-Id: <1565163924-18621-11-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" sifive_u machine does not use PRCI as of today. Remove the prci header inclusion. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: None hw/riscv/sifive_u.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ea45e77..7557026 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -41,7 +41,6 @@ #include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" -#include "hw/riscv/sifive_prci.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" #include "chardev/char.h" From patchwork Wed Aug 7 07:45:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143351 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SRqIRKis"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463Nv93RnWz9sNk for ; Wed, 7 Aug 2019 17:49:41 +1000 (AEST) Received: from localhost ([::1]:37782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGhX-0008B7-Gu for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:49:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36527) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdo-0000xy-Nu for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdm-00084T-H7 for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:48 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:42813) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdm-00082h-91; Wed, 07 Aug 2019 03:45:46 -0400 Received: by mail-pl1-x643.google.com with SMTP id ay6so39529267plb.9; Wed, 07 Aug 2019 00:45:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=22OUNLHIuaiTt9aSMUQBk/o0JnEHWgUDvI8KUvBr+sQ=; b=SRqIRKis4jDiqQCnUhI0FRdJa2ZK9u+TlEAJevcNJaqvxoZsDva55jDQBW6aLM/f2E pLydbmn2SLLYqt0dA9sahonV0jYI5XrSZWI8tdr4rSw4VnyeY9VOpfuS+GyXVop7Dt4u K5XI2N30EpN1Ts/uJQBCd8AwWYvWSP3ShX4pNzKBZQoF88nFufiBQU9Ggdt1ft10sLGf 5vMKDeUEbO6CLj1nX6V2DhWxokNiyXmBOhZda2NTR/1jzvSNuPCxrfPgLy/DeguH63Hc 3kkFWE24VJN4bHArlQJlEhnz/j8BJRinmk9vDqJ3+fpQztEUIomMwx8/sTOCF8kK9Rzy LbcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=22OUNLHIuaiTt9aSMUQBk/o0JnEHWgUDvI8KUvBr+sQ=; b=BsLatY6XviNAMNNCMeajxj7GpHOyDr459ukXJ4KBfsPbE2I1MYo0t74ZNn9WBIkY/5 bsUK6fHS0IFWPw/L7EDNgjaA6pwjAAOhMK02lRxVHSpnR+OL83JdzFfiF/bVN02RPHIq eCQHGmRXaMb1gz+0zgYRzwcmjturDHEdn9YVsKxiN1U33abGXb8ilLBP73sdpfc738bK G2GuWfPNZmk7sBT4JavbEYUHnTDdtkH/7cBKKcQLlO8HIN6vieYMNXFeXqLZjXbSkC3Q FUv7N989O9Kv/CJ5dtWMGh0bk/ZcXCMLpWvuo7NJcUnsedGgrdpZdvuRuW6qQDxtgOj4 29FA== X-Gm-Message-State: APjAAAXHqO5k6eLOjg+70RUSyz5CWbyYPC2bMa60EINNWkPw8D5Ahy0Y ONDr4OM9N5gTvN1YTy6smTE= X-Google-Smtp-Source: APXvYqwSaa84Kfj1r0fbcw/qXbn1foQFKVmOceHfg6DzpbhCPErvJ1HVo3ZxuuJRuhL4jNryFCNpxA== X-Received: by 2002:a63:2bd2:: with SMTP id r201mr6453372pgr.193.1565163942533; Wed, 07 Aug 2019 00:45:42 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.41 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:41 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:07 -0700 Message-Id: <1565163924-18621-12-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao --- Changes in v2: None hw/riscv/Makefile.objs | 2 +- hw/riscv/sifive_e.c | 4 ++-- hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 14 +++++++------- include/hw/riscv/{sifive_prci.h => sifive_e_prci.h} | 14 +++++++------- 4 files changed, 17 insertions(+), 17 deletions(-) rename hw/riscv/{sifive_prci.c => sifive_e_prci.c} (90%) rename include/hw/riscv/{sifive_prci.h => sifive_e_prci.h} (82%) diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index eb9d4f9..c859697 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -2,9 +2,9 @@ obj-y += boot.o obj-$(CONFIG_SPIKE) += riscv_htif.o obj-$(CONFIG_HART) += riscv_hart.o obj-$(CONFIG_SIFIVE_E) += sifive_e.o +obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o obj-$(CONFIG_SIFIVE) += sifive_clint.o obj-$(CONFIG_SIFIVE) += sifive_gpio.o -obj-$(CONFIG_SIFIVE) += sifive_prci.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 2a499d8..2d67670 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -41,9 +41,9 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_clint.h" -#include "hw/riscv/sifive_prci.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" +#include "hw/riscv/sifive_e_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" @@ -174,7 +174,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); - sifive_prci_create(memmap[SIFIVE_E_PRCI].base); + sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); /* GPIO */ diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_e_prci.c similarity index 90% rename from hw/riscv/sifive_prci.c rename to hw/riscv/sifive_e_prci.c index f406682..acb914d 100644 --- a/hw/riscv/sifive_prci.c +++ b/hw/riscv/sifive_e_prci.c @@ -1,5 +1,5 @@ /* - * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) + * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) * * Copyright (c) 2017 SiFive, Inc. * @@ -22,7 +22,7 @@ #include "hw/sysbus.h" #include "qemu/module.h" #include "target/riscv/cpu.h" -#include "hw/riscv/sifive_prci.h" +#include "hw/riscv/sifive_e_prci.h" static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) { @@ -82,10 +82,10 @@ static const MemoryRegionOps sifive_prci_ops = { static void sifive_prci_init(Object *obj) { - SiFivePRCIState *s = SIFIVE_PRCI(obj); + SiFivePRCIState *s = SIFIVE_E_PRCI(obj); memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, - TYPE_SIFIVE_PRCI, 0x8000); + TYPE_SIFIVE_E_PRCI, 0x8000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); @@ -97,7 +97,7 @@ static void sifive_prci_init(Object *obj) } static const TypeInfo sifive_prci_info = { - .name = TYPE_SIFIVE_PRCI, + .name = TYPE_SIFIVE_E_PRCI, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(SiFivePRCIState), .instance_init = sifive_prci_init, @@ -114,9 +114,9 @@ type_init(sifive_prci_register_types) /* * Create PRCI device. */ -DeviceState *sifive_prci_create(hwaddr addr) +DeviceState *sifive_e_prci_create(hwaddr addr) { - DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI); + DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_E_PRCI); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); return dev; diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_e_prci.h similarity index 82% rename from include/hw/riscv/sifive_prci.h rename to include/hw/riscv/sifive_e_prci.h index bd51c4a..7932fe7 100644 --- a/include/hw/riscv/sifive_prci.h +++ b/include/hw/riscv/sifive_e_prci.h @@ -1,5 +1,5 @@ /* - * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface + * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface * * Copyright (c) 2017 SiFive, Inc. * @@ -16,8 +16,8 @@ * this program. If not, see . */ -#ifndef HW_SIFIVE_PRCI_H -#define HW_SIFIVE_PRCI_H +#ifndef HW_SIFIVE_E_PRCI_H +#define HW_SIFIVE_E_PRCI_H enum { SIFIVE_PRCI_HFROSCCFG = 0x0, @@ -47,10 +47,10 @@ enum { SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8) }; -#define TYPE_SIFIVE_PRCI "riscv.sifive.prci" +#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" -#define SIFIVE_PRCI(obj) \ - OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI) +#define SIFIVE_E_PRCI(obj) \ + OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_E_PRCI) typedef struct SiFivePRCIState { /*< private >*/ @@ -64,6 +64,6 @@ typedef struct SiFivePRCIState { uint32_t plloutdiv; } SiFivePRCIState; -DeviceState *sifive_prci_create(hwaddr addr); +DeviceState *sifive_e_prci_create(hwaddr addr); #endif From patchwork Wed Aug 7 07:45:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LUclFCIr"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463NsV0LPxz9sNF for ; Wed, 7 Aug 2019 17:48:12 +1000 (AEST) Received: from localhost ([::1]:37756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGg6-0004eb-WF for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:48:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36523) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdo-0000xm-Lw for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdm-00084J-Dv for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:48 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:42813) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdm-00082x-70; Wed, 07 Aug 2019 03:45:46 -0400 Received: by mail-pl1-x642.google.com with SMTP id ay6so39529321plb.9; Wed, 07 Aug 2019 00:45:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=rJ9o3PjetsKa5rb+xZapTTjmCu2Ub9mNF6ud1wfYiP0=; b=LUclFCIr+qCYp8G5hGe8bvlyBqgoGcDJaI7DTlMlCScFTdx7zyXoQw6+7LmQW0xMcr fh7/AGlFw/58V7CqAlM43SyYcVqIylSwgkTGu5cXQNBPtl0K6Yx+k4P1/Rdpp5NYEwvT sBtHPER+LKWBZ8HrXcv6ztI77VhgOkvB8b8b5t7QSW0aKxBt0G0u4pyHFkJT3xtn8KeR wLH8aQojKSHBIMtnQJ+5gHbc1gRKq3AksmIDxsIPnItaO0K8Hn8G+Bugj72D6dkJEuWL UFCUFK+ikzGYZIPLYNX1RXLs1Bn8U/KrFIzbryCNme0svZtRPUg2Mom9HJJ6gfVEKq9c wL3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=rJ9o3PjetsKa5rb+xZapTTjmCu2Ub9mNF6ud1wfYiP0=; b=iZdJ9EQiIJ7a8OrRehalHI9wtj6HyWNGKsXNIL2vtM6pE3nz/CX+5DOv9VKXP7HcS2 jbDUjNbR+51gcv4dAx5aIHdqzttwUOWXCmfCKTGTIUNmQvRTSCvSQAl+eDmiYu0FmAQT YFcfWyy74QjhrTeCKzZyardOcl1gXfRaDJ6B0ibGIRcapdgl8I3QZ8F4Jif2Taokhqvq MAxK/PnLo00aNQXHVkFxQAI+qx4cgE1QjavvHO/qwbO8gAJ2xuSiCgg43RZyyuqXWqw8 oNtc/5d225xAmQn/QxBDp2o1/m+zywrl5wccMuKuRIa+NaDHH9PB7SpcY91ZDK/iWSZW qW/A== X-Gm-Message-State: APjAAAVnOcsHcQUtYqqIDTu6oY0YnoJa1WE0ExAqM/WeHE8oLImmj2FE Vtd1WBHemFoXY0DVTmFOQbE= X-Google-Smtp-Source: APXvYqxboaP56WvyUfWBtqd6lBlGDV5tOX2cOBUI0SeayM/f6RjLyHllS/5Xf06ZPOVBfdqj6Zb4rQ== X-Received: by 2002:a63:6fcf:: with SMTP id k198mr6545857pgc.276.1565163943744; Wed, 07 Aug 2019 00:45:43 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.42 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:43 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:08 -0700 Message-Id: <1565163924-18621-13-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN for hfxosccfg register programming. Signed-off-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Philippe Mathieu-Daudé --- Changes in v2: None hw/riscv/sifive_e_prci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c index acb914d..c906f11 100644 --- a/hw/riscv/sifive_e_prci.c +++ b/hw/riscv/sifive_e_prci.c @@ -89,7 +89,7 @@ static void sifive_prci_init(Object *obj) sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); - s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); + s->hfxosccfg = (SIFIVE_PRCI_HFXOSCCFG_RDY | SIFIVE_PRCI_HFXOSCCFG_EN); s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS | SIFIVE_PRCI_PLLCFG_LOCK); s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1; From patchwork Wed Aug 7 07:45:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mx6GuIP/"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463Nv736jsz9sBF for ; Wed, 7 Aug 2019 17:49:39 +1000 (AEST) Received: from localhost ([::1]:37776 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGhV-00084K-GA for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:49:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36587) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdq-0000zD-MR for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdo-00085e-Jp for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:50 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:40960) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdm-00083I-EN; Wed, 07 Aug 2019 03:45:46 -0400 Received: by mail-pl1-x644.google.com with SMTP id m9so39339316pls.8; Wed, 07 Aug 2019 00:45:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=PYmQWfCrUBsGOKU899NdMH88IzO+9rIts3A/MmHk1JA=; b=mx6GuIP/Vm4f0NYSg0UMP04Tcknz5Dn02OMIfgBwiePzLU2dIM9o2ArdWjrUZs7YiE hNEis1gfiefal0fMOOWRCASR6r8eq0wmCND/GmRYNaimdykenRaD/OGPq2bOgtT3KVE8 +61UcPV3/EEHEEqHcx7AxVuhps2QfFpzu22Uy54oRNB5cO8g2wKfjv/yMeFp41vUwl5r SMF0B+b/dVmWoVNd6ryy9MV9INhfIb0KdgwfC3oXdqfXhwABBPr8fCXVIJD+X5Ye4HXI WQK+v4yPJIXTAfkyR76mhOKq09uUt1Vop6DS/rNfZngMewXV8fPKIX5rdf0CaSmDz1MZ aXPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=PYmQWfCrUBsGOKU899NdMH88IzO+9rIts3A/MmHk1JA=; b=rV+wjeNPdtNfZP9OUgqD9AIFTKO8BkkgQO4LzFQB61e/BRIMxglPBYUCgVr38kDZvZ ck70kyx6Sykhm/NhJ+EZSwnHJIX/nhfY+2aQSnTMUiKKaM00LCphpL9tUFri7gB1CJ2X hCs3FpWIdrBNh3sMdzeX2nsXUnuwlHo9NBbFoP5e6Wj5NNSioScKuChah2iA8u+4lQb8 MFvENix1ubuw7euHwvkkzEONKKFik25braiJAGygCvVbvfKbs6q4bn47pEQZwmI/ptH6 4IC0sD14TJGOJ+awtN0KaWvEDrNkf4VZ9bDCUlB8cRLGb5DbmZXxMJ2vvLUHxdv3E1oC VQlQ== X-Gm-Message-State: APjAAAVNBjzhFhZUF7xOzeh5yJRKVLplb8baqLmSJDz9oeYY1KGGuMV/ HZekY6BkaBtjUjE4CiX6bQY= X-Google-Smtp-Source: APXvYqwsHZF52LU1Qi18Kgh8JzreeQ3Haimxu2PjVmmZsJuO8aYLpPQBYp1N26EcCmP1aEZUyPN9YQ== X-Received: by 2002:a63:2364:: with SMTP id u36mr6328816pgm.449.1565163944899; Wed, 07 Aug 2019 00:45:44 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.43 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:44 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:09 -0700 Message-Id: <1565163924-18621-14-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/sifive_e_prci.c | 2 +- include/hw/riscv/sifive_e_prci.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c index c906f11..4cbce48 100644 --- a/hw/riscv/sifive_e_prci.c +++ b/hw/riscv/sifive_e_prci.c @@ -85,7 +85,7 @@ static void sifive_prci_init(Object *obj) SiFivePRCIState *s = SIFIVE_E_PRCI(obj); memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, - TYPE_SIFIVE_E_PRCI, 0x8000); + TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h index 7932fe7..81e506b 100644 --- a/include/hw/riscv/sifive_e_prci.h +++ b/include/hw/riscv/sifive_e_prci.h @@ -47,6 +47,8 @@ enum { SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8) }; +#define SIFIVE_E_PRCI_REG_SIZE 0x1000 + #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" #define SIFIVE_E_PRCI(obj) \ From patchwork Wed Aug 7 07:45:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143357 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="oJW4L1Q2"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463Nyw0Lvmz9s7T for ; Wed, 7 Aug 2019 17:52:56 +1000 (AEST) Received: from localhost ([::1]:37854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGkg-0006u4-4M for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:52:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36661) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGds-00011B-Ti for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdq-00087s-NY for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:52 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:37592) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdo-00084c-RH; Wed, 07 Aug 2019 03:45:50 -0400 Received: by mail-pl1-x641.google.com with SMTP id b3so39517468plr.4; Wed, 07 Aug 2019 00:45:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=sRnA4nrwp6AFiMuamcgkCBOMUL8OMOfiKsUt0uVn5sI=; b=oJW4L1Q20eHhOYLT7JUn4o/gH4Q+V3tCZRmCC1pYGOM85dwqaznA+kZ6TRBkeA70Zf gDneWEMEdKCn7oFyRKOyDu1y557RfQQakAfzTypZKtdWMrWPy2mwEsgxGtETUb8fui2n fQapNBbmiPm/uA/gYkabGGFpAymuuyee6VNPyZxQynVe5OMUl8RQ3eTTumlKxALChPlK 5JNo+AosOmBagWmsPuz3SvaZiEauq/hY+YUENwV/WDESloBODDJgaGiLwpT4PFod5tCj 8YduKCGmqve4A9MMSbJ5IGyNsu3RUQRx+dJ/hdAtLGe/F8G9KMjKIcg8e5HpvgIx1nre QtxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=sRnA4nrwp6AFiMuamcgkCBOMUL8OMOfiKsUt0uVn5sI=; b=bA2KrodjyH+O6uqRBsPvGCX0sDfzQKfA2jlpBY7MD0AmUSw9PHjQmzx5nHUwQCJ73/ b7XMc7JWUWUwJ+YpTSiDMoN8LeLUz3jzosjWsVvbIKdWHHkEYbQm2FJfGx/CkI/H8cE8 zn0KG4lscjpWDuQNeyOQRhRrXqQDs8az2ooJuddA56wbK9aI1pHT0COyXgbVKzq9Ggu9 YyUw04F3xkA4IKuhk1uKXwZZ+aJa4nH94g5YF8qgxyVspGlSL1mhuuicUkE69UcM8QQq x6+ZCvoFXwq45jsi+r/cXjC3IogfQotX8EKnOddVCMGXt9qd9mgCMrC8FbnZCLPCQzD1 DjpQ== X-Gm-Message-State: APjAAAXacu+YSbpBjBGnJU8CZUSTnQuloFzzpB4LP44Y74bewo+gDdZW kugygOzv+m6VhJ0mm/xC9fI= X-Google-Smtp-Source: APXvYqxhCyEfYRMTp3hTp9rNV8st4SV3I7Jc2+ftDNlyHPuQmHFkmpIpAtYIMNrUTW3yqCTV6/V5fA== X-Received: by 2002:a17:902:4201:: with SMTP id g1mr6963498pld.300.1565163946244; Wed, 07 Aug 2019 00:45:46 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.45 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:45 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:10 -0700 Message-Id: <1565163924-18621-15-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 14/28] riscv: sifive: Implement PRCI model for FU540 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_prci.c | 163 +++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_u_prci.h | 90 +++++++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100644 hw/riscv/sifive_u_prci.c create mode 100644 include/hw/riscv/sifive_u_prci.h diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index c859697..b95bbd5 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o +obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o obj-$(CONFIG_SIFIVE) += sifive_uart.o obj-$(CONFIG_SPIKE) += spike.o obj-$(CONFIG_RISCV_VIRT) += virt.o diff --git a/hw/riscv/sifive_u_prci.c b/hw/riscv/sifive_u_prci.c new file mode 100644 index 0000000..35e5962 --- /dev/null +++ b/hw/riscv/sifive_u_prci.c @@ -0,0 +1,163 @@ +/* + * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) + * + * Copyright (c) 2019 Bin Meng + * + * Simple model of the PRCI to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/module.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/sifive_u_prci.h" + +static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFivePRCIState *s = opaque; + + switch (addr) { + case SIFIVE_PRCI_HFXOSCCFG: + return s->hfxosccfg; + case SIFIVE_PRCI_COREPLLCFG0: + return s->corepllcfg0; + case SIFIVE_PRCI_DDRPLLCFG0: + return s->ddrpllcfg0; + case SIFIVE_PRCI_DDRPLLCFG1: + return s->ddrpllcfg1; + case SIFIVE_PRCI_GEMGXLPLLCFG0: + return s->gemgxlpllcfg0; + case SIFIVE_PRCI_GEMGXLPLLCFG1: + return s->gemgxlpllcfg1; + case SIFIVE_PRCI_CORECLKSEL: + return s->coreclksel; + case SIFIVE_PRCI_DEVICESRESET: + return s->devicesreset; + case SIFIVE_PRCI_CLKMUXSTATUS: + return s->clkmuxstatus; + } + + hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); + return 0; +} + +static void sifive_prci_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFivePRCIState *s = opaque; + + switch (addr) { + case SIFIVE_PRCI_HFXOSCCFG: + s->hfxosccfg = (uint32_t) val64; + /* OSC stays ready */ + s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY; + break; + case SIFIVE_PRCI_COREPLLCFG0: + s->corepllcfg0 = (uint32_t) val64; + /* internal feedback */ + s->corepllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE; + /* PLL stays locked */ + s->corepllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK; + break; + case SIFIVE_PRCI_DDRPLLCFG0: + s->ddrpllcfg0 = (uint32_t) val64; + /* internal feedback */ + s->ddrpllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE; + /* PLL stays locked */ + s->ddrpllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK; + break; + case SIFIVE_PRCI_DDRPLLCFG1: + s->ddrpllcfg1 = (uint32_t) val64; + break; + case SIFIVE_PRCI_GEMGXLPLLCFG0: + s->gemgxlpllcfg0 = (uint32_t) val64; + /* internal feedback */ + s->gemgxlpllcfg0 |= SIFIVE_PRCI_PLLCFG0_FSE; + /* PLL stays locked */ + s->gemgxlpllcfg0 |= SIFIVE_PRCI_PLLCFG0_LOCK; + break; + case SIFIVE_PRCI_GEMGXLPLLCFG1: + s->gemgxlpllcfg1 = (uint32_t) val64; + break; + case SIFIVE_PRCI_CORECLKSEL: + s->coreclksel = (uint32_t) val64; + break; + case SIFIVE_PRCI_DEVICESRESET: + s->devicesreset = (uint32_t) val64; + break; + case SIFIVE_PRCI_CLKMUXSTATUS: + s->clkmuxstatus = (uint32_t) val64; + break; + default: + hw_error("%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)val64); + } +} + +static const MemoryRegionOps sifive_prci_ops = { + .read = sifive_prci_read, + .write = sifive_prci_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static void sifive_prci_init(Object *obj) +{ + SiFivePRCIState *s = SIFIVE_U_PRCI(obj); + + memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, + TYPE_SIFIVE_U_PRCI, SIFIVE_U_PRCI_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + /* Initialize register to power-on-reset values */ + s->hfxosccfg = (SIFIVE_PRCI_HFXOSCCFG_RDY | SIFIVE_PRCI_HFXOSCCFG_EN); + s->corepllcfg0 = (SIFIVE_PRCI_PLLCFG0_DIVR | SIFIVE_PRCI_PLLCFG0_DIVF | + SIFIVE_PRCI_PLLCFG0_DIVQ | SIFIVE_PRCI_PLLCFG0_FSE | + SIFIVE_PRCI_PLLCFG0_LOCK); + s->ddrpllcfg0 = (SIFIVE_PRCI_PLLCFG0_DIVR | SIFIVE_PRCI_PLLCFG0_DIVF | + SIFIVE_PRCI_PLLCFG0_DIVQ | SIFIVE_PRCI_PLLCFG0_FSE | + SIFIVE_PRCI_PLLCFG0_LOCK); + s->gemgxlpllcfg0 = (SIFIVE_PRCI_PLLCFG0_DIVR | SIFIVE_PRCI_PLLCFG0_DIVF | + SIFIVE_PRCI_PLLCFG0_DIVQ | SIFIVE_PRCI_PLLCFG0_FSE | + SIFIVE_PRCI_PLLCFG0_LOCK); + s->coreclksel = SIFIVE_PRCI_CORECLKSEL_HFCLK; +} + +static const TypeInfo sifive_prci_info = { + .name = TYPE_SIFIVE_U_PRCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFivePRCIState), + .instance_init = sifive_prci_init, +}; + +static void sifive_prci_register_types(void) +{ + type_register_static(&sifive_prci_info); +} + +type_init(sifive_prci_register_types) + + +/* Create PRCI device */ +DeviceState *sifive_u_prci_create(hwaddr addr) +{ + DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_U_PRCI); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + return dev; +} diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h new file mode 100644 index 0000000..f3a4656 --- /dev/null +++ b/include/hw/riscv/sifive_u_prci.h @@ -0,0 +1,90 @@ +/* + * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2019 Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_U_PRCI_H +#define HW_SIFIVE_U_PRCI_H + +enum { + SIFIVE_PRCI_HFXOSCCFG = 0x00, + SIFIVE_PRCI_COREPLLCFG0 = 0x04, + SIFIVE_PRCI_DDRPLLCFG0 = 0x0C, + SIFIVE_PRCI_DDRPLLCFG1 = 0x10, + SIFIVE_PRCI_GEMGXLPLLCFG0 = 0x1C, + SIFIVE_PRCI_GEMGXLPLLCFG1 = 0x20, + SIFIVE_PRCI_CORECLKSEL = 0x24, + SIFIVE_PRCI_DEVICESRESET = 0x28, + SIFIVE_PRCI_CLKMUXSTATUS = 0x2C +}; + +/* + * Current FU540-C000 manual says ready bit is at bit 29, but + * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31. + * We have to trust the actual codes that worked. + * + * see https://github.com/sifive/freedom-u540-c000-bootloader + */ +enum { + SIFIVE_PRCI_HFXOSCCFG_EN = (1 << 30), + SIFIVE_PRCI_HFXOSCCFG_RDY = (1 << 31), +}; + +/* xxxPLLCFG0 register bits */ +enum { + SIFIVE_PRCI_PLLCFG0_DIVR = (1 << 0), + SIFIVE_PRCI_PLLCFG0_DIVF = (31 << 6), + SIFIVE_PRCI_PLLCFG0_DIVQ = (3 << 15), + SIFIVE_PRCI_PLLCFG0_FSE = (1 << 25), + SIFIVE_PRCI_PLLCFG0_LOCK = (1 << 31) +}; + +/* xxxPLLCFG1 register bits */ +enum { + SIFIVE_PRCI_PLLCFG1_CKE = (1 << 24) +}; + +enum { + SIFIVE_PRCI_CORECLKSEL_HFCLK = (1 << 0) +}; + +#define SIFIVE_U_PRCI_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci" + +#define SIFIVE_U_PRCI(obj) \ + OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_U_PRCI) + +typedef struct SiFivePRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t hfxosccfg; + uint32_t corepllcfg0; + uint32_t ddrpllcfg0; + uint32_t ddrpllcfg1; + uint32_t gemgxlpllcfg0; + uint32_t gemgxlpllcfg1; + uint32_t coreclksel; + uint32_t devicesreset; + uint32_t clkmuxstatus; +} SiFivePRCIState; + +DeviceState *sifive_u_prci_create(hwaddr addr); + +#endif /* HW_SIFIVE_U_PRCI_H */ From patchwork Wed Aug 7 07:45:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143359 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WW03TmlS"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463NzJ5Z9Hz9sBF for ; Wed, 7 Aug 2019 17:53:14 +1000 (AEST) Received: from localhost ([::1]:37862 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGkx-0007uZ-Up for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:53:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36656) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGds-000116-Tk for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdq-00087u-NR for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:52 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:44510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdo-00085D-Ux; Wed, 07 Aug 2019 03:45:50 -0400 Received: by mail-pl1-x643.google.com with SMTP id t14so39456656plr.11; Wed, 07 Aug 2019 00:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=hMvYW7mfGG88MHubLGvzFP/RPmVwEJ+0YkprwoOzkJI=; b=WW03TmlSydrcgWS3Ky1fiuOAaOMIeeWTxaNVA0TQ2fZJRLZnma2L8QHJfR49u8PIkB lUoOuZQltl+IKKZ41yP207R0A3uC3/jShhlQramQlGQE1J3RIuMOATJagOy/3acUBWah HQ5tmlrqNtQsW7OkjdEr8KmaFS1jjvL/141yGYscRi9AKUV/K502hdgf0N7fzWwYWVmu 6i3efgNisEQKjTrVZ0DQZCg/vUdkVMUKAimrNouVADFP3EwflaU7asgOCbDqB8OpbyvH tu7EJ3mml0R3ZE6JeFAGsdOGs8vxeUfT2ugRJrL1ahUaD/vy9isUKUWvNSn4zuBZqZ5D Qbkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=hMvYW7mfGG88MHubLGvzFP/RPmVwEJ+0YkprwoOzkJI=; b=FUVZhpQ64YwawnWihHsWrjXrpo8k9h5cRyNRPbp54AfQWUfRK9KIyxDbB7/p8kIQ9Y FN0HFTSiWgzgHc0xZy3epplF+yZKi6QdQ+ACoL2tT4fFg48iexFY4GDdlTfyzs4mpO13 +jxxtWv9nEnNy4Hf82yXzeTsnkm65CSeE8Dcs7/yR1VTSzCEFOhfe3WGaO4vBQ4eDrm2 9y5kN51AUWkRSqwTrLrlMPBn4xJzHD1OERSmrhIKfj0VSYGjHknxTcr9ZADGGbsGqPUF YT1wvQi/nTd56QIyWIrth/+NqL22BBhB4GX70t9S/jThQoUFzeRchCsrm19ZoLv1m4BB 0o9g== X-Gm-Message-State: APjAAAXu+KpI59uQ1+c7ZSYvleGJs+w6eNnHsZRkLp4XhfCOB9wqUzDp xBimPXvkchSYGYHSI9NVsbI= X-Google-Smtp-Source: APXvYqzYomUgvEMuPbWqxuH/uS3i6EHr4hpolpz4C0ocA5jyX8GpLuUfrfmDZbeRI70PCcobEv2hvg== X-Received: by 2002:aa7:957c:: with SMTP id x28mr8018677pfq.42.1565163947443; Wed, 07 Aug 2019 00:45:47 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.46 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:46 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:11 -0700 Message-Id: <1565163924-18621-16-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/sifive_u.c | 23 +++++++++++++++++++++++ include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7557026..9529154 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -77,6 +77,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, char *nodename; char ethclk_names[] = "pclk\0hclk\0tx_clk"; uint32_t plic_phandle, ethclk_phandle, phandle = 1; + uint32_t hfclk_phandle, rtcclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -95,6 +96,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + hfclk_phandle = phandle++; + nodename = g_strdup_printf("/hfclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_HFCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + + rtcclk_phandle = phandle++; + nodename = g_strdup_printf("/rtcclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_RTCCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + nodename = g_strdup_printf("/memory@%lx", (long)memmap[SIFIVE_U_DRAM].base); qemu_fdt_add_subnode(fdt, nodename); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 4abc621..bacd60f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -65,6 +65,8 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, + SIFIVE_U_HFCLK_FREQ = 33333333, + SIFIVE_U_RTCCLK_FREQ = 1000000, SIFIVE_U_GEM_CLOCK_FREQ = 125000000 }; From patchwork Wed Aug 7 07:45:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143360 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SVtTrq+w"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463P0F37G4z9sBF for ; Wed, 7 Aug 2019 17:54:05 +1000 (AEST) Received: from localhost ([::1]:37881 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGln-0001TY-Hm for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:54:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36719) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdu-00015n-5W for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGds-000898-Qf for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:54 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:33388) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdq-00086Q-Jk; Wed, 07 Aug 2019 03:45:50 -0400 Received: by mail-pl1-x642.google.com with SMTP id c14so39397566plo.0; Wed, 07 Aug 2019 00:45:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=t/G9J15KBwjj/ktXcjxNHx//GmmC2qX2xDF6hEGtdMM=; b=SVtTrq+w4h4CpFFfBlR3YX+JKnvOcELRpDdDKN7v6yIatdHFipP8mDHFzLGipyX4ws cpEL4S8XNpguuSEBqwXghZbXChslm6C3UUlt/n3T5oDywm864J6noRZVCZH10kvs/Bn8 oWuw8IDBrESa3LYiz2E+7/C+POelhXxUvz7Mqr7flsT8fK4252wkf9UOHChj8h6Ip0Yr +OetMg3cB4lnlH2+dmZWrq+eAHrY9bL8x+Ew8XoDMJZiaF19AgKE87gKE/plFio0b6pF HLB6lQAQfSWtAcgmaG4vcTCIXQ5HMh+vsmd8cUD56LSdec3IisurKUO3zQogAZrWRT+4 j0Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=t/G9J15KBwjj/ktXcjxNHx//GmmC2qX2xDF6hEGtdMM=; b=tKfT+/IdUv4gd/UVO+YMzDduvQHj9JOTdD0XpXo4O98mHF5J1Q6HzDhnpVCC/Cp19g a9ClCp7jLB1SEesQginXV/zNpvrOhqDHzsbczIpDYZaHFrMc+Bw3W0achqWjMz1wrFtr CUZjweGlg9C7PqtDGwiM37LJHnEj/qcvGBke7agdxE+FY7KjsASDrpDxVrthg4knj9AW Qa0ZV1tIBj2/mxurZ0oVCHID840h4kt9kf9iai74z4HRUxYBlyR2T2Pk0oP93Vs4ZaPB 1Y71FgeuZesCLlnJoDRX4tmx77E2I8L5AN4FJvOeHilbXoC0whu/zkfSuLP22imCJt/0 m1kw== X-Gm-Message-State: APjAAAXFHRwiH5pvA91skfGILM4Xnk/WQYs5AGl0pT8kmr3feoCDyhbg TGKziE9J4vBq9T7R8Nt+TT4= X-Google-Smtp-Source: APXvYqwIaFqC5jj+4eGxusLI0peoA5An5GknuBWV3ALbZwOztJmE5IPADiC+Bi43KBKA58DXBkyGSg== X-Received: by 2002:a17:902:da4:: with SMTP id 33mr6340868plv.209.1565163948546; Wed, 07 Aug 2019 00:45:48 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.47 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:47 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:12 -0700 Message-Id: <1565163924-18621-17-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 16/28] riscv: sifive_u: Add PRCI block to the SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/sifive_u.c | 21 ++++++++++++++++++++- include/hw/riscv/sifive_u.h | 1 + 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9529154..cab329a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -9,6 +9,7 @@ * 0) UART * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) + * 3) PRCI (Power, Reset, Clock, Interrupt) * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -42,6 +43,7 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" +#include "hw/riscv/sifive_u_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" @@ -60,6 +62,7 @@ static const struct MemmapEntry { [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, + [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, @@ -76,7 +79,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, uint32_t *cells; char *nodename; char ethclk_names[] = "pclk\0hclk\0tx_clk"; - uint32_t plic_phandle, ethclk_phandle, phandle = 1; + uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; uint32_t hfclk_phandle, rtcclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); @@ -183,6 +186,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); + prci_phandle = phandle++; + nodename = g_strdup_printf("/soc/clock-controller@%lx", + (long)memmap[SIFIVE_U_PRCI].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + hfclk_phandle, rtcclk_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_PRCI].base, + 0x0, memmap[SIFIVE_U_PRCI].size); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-prci"); + g_free(nodename); + plic_phandle = phandle++; cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4 - 2); for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { @@ -422,6 +440,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); + sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base); for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index bacd60f..19d5a6f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -51,6 +51,7 @@ enum { SIFIVE_U_MROM, SIFIVE_U_CLINT, SIFIVE_U_PLIC, + SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, SIFIVE_U_DRAM, From patchwork Wed Aug 7 07:45:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143356 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qfY40xdX"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463Nwl07H6z9s7T for ; Wed, 7 Aug 2019 17:51:03 +1000 (AEST) Received: from localhost ([::1]:37822 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGir-0003Ql-3w for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:51:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36713) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdt-00014t-UJ for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGds-00089L-RW for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:53 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:33390) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdq-00086v-Li; Wed, 07 Aug 2019 03:45:50 -0400 Received: by mail-pl1-x644.google.com with SMTP id c14so39397632plo.0; Wed, 07 Aug 2019 00:45:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=dRLa2JND76bWv7IUc9c8GfiO26glVkTf37D7H11ZvmA=; b=qfY40xdXSoOS4FUL8R+HezgB6H7ak+WahZB00+ir3O6stHU0YYmuKJvVQ3u9svihIm Km4j1V9qDnswoVD2PSwZWorEhI6RMtpojIqd8vCKZYeyRrqdUys6Mds47yU0TcwNYmW1 3IW39/07LzzCBETatcg6sVViZwfq9npjmRpKQJXRuAqUtsBe+1GL/slhpopXDwS1emKT 7v2XKpCnLa9ANfRKbrjiC6Fe4c2BAY4UpH/oPn+xoUhjLzWAv506ljkaF5/HDeq5GYLC GKu7HLc82J/OWfHuTLOhYXtEnzBp5Ibvo7tAWiDFeO3ssIBMvWZ6DVreyTS8d+W+7SPo MNeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=dRLa2JND76bWv7IUc9c8GfiO26glVkTf37D7H11ZvmA=; b=Q2QY5eVQQ46VkodqRsL69Fmsf+Ve02FBC2vE90RclxZnqR5TUzXbytQNa1riAV6O7Z 9pl3o6PiZKWkM/9hIJ1orGbKOhaZNKOSBVUX/xWh/IPWF6TvdbWERVN9rk2OE+vO3fI/ nxDFzOFJJrBt/Lfe7lT+i2orO+1eH8iTNqeSKF1lRi1IYQknjZHU6EhXHuWV5RdWfFLH B+sDxGf5F4df+N3xotQSE3AF4R2TzLzzpy1UauOoBv/McAUqA1mRty9S1I5RQ8MRtjqM fLfbX7zrusRU70/cfZS+6u9ovq7o3czqMUN8OYWV1iGGJFgHUCVXZpI5q0lMTnFs9Jew ng1Q== X-Gm-Message-State: APjAAAWgX1TdJcghBMoadDpzL7forH5S3bhJgevUYPBlVMpIoI3LR+73 J+HLoPaTHjMLt2+d348J8IE= X-Google-Smtp-Source: APXvYqzGuliqC2/LoRoKY5oDsIxqLKcRpnGzCepLb1H8PEj1rw9H0+d4koOD84n0dk6d4wj3GS3U7g== X-Received: by 2002:a17:902:b789:: with SMTP id e9mr6839650pls.294.1565163949636; Wed, 07 Aug 2019 00:45:49 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.48 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:49 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:13 -0700 Message-Id: <1565163924-18621-18-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 17/28] riscv: sifive_u: Change UART node name in device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will use this information to locate the serial node and probe its driver. However currently we generate the UART node name as "/soc/uart@...", causing U-Boot fail to find the serial node in DT. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: None hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index cab329a..bddf892 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -274,7 +274,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); - nodename = g_strdup_printf("/soc/uart@%lx", + nodename = g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_UART0].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); From patchwork Wed Aug 7 07:45:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143355 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Pu6CPeP6"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463Nwc6DKTz9s7T for ; Wed, 7 Aug 2019 17:50:56 +1000 (AEST) Received: from localhost ([::1]:37816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGik-0003Ib-VS for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:50:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36786) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdv-0001B2-RT for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdt-0008BI-4e for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:55 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:39916) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGds-00088L-Sm; Wed, 07 Aug 2019 03:45:53 -0400 Received: by mail-pl1-x643.google.com with SMTP id b7so39535120pls.6; Wed, 07 Aug 2019 00:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=NZY/KTT3dtH/V4xCN7svEcOpTwcEShhbpnGZz7sq+Yk=; b=Pu6CPeP6LRYf3wUmPHmkVnsCbxpxUbvJF80WAbyUrqpSgBaAA8eXSELNgI5WXYagrG 1pTya5mUM60YkW0ReeRLdchWDarppi0eOCDLCt3FTSt0eiOk4gGwv9as313smrYq0Z5V mV2mzTaBmUvUPVYBrrLJ4uQEoOgDVUWzflbjqhFln7SgGgkA5hUk9vudzK91NIS3LhVm YU0E6tMN69KYQE3GLFi3ezwcp95hlZtmrXnN8sgMFh9lnTSpE7QXfWOQn3M3LWdY20IM s9DfDxUEhC6YbJ0wz12qZUYmK4Nl5ssLbZZpn1Zcg7Amh6IZdftahs78arD2d4y4kuR/ E8fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=NZY/KTT3dtH/V4xCN7svEcOpTwcEShhbpnGZz7sq+Yk=; b=Di2X7kzDd+Aw5f446fefGFyL9NhaC9vD/CRdPzecAslJzFQmSA/gyzj6bI6oxc4hvu q77HX+wwjGo1kYHkWEWa2votPgcJJXgF+wJaOoJZoGumhNQDob4rhwAChZBmrRdWU6pG p9mH3hDsaLkXx4IKJvdsa9ac7FOLnQZTAkeizX0GBkGDvCp2xva1b4YNEG57FcXQeNqK 7AmEaCfyAgZEPTESTzDTvr5YrIn2uk7f40DDI0qQaYXYdStlXBlndrYpsC47ZG0+ZSPk lTR1P5trEOg1oBkWXHiNlGTeiBGULmRG5XXVWQlUwgKIZmKLJn0ESLIeRFxAggmwCVHf oOVg== X-Gm-Message-State: APjAAAWt8DYLcL9m81FYdOg45sQF9iRwdtzb/N0nt8MQmf2qQHXi+HSz ekJ6bIuzGG1htorIJXkJaTY= X-Google-Smtp-Source: APXvYqx9pjSRj5XcAS83m2WlqKcHJCmIOiGXptpadJLDDj1MbhHDxrAxQ6tsSNc7s6dpHZkwfBQOqw== X-Received: by 2002:a62:3103:: with SMTP id x3mr7829181pfx.107.1565163950852; Wed, 07 Aug 2019 00:45:50 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.49 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:50 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:14 -0700 Message-Id: <1565163924-18621-19-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 18/28] riscv: hw: Implement a model for SiFive FU540 OTP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_otp.c | 194 ++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_u_otp.h | 90 +++++++++++++++++++ 3 files changed, 285 insertions(+) create mode 100644 hw/riscv/sifive_u_otp.c create mode 100644 include/hw/riscv/sifive_u_otp.h diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index b95bbd5..fc3c6dd 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o +obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o obj-$(CONFIG_SIFIVE) += sifive_uart.o obj-$(CONFIG_SPIKE) += spike.o diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c new file mode 100644 index 0000000..f21d9f4 --- /dev/null +++ b/hw/riscv/sifive_u_otp.c @@ -0,0 +1,194 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng + * + * Simple model of the OTP to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/module.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/sifive_u_otp.h" + +static uint64_t sifive_otp_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveOTPState *s = opaque; + + switch (addr) { + case SIFIVE_OTP_PA: + return s->pa; + case SIFIVE_OTP_PAIO: + return s->paio; + case SIFIVE_OTP_PAS: + return s->pas; + case SIFIVE_OTP_PCE: + return s->pce; + case SIFIVE_OTP_PCLK: + return s->pclk; + case SIFIVE_OTP_PDIN: + return s->pdin; + case SIFIVE_OTP_PDOUT: + if ((s->pce & SIFIVE_OTP_PCE_EN) && + (s->pdstb & SIFIVE_OTP_PDSTB_EN) && + (s->ptrim & SIFIVE_OTP_PTRIM_EN)) { + return s->fuse[s->pa & SIFIVE_OTP_PA_MASK]; + } else { + return 0xff; + } + case SIFIVE_OTP_PDSTB: + return s->pdstb; + case SIFIVE_OTP_PPROG: + return s->pprog; + case SIFIVE_OTP_PTC: + return s->ptc; + case SIFIVE_OTP_PTM: + return s->ptm; + case SIFIVE_OTP_PTM_REP: + return s->ptm_rep; + case SIFIVE_OTP_PTR: + return s->ptr; + case SIFIVE_OTP_PTRIM: + return s->ptrim; + case SIFIVE_OTP_PWE: + return s->pwe; + } + + hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); + return 0; +} + +static void sifive_otp_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveOTPState *s = opaque; + + switch (addr) { + case SIFIVE_OTP_PA: + s->pa = (uint32_t) val64 & SIFIVE_OTP_PA_MASK; + break; + case SIFIVE_OTP_PAIO: + s->paio = (uint32_t) val64; + break; + case SIFIVE_OTP_PAS: + s->pas = (uint32_t) val64; + break; + case SIFIVE_OTP_PCE: + s->pce = (uint32_t) val64; + break; + case SIFIVE_OTP_PCLK: + s->pclk = (uint32_t) val64; + break; + case SIFIVE_OTP_PDIN: + s->pdin = (uint32_t) val64; + break; + case SIFIVE_OTP_PDOUT: + /* read-only */ + break; + case SIFIVE_OTP_PDSTB: + s->pdstb = (uint32_t) val64; + break; + case SIFIVE_OTP_PPROG: + s->pprog = (uint32_t) val64; + break; + case SIFIVE_OTP_PTC: + s->ptc = (uint32_t) val64; + break; + case SIFIVE_OTP_PTM: + s->ptm = (uint32_t) val64; + break; + case SIFIVE_OTP_PTM_REP: + s->ptm_rep = (uint32_t) val64; + break; + case SIFIVE_OTP_PTR: + s->ptr = (uint32_t) val64; + break; + case SIFIVE_OTP_PTRIM: + s->ptrim = (uint32_t) val64; + break; + case SIFIVE_OTP_PWE: + s->pwe = (uint32_t) val64; + break; + default: + hw_error("%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)val64); + } +} + +static const MemoryRegionOps sifive_otp_ops = { + .read = sifive_otp_read, + .write = sifive_otp_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static Property sifive_otp_properties[] = { + DEFINE_PROP_UINT32("serial", SiFiveOTPState, serial, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_otp_realize(DeviceState *dev, Error **errp) +{ + SiFiveOTPState *s = SIFIVE_U_OTP(dev); + + memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_otp_ops, s, + TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); + + /* Initialize all fuses' initial value to 0xFFs */ + memset(s->fuse, 0xff, sizeof(s->fuse)); + + /* Make a valid content of serial number */ + s->fuse[SIFIVE_OTP_SERIAL_ADDR] = s->serial; + s->fuse[SIFIVE_OTP_SERIAL_ADDR + 1] = ~(s->serial); +} + +static void sifive_otp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = sifive_otp_properties; + dc->realize = sifive_otp_realize; +} + +static const TypeInfo sifive_otp_info = { + .name = TYPE_SIFIVE_U_OTP, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveOTPState), + .class_init = sifive_otp_class_init, +}; + +static void sifive_otp_register_types(void) +{ + type_register_static(&sifive_otp_info); +} + +type_init(sifive_otp_register_types) + + +/* Create OTP device */ +DeviceState *sifive_u_otp_create(hwaddr addr, uint32_t serial) +{ + DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_U_OTP); + qdev_prop_set_uint32(dev, "serial", serial); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + return dev; +} diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h new file mode 100644 index 0000000..16095b0 --- /dev/null +++ b/include/hw/riscv/sifive_u_otp.h @@ -0,0 +1,90 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_U_OTP_H +#define HW_SIFIVE_U_OTP_H + +enum { + SIFIVE_OTP_PA = 0x00, + SIFIVE_OTP_PAIO = 0x04, + SIFIVE_OTP_PAS = 0x08, + SIFIVE_OTP_PCE = 0x0C, + SIFIVE_OTP_PCLK = 0x10, + SIFIVE_OTP_PDIN = 0x14, + SIFIVE_OTP_PDOUT = 0x18, + SIFIVE_OTP_PDSTB = 0x1C, + SIFIVE_OTP_PPROG = 0x20, + SIFIVE_OTP_PTC = 0x24, + SIFIVE_OTP_PTM = 0x28, + SIFIVE_OTP_PTM_REP = 0x2C, + SIFIVE_OTP_PTR = 0x30, + SIFIVE_OTP_PTRIM = 0x34, + SIFIVE_OTP_PWE = 0x38 +}; + +enum { + SIFIVE_OTP_PCE_EN = (1 << 0) +}; + +enum { + SIFIVE_OTP_PDSTB_EN = (1 << 0) +}; + +enum { + SIFIVE_OTP_PTRIM_EN = (1 << 0) +}; + +#define SIFIVE_OTP_PA_MASK 0xfff +#define SIFIVE_OTP_NUM_FUSES 0x1000 +#define SIFIVE_OTP_SERIAL_ADDR 0xfc + +#define SIFIVE_U_OTP_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" + +#define SIFIVE_U_OTP(obj) \ + OBJECT_CHECK(SiFiveOTPState, (obj), TYPE_SIFIVE_U_OTP) + +typedef struct SiFiveOTPState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t pa; + uint32_t paio; + uint32_t pas; + uint32_t pce; + uint32_t pclk; + uint32_t pdin; + uint32_t pdstb; + uint32_t pprog; + uint32_t ptc; + uint32_t ptm; + uint32_t ptm_rep; + uint32_t ptr; + uint32_t ptrim; + uint32_t pwe; + uint32_t fuse[SIFIVE_OTP_NUM_FUSES]; + /* config */ + uint32_t serial; +} SiFiveOTPState; + +DeviceState *sifive_u_otp_create(hwaddr addr, uint32_t serial); + +#endif /* HW_SIFIVE_U_OTP_H */ From patchwork Wed Aug 7 07:45:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CKeDV0BM"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463P1h6C6Fz9s7T for ; Wed, 7 Aug 2019 17:55:20 +1000 (AEST) Received: from localhost ([::1]:37910 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGn0-0004AH-Ts for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:55:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36767) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdv-000197-A6 for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdt-0008BA-2u for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:55 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:40794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGds-00088p-S7; Wed, 07 Aug 2019 03:45:53 -0400 Received: by mail-pl1-x642.google.com with SMTP id a93so39421442pla.7; Wed, 07 Aug 2019 00:45:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=irnIasjoPryyn6PeGNluzSnHr2iiYTUs2FFgMVWmq5s=; b=CKeDV0BM0hnPzmC2G4IQT5a96E5acqVLco5LqgrD4xmbRfezZEMyQppx9Uj0b3fqZV OqnsChTxnE3HT+zDvIsib8h7KR+PRnJL5rjOfmJKgB7J9Xe8dBaF2l2nYFPnQ4LLLx7D zpTzeHDomjgBL45jaq6lN+KLIATDeQ10QT8gviFLfoWuKr6jlq6hi1BixvM5mh+8h+Pz mnZmFDitxxN3DAzowF1HjuTKptX571BMsSl0BY/8Lhwv88p6cXiZcPAfj51xcA22+RYo WAFOyfsiflz7NFQlmCiI2KaTYsZ+smxgVK/AJpCifzc5qTJkSbgQb5S//1d2bAoUCmEY 1JOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=irnIasjoPryyn6PeGNluzSnHr2iiYTUs2FFgMVWmq5s=; b=Vu6bi1+r1Ao/9sUDD9OrnGqVI5upvn5PHLoQ150PWY0P545CkhjyV1kd3Ky9enJrKv k0uvegC0Xus6t3nN3/+is+HEfMjVFSkrTg2vvszUVwQB4bEtLIWaXpk2q4CtSl8FDbKD D92bUzOaDpV9nUuEjsZvGVcwp1oO92aH82wPOIfJfM2BRjLkFiFxdEdscEQoLsHRO0Gi j587v9FIMnnkz1Fmp9Wb+GEPicrTA0Nqj2S01ov+jVv5K3PgKNMX9b2vhB+UOCCeCRBH 1/uqfDA8NoqgDYWfooaFeA28hCqg4NGwOSHz2LjyTY5VlwHQ5Ofvtm42f/oDEMYa0YoU 5yuA== X-Gm-Message-State: APjAAAXhKvgtE7XH+G8yJAm1zlkWFNtenXND/VCos4nWa8QR/d/jIAgD rqbzHvp1d4JFkS3OlkiiCYs= X-Google-Smtp-Source: APXvYqztIJcN+D79X0pPGqjRS+hYzRRiNh9s11NMB0L9Pma6DCrQZ/u4zzcky3xVdGax3n7JPrTe1g== X-Received: by 2002:a17:902:2987:: with SMTP id h7mr6874236plb.37.1565163951985; Wed, 07 Aug 2019 00:45:51 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.50 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:51 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:15 -0700 Message-Id: <1565163924-18621-20-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/sifive_u.c | 5 +++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 6 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bddf892..7b4a684 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -10,6 +10,7 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * 3) PRCI (Power, Reset, Clock, Interrupt) + * 4) OTP (One-Time Programmable) memory with stored serial number * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -43,6 +44,7 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" +#include "hw/riscv/sifive_u_otp.h" #include "hw/riscv/sifive_u_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" @@ -65,10 +67,12 @@ static const struct MemmapEntry { [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, + [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, }; +#define SIFIVE_OTP_SERIAL 1 #define GEM_REVISION 0x10070109 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, @@ -441,6 +445,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base); + sifive_u_otp_create(memmap[SIFIVE_U_OTP].base, SIFIVE_OTP_SERIAL); for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 19d5a6f..2f475c5 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -54,6 +54,7 @@ enum { SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, + SIFIVE_U_OTP, SIFIVE_U_DRAM, SIFIVE_U_GEM }; From patchwork Wed Aug 7 07:45:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143362 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="jdDsOGUS"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463P0b0bwcz9sBF for ; Wed, 7 Aug 2019 17:54:23 +1000 (AEST) Received: from localhost ([::1]:37890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGm5-0002Go-3J for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:54:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36813) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdw-0001DY-Ls for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdv-0008Cy-99 for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:56 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:33390) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdv-0008CS-2C; Wed, 07 Aug 2019 03:45:55 -0400 Received: by mail-pl1-x641.google.com with SMTP id c14so39397942plo.0; Wed, 07 Aug 2019 00:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=iTctY9qvWpXmxPkVyXSKVQceUtv+x2qlyz/k9SkFORE=; b=jdDsOGUSDqd75IqncBV29Pysbgdccgk3HzavyqWibGvW8Iohme5ToAM+z/1rqZRopw arxcKL4/OK4iTY57CsSj6vujrckdQagVmluPZbE1fcsAQhP6P5InTjhEk9G/JtkAh+9+ uO9n5U0vJ96sln5Syex4tamd4QufPbf5S8pxvameTQRUzTo+gVyHrD/2HN0fOnWqbUtz 54EstziCtS7Tf1tmgtYtUIL47wpYoxcPrbDE6DH1DkZEi8AzxNFHFA7e3sNgWG761GfQ eVFDqB2S9aNLIQv/5kyzOhqsQFpGHP0Ak4ua6h7WFSINUpbiH6a5eQ+dmv5SdFqRcToY H4Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=iTctY9qvWpXmxPkVyXSKVQceUtv+x2qlyz/k9SkFORE=; b=E+UaCMQE5+GpETdxpiHSN7td4o6jzyOynIvOOLvIEXg6PRWpPfAdN55dJ3+O456DpR KhvpKACZ72vpRlGo9+i1II/S9b1m/IcOqAHiqP9nccrnG5WSpMWHTurE8M63Zoxt9w8N gKU+ZZagO+1rnNQ4HncJGAd7Nqwr+Lzat5ujcXhOxkEFrCDTZSj4GFJOVl4yeND2dYT2 7UG5ja9bV5ywyqTNUHMNZPKxAgPLejaG7Bry+1o3UEmNndMHY025cec62mLVt5UjaRdw 5aCt4d41+UBzKDe2eHdIPu13hv4E/9DmuHamcNuvlKXn7guRpmnwmiEfFddlfAQPnZ12 DKxQ== X-Gm-Message-State: APjAAAWccj2A4v/ZScSsc8tqr2DwCbpTAmXhgXNB8lHc2aceQZenuCcl Rn0sDl0iSZ1SUGDy7n/RuMs= X-Google-Smtp-Source: APXvYqxsdSd/rhwvc/yD2JpW/hEAwD3HfXUxaremWIMGKl6rkYFAIfm5xtVDGJBSBWHJESDv7hD3ag== X-Received: by 2002:a17:902:8f81:: with SMTP id z1mr6825808plo.290.1565163954338; Wed, 07 Aug 2019 00:45:54 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.53 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:53 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:17 -0700 Message-Id: <1565163924-18621-22-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 21/28] riscv: sifive_u: Update UART and ethernet node clock properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that we have added PRCI nodes, update existing UART and ethernet nodes to use PRCI as their clock sources, to keep in sync with the Linux kernel device tree. With above changes, the previously handcrafted "/soc/ethclk" node is no longer needed. Remove it. Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/sifive_u.c | 21 +++++---------------- include/hw/riscv/sifive_u.h | 3 +-- include/hw/riscv/sifive_u_prci.h | 10 ++++++++++ 3 files changed, 16 insertions(+), 18 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7b4a684..fb4845c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -82,8 +82,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, int cpu; uint32_t *cells; char *nodename; - char ethclk_names[] = "pclk\0hclk\0tx_clk"; - uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; + char ethclk_names[] = "pclk\0hclk"; + uint32_t plic_phandle, prci_phandle, phandle = 1; uint32_t hfclk_phandle, rtcclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); @@ -242,17 +242,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); - ethclk_phandle = phandle++; - nodename = g_strdup_printf("/soc/ethclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_GEM_CLOCK_FREQ); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); - ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); @@ -265,7 +254,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", - ethclk_phandle, ethclk_phandle, ethclk_phandle); + prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, sizeof(ethclk_names)); qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); @@ -285,8 +274,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_UART0].base, 0x0, memmap[SIFIVE_U_UART0].size); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_CLOCK_FREQ / 2); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2f475c5..0461331 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -68,8 +68,7 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, SIFIVE_U_HFCLK_FREQ = 33333333, - SIFIVE_U_RTCCLK_FREQ = 1000000, - SIFIVE_U_GEM_CLOCK_FREQ = 125000000 + SIFIVE_U_RTCCLK_FREQ = 1000000 }; #define SIFIVE_U_PLIC_HART_CONFIG "MS" diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h index f3a4656..640c641 100644 --- a/include/hw/riscv/sifive_u_prci.h +++ b/include/hw/riscv/sifive_u_prci.h @@ -87,4 +87,14 @@ typedef struct SiFivePRCIState { DeviceState *sifive_u_prci_create(hwaddr addr); +/* + * Clock indexes for use by Device Tree data and the PRCI driver. + * + * These values are from sifive-fu540-prci.h in the Linux kernel. + */ +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + #endif /* HW_SIFIVE_U_PRCI_H */ From patchwork Wed Aug 7 07:45:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143365 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="T4OaPej8"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463P260j4dz9s7T for ; Wed, 7 Aug 2019 17:55:42 +1000 (AEST) Received: from localhost ([::1]:37930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGnM-0004zM-41 for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:55:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36849) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdx-0001G5-IV for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdw-0008Du-ET for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:57 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:44513) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdw-0008DW-8A; Wed, 07 Aug 2019 03:45:56 -0400 Received: by mail-pl1-x642.google.com with SMTP id t14so39457220plr.11; Wed, 07 Aug 2019 00:45:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=4sBZOy54i7FwospnAgzS66UMgmogyqri0jjg65m7Jmg=; b=T4OaPej8EYBlFG523BLm+sYaxJ4oum25P23a0E55r5tYoWCmaly3cZw209efW4znID uQ5oeTfJ18uaxEWQvsT3cm18Qw+qkRP/QAcumnCbRY79GTucUemXgPIgsLdBoaQ0rMO6 Pzl9XribMMPFM4PtgvIaIf4WMb+kkoqdh9jaK56oisDu4X4klDMyqVnM3Cg0vSyyPDtX X7m2r3Pf86Sw2U+QxiKWEe4av3BuapNKh/LR/nyYmW36spul1bXYlfiJzSNACld+RvTd 2bAQoPs5N/YPvvN5ZgD1PE/6QsVTG60UtglK8B1S2Nsqxdq3Fzf7cWI1S9c1fiqfmFJE vc4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=4sBZOy54i7FwospnAgzS66UMgmogyqri0jjg65m7Jmg=; b=mt9Wsa6+I0GuWoVk8JuwPz8deTUSWM4/l6Q3YfzPFrgsU7aBszaR6SKu4bWRQqknA0 TGgbEXXoYfiPv/4EJlobvheQNIcVjvkUCT/kXTpkXNlEVLe7P3zBXxUEj0uCwDLpzJt3 5A8EmKjxLAebbMIuoa8uIXM59d6EKs5XAJzf3wej67NRJ7lnEZa+dsQVEPhdktxejjJM Y0Ob0Rs0Dm38ntzq9uHQwAKsAt077gtdVYZjhVZJxl1aUcBLYBRVxohVao7JDqsZfVts UihHONZH7/MPEhR12xgwZblv/4TX3lSS9An/jcwOBxUwMLIgB3JdKDb4UafOXj5LzLgM sQ6w== X-Gm-Message-State: APjAAAUcUS2N6FzwstjT4QycD0tK0J8CPoJZ37wG1Yg+0SVoMh0NKs95 uKfPyGjPtPS/lhNQYjPgw/E= X-Google-Smtp-Source: APXvYqy2autF5vGFvA9bkoasbcY5aluqTVz8cLI2on4ol/oOHm7U6DImL8alIMgNemSBYvBpvXPWTQ== X-Received: by 2002:a17:902:7283:: with SMTP id d3mr6800715pll.93.1565163955394; Wed, 07 Aug 2019 00:45:55 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.54 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:54 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:18 -0700 Message-Id: <1565163924-18621-23-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 22/28] riscv: sifive_u: Generate an aliases node in the device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The Linux kernel SiFive UART driver expects an aliases node to be present in the device tree, from which the driver extracts the port number from "serial#" in the aliases node. Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/sifive_u.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index fb4845c..8218cdd 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -284,6 +284,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, if (cmdline) { qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } + qemu_fdt_add_subnode(fdt, "/aliases"); + qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); g_free(nodename); } From patchwork Wed Aug 7 07:45:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143358 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="P6fX2EFU"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463Nyw3Q5hz9sBF for ; Wed, 7 Aug 2019 17:52:56 +1000 (AEST) Received: from localhost ([::1]:37856 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGkg-0006vF-Hb for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:52:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36893) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdz-0001LR-HF for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:46:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdx-0008En-Ib for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:59 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:37596) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdx-0008EJ-85; Wed, 07 Aug 2019 03:45:57 -0400 Received: by mail-pl1-x642.google.com with SMTP id b3so39518151plr.4; Wed, 07 Aug 2019 00:45:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=k/MAfYxDy/xn/xAFZ7zsPvNNLeZK97yMtxrB45BQ/Ec=; b=P6fX2EFUGkiOAzoCuUJH9dlipjcjusg9prLzdbr+8Z4HtTYXMAfS6J2SWd5py7ljTZ XPrKxLvWM5BL+KkYGNMQL1BzAiBV8mz9X6cWfYxHI5iNVw4mhQJ8nRRIs8dnyAAtmi3d oGePygd0pJyh2FWFFnSyO+Nr+1dCAYh9gLOU/CMDcCzim3mjT6CcKpP4GqPs+8e80DK7 bDggrC6CxJpe7lvifserLVbukZunWXAHYOnixbC8auWZYtIASR7fTr8nLdlmfXVM7RKy X5hsAkl4yGuIkrrNaTd/bA0O7u/+93R+mZEC0PLRtiTrSrB06mrhDcIyoV26+BpcKeJX z+Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=k/MAfYxDy/xn/xAFZ7zsPvNNLeZK97yMtxrB45BQ/Ec=; b=a4FdpW9fDSuKPcyZWLiHNS++T5xNRRM6uk5ZuaGqtogStjT4ZiIRo5nrxROmdDpTNT mT2Ax/2GN3qMmvPKaU6lcZ9pzQCIex0mcYVdeiwtd9VqimKMCi1xM7NXnxTnIqub1sCy lz97oFAWG16uHNtwytR7kcACZqGn2OAHFMCMnJPxPIx5uuX1ttePWds0twMTa+wD4vIW GveUkXpebh8BGB68lf2IfSQX9kxfxezevJvEGw1zj+jj2GuXkKaJS4QV+TLon6dzM3hR Lk8CCCSi7KAEifBTu4K1cRSO7HLgNbK6xVHHMMgQ/ROyst5S/Fst5ZCC2xkFrjDyBbUp ipKw== X-Gm-Message-State: APjAAAXpgGu729W53WISJx6BTWNp/hU3JbpA0Xfw1Lu8Nq/zg9YlM1yk LPjgGe3Mn07AiAd8Yt94SQ8= X-Google-Smtp-Source: APXvYqyN9OrJcs/crx7jqvFRkUZZJKB/DfSZvPJqpZLaf6RuhtfFF1A7nhJgIn2E0/jHptdnxGe2Sw== X-Received: by 2002:a17:902:204:: with SMTP id 4mr6824493plc.178.1565163956439; Wed, 07 Aug 2019 00:45:56 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.55 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:55 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:19 -0700 Message-Id: <1565163924-18621-24-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 23/28] riscv: sifive_u: Fix broken GEM support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" At present the GEM support in sifive_u machine is seriously broken. - The GEM block register base was set to a weird number (0x100900FC), which for no way could work with the cadence_gem model in QEMU. - The generated DT node for GEM has a "clocks-names" which is an invalid property name. Not like other GEM variants, the FU540-specific GEM has a management block to control 10/100/1000Mbps link speed changes, that is mapped to 0x100a0000. We can simply map it into MMIO space without special handling using create_unimplemented_device(). Update the GEM node compatible string to use the official name used by the upstream Linux kernel, and add the management block reg base & size to the property encoding. Tested with upstream U-Boot and Linux kernel MACB drivers. Signed-off-by: Bin Meng --- Changes in v2: - use create_unimplemented_device() to create the GEM management block instead of sifive_mmio_emulate() - add "phy-handle" property to the ethernet node hw/riscv/sifive_u.c | 23 ++++++++++++++++++----- include/hw/riscv/sifive_u.h | 3 ++- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 8218cdd..ce6eba5 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -3,6 +3,7 @@ * * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Bin Meng * * Provides a board compatible with the SiFive Freedom U SDK: * @@ -11,6 +12,7 @@ * 2) PLIC (Platform Level Interrupt Controller) * 3) PRCI (Power, Reset, Clock, Interrupt) * 4) OTP (One-Time Programmable) memory with stored serial number + * 5) GEM (Gigabit Ethernet Controller) and management block * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -38,6 +40,7 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "hw/char/serial.h" +#include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" @@ -69,7 +72,8 @@ static const struct MemmapEntry { [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, - [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, + [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, + [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, }; #define SIFIVE_OTP_SERIAL 1 @@ -84,7 +88,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, char *nodename; char ethclk_names[] = "pclk\0hclk"; uint32_t plic_phandle, prci_phandle, phandle = 1; - uint32_t hfclk_phandle, rtcclk_phandle; + uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -242,20 +246,25 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); + phy_phandle = phandle++; nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb"); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-gem"); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_GEM].base, - 0x0, memmap[SIFIVE_U_GEM].size); + 0x0, memmap[SIFIVE_U_GEM].size, + 0x0, memmap[SIFIVE_U_GEM_MGMT].base, + 0x0, memmap[SIFIVE_U_GEM_MGMT].size); qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); + qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); - qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, + qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, sizeof(ethclk_names)); qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); @@ -264,6 +273,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); @@ -456,6 +466,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, plic_gpios[SIFIVE_U_GEM_IRQ]); + + create_unimplemented_device("riscv.sifive.u.gem-mgmt", + memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } static void riscv_sifive_u_machine_init(MachineClass *mc) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 0461331..e92f1aa 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -56,7 +56,8 @@ enum { SIFIVE_U_UART1, SIFIVE_U_OTP, SIFIVE_U_DRAM, - SIFIVE_U_GEM + SIFIVE_U_GEM, + SIFIVE_U_GEM_MGMT }; enum { From patchwork Wed Aug 7 07:45:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fvOU2b5G"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463P3F1xzHz9s7T for ; Wed, 7 Aug 2019 17:56:41 +1000 (AEST) Received: from localhost ([::1]:37952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGoJ-0007XM-C5 for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:56:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36892) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGdz-0001LE-Fh for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:46:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdy-0008FS-FZ for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:45:59 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:34043) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdy-0008Ex-7r; Wed, 07 Aug 2019 03:45:58 -0400 Received: by mail-pl1-x642.google.com with SMTP id i2so39505839plt.1; Wed, 07 Aug 2019 00:45:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=++PxAHxQgFZf8IyF1BGk/O95LoL/ngMnCoTtc4g0wvo=; b=fvOU2b5G7Fn4yreeUSmOZWhPFpAb80Ab8ytG8FEdMh38P80XKIcE/OV2rt6jo4Fga6 r5jMzKb2b3UtQGqK4FdPEgsupLJI4idFnF1hJaWBP7m+b/ilLm4v7bIRkQcaXEJ1KzMM dnin1pjQ5e/SiqgAoJRIs9gBKh2WfqfWzzfqi82+jcw33tuhpwTPh1hQTX+/Cu9ITH9A BZMOgwKzUYqIUHKqEnam1l7aY/cdQnpWgM/bOI/Lmr1vDlsx1tTGX0PjY8TzrTZ96duu 05Z/mv71QBuD95D7/GSAEQLdnqU1zuLRGyTdl/E15U4nm64GKrQS9sP013Pa2t6zXr6D CqNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=++PxAHxQgFZf8IyF1BGk/O95LoL/ngMnCoTtc4g0wvo=; b=q7wbSlK6fVZhPxFNbi/wzOHrFoMzUDoXt6GceIEdlGhGf6JpKOeZdFY6K+82Dmb4DB 6Xrgc00ZxIOeRCr4EPbl1bYb+7HpxQ/K71acxJ8a3ZIIm/EivVzRiDTfIy31GbfRd0sA KtyhOxeD/bErSlFFKwWPgfrkAmuiXqUGVEyHlL+Krm7wK/2QgJDVJ0/gF+XyFYJoKdXN bNkh39v18LtJYM3A+3IjIh8E6D6b0YgEpRuIl1RjbG2eSbcA9X0xLmPtMj5+tIClyHFJ 4aVCr/pxmNVb9c6SZp4LG5bnzumFUYVH6heGwEY0MbXgCnhtNVxOeuKkMGm+iM5Ae+xF 0RDg== X-Gm-Message-State: APjAAAXC/YfycallARaUBmku5Ifw3jH1CxdCmyhVHnj6l/9+qcKlqmSs I7KlRJuq325oTk+E1Esj1fM= X-Google-Smtp-Source: APXvYqyr1PduyJmCzUkySTrPTWD9ZFg9tqHu8eYkwq7q7kA4lOfth/MNZvtCfba5wM6AEnuyRO2RZQ== X-Received: by 2002:a17:902:7791:: with SMTP id o17mr7040085pll.27.1565163957541; Wed, 07 Aug 2019 00:45:57 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.56 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:56 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:20 -0700 Message-Id: <1565163924-18621-25-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 24/28] riscv: sifive_u: Support loading initramfs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The loading of initramfs is currently not supported on 'sifive_u'. Add the support to make '-initrd' command line parameter useful. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao --- Changes in v2: None hw/riscv/sifive_u.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ce6eba5..30e6c43 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -328,7 +328,18 @@ static void riscv_sifive_u_init(MachineState *machine) memmap[SIFIVE_U_DRAM].base); if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename); + uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); + + if (machine->initrd_filename) { + hwaddr start; + hwaddr end = riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + end); + } } /* reset vector */ From patchwork Wed Aug 7 07:45:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143361 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rxcMQeAt"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463P0G0mwtz9sNF for ; Wed, 7 Aug 2019 17:54:06 +1000 (AEST) Received: from localhost ([::1]:37882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGlo-0001Tk-6j for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:54:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36932) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGe0-0001P9-M4 for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:46:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGdz-0008GC-LM for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:46:00 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:40797) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGdz-0008Fe-Ef; Wed, 07 Aug 2019 03:45:59 -0400 Received: by mail-pl1-x643.google.com with SMTP id a93so39421854pla.7; Wed, 07 Aug 2019 00:45:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=5yv5CdOFuxZYetYZHajkKH0g9WGo0eAwO4vJ1GVM74E=; b=rxcMQeAtSU3j5P0tzdOIXFGgZXyA9ioDYNkKey3MM/7mGgost+HUPmgB4S84wncJUI +s4VcOnUTE0HVYVJXvglLdRkX84tlX+uPxW01DKon6D5iawwBDLX4gLHnVNdpJUIjh0z b9P1gGYa1pXYafGBUlksoU7odwG5ZylKyuyJC16fzXYTR4PwDnr/SlFKkq7w/QFgBPov LanzVmYzCjgQ7W26W4+UpZ/2pnHfvEAjVkLeI1dMDI4JN8YULrDHiGXfjlogaoTcsU8f LgypqYs3LadMQF2x+gPBTh9/uBV51ol3bMn2hUqIRUp2MmjAPlaR2zUihCmNindXZC5L WM5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=5yv5CdOFuxZYetYZHajkKH0g9WGo0eAwO4vJ1GVM74E=; b=fX0BkRFgkZnNxm5kFlrP6NNplgJF97KUBRnDbBpj5db/yXv+9Z1/0tBueSSGnGSuE8 VbsjCUgchmq9Q14nATWIoh6iSER3quwBJpXR05scGVooW6+wElJ5jlUKE6Vh3bsCnOcT CavH+UXCXY76ZntJINtIbntLK+Xpk3Bvu9eP1suc9rK0u9Q8LVl3Fb07csw9savKZTb4 YC7ZBIG16trIY2gca8Nfxmvu115XAf6Fy0yN2xj6pRo9gZ7PyoP+8xUFxf8pqXC/VJoy +56tS/K0YrWuWB/Zm39oWm5Tb0KJaF+MPZiSzGNCIppKjMKLkRxS17lQZrVjU+JQZGrJ +ykQ== X-Gm-Message-State: APjAAAWDV3Fe37NCu6y2T54zBEESx4WJzVszEqD8v9+h7d7A9UXrmOtI goruEtNzZEF8ITKdBRA1gsk= X-Google-Smtp-Source: APXvYqxIwP3lWtryoHmqTe/Yzx5gZAnOwRceOuyCA24MTBAyVmkAUAM4ujIAOQUCrj5VozOGIqksYQ== X-Received: by 2002:a17:902:f095:: with SMTP id go21mr7130477plb.58.1565163958734; Wed, 07 Aug 2019 00:45:58 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.57 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:45:58 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:21 -0700 Message-Id: <1565163924-18621-26-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 25/28] riscv: hw: Remove not needed PLIC properties in device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This removes "reg-names" and "riscv,max-priority" properties of the PLIC node from device tree. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens --- Changes in v2: - keep the PLIC compatible string unchanged as OpenSBI uses that for DT fix up hw/riscv/sifive_u.c | 2 -- hw/riscv/virt.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 30e6c43..d7a4aae 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -238,8 +238,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_PLIC].base, 0x0, memmap[SIFIVE_U_PLIC].size); - qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); - qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 127f005..2f75195 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -244,8 +244,6 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[VIRT_PLIC].base, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); - qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); From patchwork Wed Aug 7 07:45:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143367 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Q+e9lu/5"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463P3h72q7z9s7T for ; Wed, 7 Aug 2019 17:57:04 +1000 (AEST) Received: from localhost ([::1]:37966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGoh-0000QF-3b for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:57:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36985) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGe2-0001VN-Vx for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:46:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGe1-0008Hl-S7 for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:46:02 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:40798) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGe1-0008HD-M6; Wed, 07 Aug 2019 03:46:01 -0400 Received: by mail-pl1-x643.google.com with SMTP id a93so39422019pla.7; Wed, 07 Aug 2019 00:46:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=WcpG0CVXsq6+o6LWOrY8Ur4Wyj26nMAadnvMIS79BgA=; b=Q+e9lu/5J5vgBg8dxjAdOx/LMflBrPklOVEBB/Qcz6UdsK9WTcU1YEVhNRhxCjmH8O YGSKdu95nlMKLw3t5rI6J+WVHg2+OZsK3t0Ek3xjBl25IK3/9Sq5YIdhyvZjjq7wYrx7 O4EwZe0rU0Dyq7mGHlYyB9lykPc8e4noxBinijyJENoeCwTE7b0DaZgS6pO2vFYdseAU UqbPW7gwtywLXY0ikkrnEf1AXo8fMaWxVJtZZ416h+NoGZrtRYABHDvTyu6PIxR22jGo pp2xr0YM4ob7yTkTqOcsyhRazVIgD7th8DidTEz+HlT8MX58Adyey+UrzvZy4obV1hIY b2eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=WcpG0CVXsq6+o6LWOrY8Ur4Wyj26nMAadnvMIS79BgA=; b=acrzTSFLQ83ZiRzoIrO/j6Cy5yK6V/cijdkHEEiBfbQzGl1tDDBG0X8YzZ0Z0gztIX N0Q3E5L+lzKk+FsHh6i0QFLFah+QvSCPNUZ/Bhg2DiztMNKCzgJylESMsIxAfoP3w+PM 59dDOA2p9VQ5mu/s016U5YUly0w1qmDOflW6g+cvs0ChEMlrA7RepAzG1aLGTYkT0jms +qd1myOtXTvBC+ZlWyGLY9ST14qv9KEqhmqvzqf19yUUQJOGYihaqyxbd9T00cxSSvS9 lehIkHTqDa8GPo5gJDP8SNscK0CmQYXw+n06/7Uy9sT3oTbwUXh9mtX5H40cK3Et+a/L cCCw== X-Gm-Message-State: APjAAAW/RvT24hnQ0mTGM7JTO+mtCE8xY7I2GpavKsYbnQRhyySuvl85 EQPKfyBPItZJmPnbcKDUPcQ= X-Google-Smtp-Source: APXvYqwqd+fz30ASxK8yq6NZH1iewj2D4OTQ/b57MuWCXdXTkC006WwAPXE8ERDnz22sMqXCRQvNaA== X-Received: by 2002:aa7:9713:: with SMTP id a19mr8008957pfg.64.1565163960946; Wed, 07 Aug 2019 00:46:00 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.45.59 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:46:00 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:23 -0700 Message-Id: <1565163924-18621-28-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 27/28] riscv: virt: Change create_fdt() to return void X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" There is no need to return fdt at the end of create_fdt() because it's already saved in s->fdt. Other machines (sifive_u, spike) don't do it neither. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Philippe Mathieu-Daudé --- Changes in v2: None hw/riscv/virt.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2f75195..6bfa721 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -112,7 +112,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename, 0x1800, 0, 0, 0x7); } -static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, +static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { void *fdt; @@ -316,8 +316,6 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } g_free(nodename); - - return fdt; } @@ -373,7 +371,6 @@ static void riscv_virt_board_init(MachineState *machine) size_t plic_hart_config_len; int i; unsigned int smp_cpus = machine->smp.cpus; - void *fdt; /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), @@ -392,7 +389,7 @@ static void riscv_virt_board_init(MachineState *machine) main_mem); /* create device tree */ - fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", @@ -411,9 +408,9 @@ static void riscv_virt_board_init(MachineState *machine) hwaddr end = riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(fdt, "/chosen", + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } } From patchwork Wed Aug 7 07:45:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1143368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UAq/6xGL"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463P5L3KWvz9sNk for ; Wed, 7 Aug 2019 17:58:30 +1000 (AEST) Received: from localhost ([::1]:37998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGq3-00032o-Ii for incoming@patchwork.ozlabs.org; Wed, 07 Aug 2019 03:58:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37007) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvGe3-0001YJ-TX for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:46:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvGe2-0008IS-S9 for qemu-devel@nongnu.org; Wed, 07 Aug 2019 03:46:03 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:38297) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvGe2-0008I1-MO; Wed, 07 Aug 2019 03:46:02 -0400 Received: by mail-pl1-x644.google.com with SMTP id m12so874973plt.5; Wed, 07 Aug 2019 00:46:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=f6T919n+SeWrGFMjenG5tGNknymIFfYMfO7/05KZX6A=; b=UAq/6xGLb1pe/EONZxRdIMc2BsFb6/7fQI3Z2dWP70Rz3xz8DVr/NoMhKIE3zpSTZs 4NjWvhiDKJQBUBvIEcqCInySDTMUVKT2u3QvxzVlmnlc6ACMT1M+j6xJGJGx1KvPMXAD zEHRsxryO5jBlk1bhjKeb1QFJLI7qfJ/bJSonOk01yz6nXarI95Pdn7qGsG39xx87C3B x+cL7Daq+6DhQlPuVSm1eV0JL9dQgOJvQwjYpmXYjGjErlqwz9r2X9XnUgOBiny6amwP 889iyxg3OMvvKQahWfo84z1I1QLSgq3YRmGuVabD44Prq6BzR/Ca7KzLX/Lrd2apfsaP AJWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=f6T919n+SeWrGFMjenG5tGNknymIFfYMfO7/05KZX6A=; b=A2OIsLgVIMty6ld59tdxYQE/Tf9Pp1fI+nHzLztCBLC2YG0spLuuT/Elqxvwuou4Bf KlF1dFdcZaZwnKlIYrR9U7spQHYCBU7JrtO5PmRgFnweCW3Ex+JzINyTJGMjL4EsYOXW lXtYYx0l7KDNqrj7fMUBrLGliEwO4Zt+Ry/4Kuhm/3itF6IbXZowy+1bIos5vPCkDDTM jo3Btp3+A7XRaILV6zeZROKKYFML/BXMngMPdgQcD/qe1jtYdwtD5fSCSv+zRehsY4dr RMHrIHSdgFpOhcoZoPZgJCf4slX4/qYv/oo+hzVAb1TxK8JWupdYu+EBWFbaHA/j0p3g Lb2w== X-Gm-Message-State: APjAAAX0O1U+TDi73tJh6BqQ2xL1Lm8VjT9BSbfJnOz/KgVsfSlPTc+I n+pIO0MHjnhI8lqmUChlgvE= X-Google-Smtp-Source: APXvYqxoYPSkhJlaWtwrpB+Nrkk8A9r+dw1ES/xRZtuV3URaucewfYmQnINIh84Y36qYSws68Na6Ig== X-Received: by 2002:a17:902:2ec5:: with SMTP id r63mr6912961plb.21.1565163961973; Wed, 07 Aug 2019 00:46:01 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id l44sm20154449pje.29.2019.08.07.00.46.00 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Aug 2019 00:46:01 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Wed, 7 Aug 2019 00:45:24 -0700 Message-Id: <1565163924-18621-29-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 28/28] riscv: sifive_u: Update model and compatible strings in device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This updates model and compatible strings to use the same strings as used in the Linux kernel device tree (hifive-unleashed-a00.dts). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v2: None hw/riscv/sifive_u.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d7a4aae..48078f1 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -96,8 +96,9 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, exit(1); } - qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); - qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); + qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); + qemu_fdt_setprop_string(fdt, "/", "compatible", + "sifive,hifive-unleashed-a00"); qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);