From patchwork Mon Aug 5 20:33:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 1142457 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 462Ty01VJ5z9s3Z for ; Tue, 6 Aug 2019 06:34:00 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 462Txz4RDjzDqXm for ; Tue, 6 Aug 2019 06:33:59 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 462TxW4FmBzDqWL for ; Tue, 6 Aug 2019 06:33:34 +1000 (AEST) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x75KWCYA133382 for ; Mon, 5 Aug 2019 16:33:30 -0400 Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0a-001b2d01.pphosted.com with ESMTP id 2u6rkf74s3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 05 Aug 2019 16:33:30 -0400 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id x75KUNF3019939 for ; Mon, 5 Aug 2019 20:33:29 GMT Received: from b01cxnp22033.gho.pok.ibm.com (b01cxnp22033.gho.pok.ibm.com [9.57.198.23]) by ppma05wdc.us.ibm.com with ESMTP id 2u51w69wwc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 05 Aug 2019 20:33:29 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x75KXSPb47448420 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 5 Aug 2019 20:33:28 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C6907124058 for ; Mon, 5 Aug 2019 20:33:28 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AB5E7124055 for ; Mon, 5 Aug 2019 20:33:28 +0000 (GMT) Received: from arbab-laptop.localdomain (unknown [9.53.179.210]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP for ; Mon, 5 Aug 2019 20:33:28 +0000 (GMT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id 5A57246219A; Mon, 5 Aug 2019 15:33:27 -0500 (CDT) From: Reza Arbab To: skiboot@lists.ozlabs.org Date: Mon, 5 Aug 2019 15:33:26 -0500 Message-Id: <1565037207-30968-1-git-send-email-arbab@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-05_11:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=959 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908050206 Subject: [Skiboot] [PATCH 1/2] npu3: Rename NPU3_SM_MISC_CFGn register macros X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Grimm MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The SM blocks have multiple MISC_CFG registers. For example, there are both CS.SM0.MCP.MISC.CONFIG0 and CS.SM0.SNP.MISC.CONFIG0. Rename our macro for the former to more clearly reflect this and avoid a clash when the latter is added. Signed-off-by: Reza Arbab Reviewed-by: Christophe Lombard --- hw/npu3.c | 10 +++++----- include/npu3-regs.h | 14 +++++++------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/npu3.c b/hw/npu3.c index e49e9bef2a96..ea687f43c5e7 100644 --- a/hw/npu3.c +++ b/hw/npu3.c @@ -301,12 +301,12 @@ static void npu3_misc_config(struct npu3 *npu) npu3_for_each_nvlink_dev(dev, npu) typemap |= 0x10 >> dev->index; - reg = NPU3_SM_MISC_CFG0; + reg = NPU3_MCP_MISC_CFG0; val = npu3_read(npu, reg); - val |= NPU3_SM_MISC_CFG0_ENABLE_PBUS; - val &= ~NPU3_SM_MISC_CFG0_ENABLE_SNARF_CPM; - val = SETFIELD(NPU3_SM_MISC_CFG0_NVLINK_MODE, val, typemap); - val = SETFIELD(NPU3_SM_MISC_CFG0_OCAPI_MODE, val, ~typemap); + val |= NPU3_MCP_MISC_CFG0_ENABLE_PBUS; + val &= ~NPU3_MCP_MISC_CFG0_ENABLE_SNARF_CPM; + val = SETFIELD(NPU3_MCP_MISC_CFG0_NVLINK_MODE, val, typemap); + val = SETFIELD(NPU3_MCP_MISC_CFG0_OCAPI_MODE, val, ~typemap); npu3_write(npu, reg, val); reg = NPU3_CTL_MISC_CFG2; diff --git a/include/npu3-regs.h b/include/npu3-regs.h index 2e1dc3930574..c0c7eab0396d 100644 --- a/include/npu3-regs.h +++ b/include/npu3-regs.h @@ -86,13 +86,13 @@ * Definitions here use NPU3_BLOCK_CQ_SM(0), but when npu3_write() is given * one of these, it will do corresponding writes to every CQ_SM block. */ -#define NPU3_SM_MISC_CFG0 (NPU3_BLOCK_CQ_SM(0) + 0x000) -#define NPU3_SM_MISC_CFG0_ENABLE_PBUS PPC_BIT(26) -#define NPU3_SM_MISC_CFG0_ENABLE_SNARF_CPM PPC_BIT(27) -#define NPU3_SM_MISC_CFG0_OCAPI_MODE PPC_BITMASK(44, 48) -#define NPU3_SM_MISC_CFG0_NVLINK_MODE PPC_BITMASK(49, 53) -#define NPU3_SM_MISC_CFG1 (NPU3_BLOCK_CQ_SM(0) + 0x008) -#define NPU3_SM_MISC_CFG2 (NPU3_BLOCK_CQ_SM(0) + 0x0f0) +#define NPU3_MCP_MISC_CFG0 (NPU3_BLOCK_CQ_SM(0) + 0x000) +#define NPU3_MCP_MISC_CFG0_ENABLE_PBUS PPC_BIT(26) +#define NPU3_MCP_MISC_CFG0_ENABLE_SNARF_CPM PPC_BIT(27) +#define NPU3_MCP_MISC_CFG0_OCAPI_MODE PPC_BITMASK(44, 48) +#define NPU3_MCP_MISC_CFG0_NVLINK_MODE PPC_BITMASK(49, 53) +#define NPU3_MCP_MISC_CFG1 (NPU3_BLOCK_CQ_SM(0) + 0x008) +#define NPU3_MCP_MISC_CFG2 (NPU3_BLOCK_CQ_SM(0) + 0x0f0) #define NPU3_GPU_MEM_BAR(brk) (NPU3_BLOCK_CQ_SM(0) + 0x190 + (brk) * 8) #define NPU3_GPU_MEM_BAR_ENABLE PPC_BIT(0) #define NPU3_GPU_MEM_BAR_ADDR_MASK PPC_BITMASK(1, 35) From patchwork Mon Aug 5 20:33:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 1142456 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 462Txd4C7Zz9s3Z for ; Tue, 6 Aug 2019 06:33:41 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 462Txd2T0czDqWg for ; Tue, 6 Aug 2019 06:33:41 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 462TxW4L4pzDqWM for ; Tue, 6 Aug 2019 06:33:34 +1000 (AEST) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x75KWBC8133248 for ; Mon, 5 Aug 2019 16:33:32 -0400 Received: from e12.ny.us.ibm.com (e12.ny.us.ibm.com [129.33.205.202]) by mx0a-001b2d01.pphosted.com with ESMTP id 2u6rkf74sx-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 05 Aug 2019 16:33:31 -0400 Received: from localhost by e12.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 5 Aug 2019 21:33:29 +0100 Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x75KXSan8127026 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 5 Aug 2019 20:33:28 GMT Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BBAAF112062 for ; Mon, 5 Aug 2019 20:33:28 +0000 (GMT) Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AB588112061 for ; Mon, 5 Aug 2019 20:33:28 +0000 (GMT) Received: from arbab-laptop.localdomain (unknown [9.53.179.210]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP for ; Mon, 5 Aug 2019 20:33:28 +0000 (GMT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id 62563460727; Mon, 5 Aug 2019 15:33:27 -0500 (CDT) From: Reza Arbab To: skiboot@lists.ozlabs.org Date: Mon, 5 Aug 2019 15:33:27 -0500 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1565037207-30968-1-git-send-email-arbab@linux.ibm.com> References: <1565037207-30968-1-git-send-email-arbab@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19080520-0060-0000-0000-0000036962AD X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011556; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000287; SDB=6.01242579; UDB=6.00655422; IPR=6.01024036; MB=3.00028055; MTD=3.00000008; XFM=3.00000015; UTC=2019-08-05 20:33:30 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19080520-0061-0000-0000-00004A709634 Message-Id: <1565037207-30968-2-git-send-email-arbab@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-05_11:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=807 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908050206 Subject: [Skiboot] [PATCH 2/2] npu3: Initialize NPU3_SNP_MISC_CFG0 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Grimm MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Enable powerbus snooping here, or else MMIO to any NTL/NDL registers will cause a checkstop. This was not an issue in Simics simulation, but discovered rather quickly during bringup on a real Axone chip. Signed-off-by: Reza Arbab Reviewed-by: Christophe Lombard --- hw/npu3.c | 7 +++++++ include/npu3-regs.h | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/hw/npu3.c b/hw/npu3.c index ea687f43c5e7..4d396b09b806 100644 --- a/hw/npu3.c +++ b/hw/npu3.c @@ -309,6 +309,13 @@ static void npu3_misc_config(struct npu3 *npu) val = SETFIELD(NPU3_MCP_MISC_CFG0_OCAPI_MODE, val, ~typemap); npu3_write(npu, reg, val); + reg = NPU3_SNP_MISC_CFG0; + val = npu3_read(npu, reg); + val |= NPU3_SNP_MISC_CFG0_ENABLE_PBUS; + val = SETFIELD(NPU3_SNP_MISC_CFG0_NVLINK_MODE, val, typemap); + val = SETFIELD(NPU3_SNP_MISC_CFG0_OCAPI_MODE, val, ~typemap); + npu3_write(npu, reg, val); + reg = NPU3_CTL_MISC_CFG2; val = npu3_read(npu, reg); val = SETFIELD(NPU3_CTL_MISC_CFG2_NVLINK_MODE, val, typemap); diff --git a/include/npu3-regs.h b/include/npu3-regs.h index c0c7eab0396d..341d652899c3 100644 --- a/include/npu3-regs.h +++ b/include/npu3-regs.h @@ -93,6 +93,10 @@ #define NPU3_MCP_MISC_CFG0_NVLINK_MODE PPC_BITMASK(49, 53) #define NPU3_MCP_MISC_CFG1 (NPU3_BLOCK_CQ_SM(0) + 0x008) #define NPU3_MCP_MISC_CFG2 (NPU3_BLOCK_CQ_SM(0) + 0x0f0) +#define NPU3_SNP_MISC_CFG0 (NPU3_BLOCK_CQ_SM(0) + 0x180) +#define NPU3_SNP_MISC_CFG0_ENABLE_PBUS PPC_BIT(2) +#define NPU3_SNP_MISC_CFG0_OCAPI_MODE PPC_BITMASK(32, 36) +#define NPU3_SNP_MISC_CFG0_NVLINK_MODE PPC_BITMASK(37, 41) #define NPU3_GPU_MEM_BAR(brk) (NPU3_BLOCK_CQ_SM(0) + 0x190 + (brk) * 8) #define NPU3_GPU_MEM_BAR_ENABLE PPC_BIT(0) #define NPU3_GPU_MEM_BAR_ADDR_MASK PPC_BITMASK(1, 35)