From patchwork Mon Nov 6 18:03:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 834864 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yW0m46zrnz9sBZ for ; Tue, 7 Nov 2017 05:03:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754227AbdKFSDP (ORCPT ); Mon, 6 Nov 2017 13:03:15 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:9097 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754158AbdKFSDO (ORCPT ); Mon, 6 Nov 2017 13:03:14 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 06 Nov 2017 10:03:11 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 06 Nov 2017 10:03:26 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 06 Nov 2017 10:03:26 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 6 Nov 2017 18:03:13 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 6 Nov 2017 18:03:13 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 6 Nov 2017 18:03:13 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.36.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 06 Nov 2017 10:03:13 -0800 From: Vidya Sagar To: , CC: , , , , , Subject: [PATCH] PCI: tegra: limit MSI target address to 32-bit Date: Mon, 6 Nov 2017 23:33:07 +0530 Message-ID: <1509991387-15951-1-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org limits MSI target address to only 32-bit region to enable some of the PCIe end points where only 32-bit MSIs are supported work properly. One example being Marvel SATA controller Signed-off-by: Vidya Sagar --- drivers/pci/host/pci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 1987fec1f126..03d3dcdd06c2 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -1531,7 +1531,7 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie) } /* setup AFI/FPCI range */ - msi->pages = __get_free_pages(GFP_KERNEL, 0); + msi->pages = __get_free_pages(GFP_DMA, 0); msi->phys = virt_to_phys((void *)msi->pages); afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);