From patchwork Sun Jul 21 19:40:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134609 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="mdxvnyLh"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFWj0VQpz9s3l for ; Mon, 22 Jul 2019 05:42:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726457AbfGUTkz (ORCPT ); Sun, 21 Jul 2019 15:40:55 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8980 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726323AbfGUTky (ORCPT ); Sun, 21 Jul 2019 15:40:54 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:40:50 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:40:52 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:40:52 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:40:52 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:40:51 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:40:51 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:40:51 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 01/21] irqchip: tegra: Do not disable COP IRQ during suspend Date: Sun, 21 Jul 2019 12:40:40 -0700 Message-ID: <1563738060-30213-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738050; bh=s1XnuLcDk97/CuRHD9/IW+GAX3pxhADV42EQBIG7j4Y=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=mdxvnyLhSwkqXvEeRBRJCBab2gnmFHKfiZBKqodjHscL+sMBNf3UQgJbVdvV3j4y9 T0Zjz6UVUXEsnTRG7I0u+wI0hCcyiU+sYN9URPzsnvxDsVaU1COed2h+zpBQvfY6eV emvwCRm8TkLR3xMZYzlnyUY108P/VhQB6KPS01QLUjX3+SC6aHBLM/S6lvz98j5Jcr 2iXsmyo+cv983GD5j1VJIiMXOjIdLT49xG6Hvq2aF1knKsRSd+zi9k9p85Lv6sLW58 eqyh7i38poPXl51BJlNaC1d7hzr37JKqsRSd7n8oaVI0ZxNwKYaWEwSkRFRU00WVvE sZFGwUXCNIc8A== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry sequence and sc7 entry firmware is run from COP/BPMP-Lite. So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence for Tegra210. This patch has fix for leaving the COP IRQ enabled for Tegra210 during interrupt controller suspend operation. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni Acked-by: Marc Zyngier --- drivers/irqchip/irq-tegra.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c index e1f771c72fc4..851f88cef508 100644 --- a/drivers/irqchip/irq-tegra.c +++ b/drivers/irqchip/irq-tegra.c @@ -44,6 +44,7 @@ static unsigned int num_ictlrs; struct tegra_ictlr_soc { unsigned int num_ictlrs; + bool supports_sc7; }; static const struct tegra_ictlr_soc tegra20_ictlr_soc = { @@ -56,6 +57,7 @@ static const struct tegra_ictlr_soc tegra30_ictlr_soc = { static const struct tegra_ictlr_soc tegra210_ictlr_soc = { .num_ictlrs = 6, + .supports_sc7 = true, }; static const struct of_device_id ictlr_matches[] = { @@ -67,6 +69,7 @@ static const struct of_device_id ictlr_matches[] = { struct tegra_ictlr_info { void __iomem *base[TEGRA_MAX_NUM_ICTLRS]; + const struct tegra_ictlr_soc *soc; #ifdef CONFIG_PM_SLEEP u32 cop_ier[TEGRA_MAX_NUM_ICTLRS]; u32 cop_iep[TEGRA_MAX_NUM_ICTLRS]; @@ -147,8 +150,20 @@ static int tegra_ictlr_suspend(void) lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER); lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS); - /* Disable COP interrupts */ - writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); + /* + * AVP/COP/BPMP-Lite is the Tegra boot processor. + * + * Tegra210 system suspend flow uses sc7entry firmware which + * is executed by COP/BPMP and it includes disabling COP IRQ, + * clamping CPU rail, turning off VDD_CPU, and preparing the + * system to go to SC7/LP0. + * + * COP/BPMP wakes up when COP IRQ is triggered and runs + * sc7entry-firmware. So need to keep COP interrupt enabled. + */ + if (!lic->soc->supports_sc7) + /* Disable COP interrupts if SC7 is not supported */ + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); /* Disable CPU interrupts */ writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); @@ -339,6 +354,7 @@ static int __init tegra_ictlr_init(struct device_node *node, goto out_unmap; } + lic->soc = soc; tegra_ictlr_syscore_init(); pr_info("%pOF: %d interrupts forwarded to %pOF\n", From patchwork Sun Jul 21 19:40:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134567 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="HzcncTV9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFTp3VJZz9s3l for ; Mon, 22 Jul 2019 05:41:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727559AbfGUTlB (ORCPT ); Sun, 21 Jul 2019 15:41:01 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15816 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727437AbfGUTlA (ORCPT ); Sun, 21 Jul 2019 15:41:00 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:01 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:40:53 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 21 Jul 2019 12:40:53 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:40:53 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:40:53 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:40:53 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 02/21] pinctrl: tegra: Add suspend and resume support Date: Sun, 21 Jul 2019 12:40:41 -0700 Message-ID: <1563738060-30213-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738061; bh=0TWDtDoYIVMoTSFpzR7yFBbnojgeD2sdZQyue/UYp68=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=HzcncTV99aOe/XLBEzcraeO7a2FwpLsthslZBvwetK46VKaP6m2J0XJwP1bKYtQYm r7B5KBImoWaOnU94tMFyJDFMieG864vnfUF2fPEzI0BVUQ+hgVaPl0DOv7DEm3IiYp nOWoxsATYpdWBbq/sj2rBtgj2KNDMUKOJVH3UMc1tpm9+uNmJ/vShhP/GuNqOMyyUv dECpqy6Ajzwi3joD8enbcmCc0jsi+DbOIueCy0fm8dKVouNnXTcMpdX9b57JFSD4pV W5mYb0MHUNnAJM650OiK306sCsYK2wq1Gxgq8DWxgWYPWeoFp/ssb9w3s63tFzZeKa baTNVebOqopHg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch adds support for Tegra pinctrl driver suspend and resume. During suspend, context of all pinctrl registers are stored and on resume they are all restored to have all the pinmux and pad configuration for normal operation. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni Reviewed-by: Dmitry Osipenko --- drivers/pinctrl/tegra/pinctrl-tegra.c | 59 +++++++++++++++++++++++++++++++++++ drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++ 2 files changed, 62 insertions(+) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 186ef98e7b2b..e3a237534281 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -631,6 +631,58 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) } } +static size_t tegra_pinctrl_get_bank_size(struct device *dev, + unsigned int bank_id) +{ + struct platform_device *pdev = to_platform_device(dev); + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); + + return resource_size(res) / 4; +} + +static int tegra_pinctrl_suspend(struct device *dev) +{ + struct tegra_pmx *pmx = dev_get_drvdata(dev); + u32 *backup_regs = pmx->backup_regs; + u32 *regs; + size_t bank_size; + unsigned int i, k; + + for (i = 0; i < pmx->nbanks; i++) { + bank_size = tegra_pinctrl_get_bank_size(dev, i); + regs = pmx->regs[i]; + for (k = 0; k < bank_size; k++) + *backup_regs++ = readl_relaxed(regs++); + } + + return pinctrl_force_sleep(pmx->pctl); +} + +static int tegra_pinctrl_resume(struct device *dev) +{ + struct tegra_pmx *pmx = dev_get_drvdata(dev); + u32 *backup_regs = pmx->backup_regs; + u32 *regs; + size_t bank_size; + unsigned int i, k; + + for (i = 0; i < pmx->nbanks; i++) { + bank_size = tegra_pinctrl_get_bank_size(dev, i); + regs = pmx->regs[i]; + for (k = 0; k < bank_size; k++) + writel_relaxed(*backup_regs++, regs++); + } + + return 0; +} + +const struct dev_pm_ops tegra_pinctrl_pm = { + .suspend = &tegra_pinctrl_suspend, + .resume = &tegra_pinctrl_resume +}; + static bool gpio_node_has_range(const char *compatible) { struct device_node *np; @@ -655,6 +707,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, int i; const char **group_pins; int fn, gn, gfn; + unsigned long backup_regs_size = 0; pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); if (!pmx) @@ -707,6 +760,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, res = platform_get_resource(pdev, IORESOURCE_MEM, i); if (!res) break; + backup_regs_size += resource_size(res); } pmx->nbanks = i; @@ -715,6 +769,11 @@ int tegra_pinctrl_probe(struct platform_device *pdev, if (!pmx->regs) return -ENOMEM; + pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, + GFP_KERNEL); + if (!pmx->backup_regs) + return -ENOMEM; + for (i = 0; i < pmx->nbanks; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 105309774079..0fc82eea9cf1 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -17,6 +17,7 @@ struct tegra_pmx { int nbanks; void __iomem **regs; + u32 *backup_regs; }; enum tegra_pinconf_param { @@ -193,6 +194,8 @@ struct tegra_pinctrl_soc_data { bool drvtype_in_mux; }; +extern const struct dev_pm_ops tegra_pinctrl_pm; + int tegra_pinctrl_probe(struct platform_device *pdev, const struct tegra_pinctrl_soc_data *soc_data); #endif From patchwork Sun Jul 21 19:40:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134608 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Yov7EyoS"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFWg5ClDz9s8m for ; Mon, 22 Jul 2019 05:42:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727116AbfGUTk5 (ORCPT ); Sun, 21 Jul 2019 15:40:57 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12449 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727005AbfGUTk4 (ORCPT ); Sun, 21 Jul 2019 15:40:56 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:40:56 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:40:55 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:40:55 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:40:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:40:55 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:40:55 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 03/21] pinctrl: tegra210: Add Tegra210 pinctrl pm ops Date: Sun, 21 Jul 2019 12:40:42 -0700 Message-ID: <1563738060-30213-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738056; bh=Zm1gtaqy4b8W/mJsa6WY/rY4ZSHBss5j7JPBEnDqUv4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Yov7EyoSlKhZwur9Ak2Z4mnldWpAp7IVmLUAlX5s0nprQMM/TgJjZLppmCSYyQ5Bt p9Ddvlc6ghD9a4YgJkkfYlQ2Mvg+TqCU+SCemk8TnCPQQVgRfkhmJq2ogKVEeeUuKk 6XnYicWvvzXkczDgkevf3VJDSQy+Aa5DdSbCbuIrQvWF9+G0fgKSvU9enb3PjPK4Hz 17gsPfYzRGy0RNvaASWskxhHP80sxoImtdxBjcfvqw7f5sFwDt7XSvhgZL0n91KxW8 prHvIhVv8iwvGlgm7unBlfaEOakcIb6HMFmO53rCoLIoPuK8i1i/OVRr/gUJVKdMl7 9lMFW1rcM0NDA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch adds suspend and resume functionality to Tegra210 pinctrl. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c index 39ab6480a941..fc072a36deb3 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c @@ -1571,6 +1571,7 @@ static struct platform_driver tegra210_pinctrl_driver = { .driver = { .name = "tegra210-pinctrl", .of_match_table = tegra210_pinctrl_of_match, + .pm = &tegra_pinctrl_pm, }, .probe = tegra210_pinctrl_probe, }; From patchwork Sun Jul 21 19:40:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134605 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="sT6G6U4q"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFWc1vgtz9sBF for ; Mon, 22 Jul 2019 05:42:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727345AbfGUTk6 (ORCPT ); Sun, 21 Jul 2019 15:40:58 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12466 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727278AbfGUTk6 (ORCPT ); Sun, 21 Jul 2019 15:40:58 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:40:57 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:40:57 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:40:57 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:40:56 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:40:56 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:40:56 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 04/21] clk: tegra: Save and restore divider rate Date: Sun, 21 Jul 2019 12:40:43 -0700 Message-ID: <1563738060-30213-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738057; bh=Nd1v90bh7Ho/ojHQIob7we6JLN3yOOpS5vD9L3b3q98=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=sT6G6U4quiCzDr/cNiyqeiylZFrOn1UvABjs7Yd4r7s7qEStzy97Bn2NC9WAqGcBf O5lrsuV5rI/F63BJmvIqezbpIgk6F7jo9McNp2yS/jePFMOJJohqZ+M3ijSdAMtxH5 OMXQRoOZ5SRxYNduehdJLmo9nYs2im5SO3FS/GmnnPZmVy0jbnkg3mhhrgp9iTjNGf xt/r/IY2qWeppBsywwBzs0sKSJ5kmHktReacw+L6T3gkXBxQJiGUf2eMsT8ubtXjht rTNkzh0G8q63dipefnAmcftWrF+WxOuzhUj9qlB27PyBi1mZ6sLNUbKnPNJKQkIK8g vj2q7DfWiVL+w== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements context save and restore for clock divider. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry the context of clock divider is saved and on resume context is restored back for normal operation. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-divider.c | 23 +++++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index e76731fb7d69..ecb7ff9ce97e 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -109,10 +109,33 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int clk_divider_save_context(struct clk_hw *hw) +{ + struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + divider->rate = clk_frac_div_recalc_rate(hw, parent_rate); + + return 0; +} + +static void clk_divider_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + if (clk_frac_div_set_rate(hw, divider->rate, parent_rate) < 0) + WARN_ON(1); +} + const struct clk_ops tegra_clk_frac_div_ops = { .recalc_rate = clk_frac_div_recalc_rate, .set_rate = clk_frac_div_set_rate, .round_rate = clk_frac_div_round_rate, + .save_context = clk_divider_save_context, + .restore_context = clk_divider_restore_context, }; struct clk *tegra_clk_register_divider(const char *name, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 905bf1096558..83623f5f55f3 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -42,6 +42,7 @@ struct clk *tegra_clk_register_sync_source(const char *name, * @width: width of the divider bit field * @frac_width: width of the fractional bit field * @lock: register lock + * @rate: rate during suspend and resume * * Flags: * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. @@ -62,6 +63,7 @@ struct tegra_clk_frac_div { u8 width; u8 frac_width; spinlock_t *lock; + unsigned long rate; }; #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) From patchwork Sun Jul 21 19:40:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134598 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="lyYpN8ED"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFWN3CSXz9s7T for ; Mon, 22 Jul 2019 05:42:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727569AbfGUTlC (ORCPT ); Sun, 21 Jul 2019 15:41:02 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8992 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727460AbfGUTlB (ORCPT ); Sun, 21 Jul 2019 15:41:01 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:40:56 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:40:58 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:40:58 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:40:58 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:40:58 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:40:58 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:40:58 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 05/21] clk: tegra: pllout: Save and restore pllout context Date: Sun, 21 Jul 2019 12:40:44 -0700 Message-ID: <1563738060-30213-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738056; bh=XCkccFmr6HwkH8cbMy/GTsrauvkmh1OiKCcR5AhT1B8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=lyYpN8EDe4/kVt4VWFEtRSbE/aCW8pDkVx8gKNricSLqOmSRYg4izJdQp/PlKUwVp yGhFhA+1vrwnpLhth2tnZ5cF0kBEn5o7IhKPszyKifRUyZixTCB5Gfcf3peO1hVWlc 1c5Y4S+UuUYlnO55M6s0swQCQm9RFjlZZW2cHPv9bUO/pX4MwJFQL8rlV7PHy2AkQs cSjDT3JRAXpuBPFao9jt0K9ViDWqJR3s9HaCL6gn/i6BkchyXo7obQjB97N/ynrBvb 5hQsoM/AdKsiQD521hke3mMvtWeVhGKUmV582gmdmNoj7hLvnpauPdGFOjFJ+1zc5G H7Apn7+Q0aLCA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements save and restore of pllout context. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry the state of pllout is saved and on resume it is restored back to have pllout in same state as before suspend. pllout rate is saved and restore in clock divider so it will be at same rate as before suspend when pllout state is restored. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-pll-out.c | 28 ++++++++++++++++++++++++++++ drivers/clk/tegra/clk-tegra210.c | 3 ++- drivers/clk/tegra/clk.h | 9 +++++++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c index 35f2bf00e1e6..8f26a7e3e579 100644 --- a/drivers/clk/tegra/clk-pll-out.c +++ b/drivers/clk/tegra/clk-pll-out.c @@ -69,10 +69,38 @@ static void clk_pll_out_disable(struct clk_hw *hw) spin_unlock_irqrestore(pll_out->lock, flags); } +static int tegra_clk_pll_out_save_context(struct clk_hw *hw) +{ + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); + + if (pll_out->flags & TEGRA_PLLRE_OUT) + pll_out->pllout_ctx = readl_relaxed(pll_out->reg); + else + pll_out->pllout_ctx = clk_hw_get_rate(hw); + + return 0; +} + +static void tegra_clk_pll_out_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); + + if (pll_out->flags & TEGRA_PLLRE_OUT) { + writel_relaxed(pll_out->pllout_ctx, pll_out->reg); + } else { + if (!__clk_get_enable_count(hw->clk)) + clk_pll_out_disable(hw); + else + clk_pll_out_enable(hw); + } +} + const struct clk_ops tegra_clk_pll_out_ops = { .is_enabled = clk_pll_out_is_enabled, .enable = clk_pll_out_enable, .disable = clk_pll_out_disable, + .save_context = tegra_clk_pll_out_save_context, + .restore_context = tegra_clk_pll_out_restore_context, }; struct clk *tegra_clk_register_pll_out(const char *name, diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index df172d5772d7..4721ee030d1c 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3200,7 +3200,8 @@ static void __init tegra210_pll_init(void __iomem *clk_base, 8, 8, 1, NULL); clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div", clk_base + PLLRE_OUT1, 1, 0, - CLK_SET_RATE_PARENT, 0, NULL); + CLK_SET_RATE_PARENT, TEGRA_PLLRE_OUT, + NULL); clks[TEGRA210_CLK_PLL_RE_OUT1] = clk; /* PLLE */ diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 83623f5f55f3..fb29a8c27873 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -439,6 +439,12 @@ struct clk *tegra_clk_register_pllu_tegra210(const char *name, * @rst_bit_idx: bit to reset PLL divider * @lock: register lock * @flags: hardware-specific flags + * @pllout_ctx: pllout context to save and restore during suspend + * and resume + * + * Flags: + * TEGRA_PLLRE_OUT - This flag indicates that it is PLLRE_OUT and is used to + * identify PLLRE_OUT during clk_pll_out save and restore. */ struct tegra_clk_pll_out { struct clk_hw hw; @@ -447,8 +453,11 @@ struct tegra_clk_pll_out { u8 rst_bit_idx; spinlock_t *lock; u8 flags; + unsigned int pllout_ctx; }; +#define TEGRA_PLLRE_OUT BIT(0) + #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) extern const struct clk_ops tegra_clk_pll_out_ops; From patchwork Sun Jul 21 19:40:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134601 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="GcES4xjr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFWR41GLz9sBF for ; Mon, 22 Jul 2019 05:42:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728006AbfGUTmX (ORCPT ); Sun, 21 Jul 2019 15:42:23 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12478 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727552AbfGUTlC (ORCPT ); Sun, 21 Jul 2019 15:41:02 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:01 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:00 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 21 Jul 2019 12:41:00 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:00 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:40:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:40:59 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:00 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 06/21] clk: tegra: pll: Save and restore pll context Date: Sun, 21 Jul 2019 12:40:45 -0700 Message-ID: <1563738060-30213-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738061; bh=aHWJSVx13LuzUutUKwAZaVtBY+ayrcR85Vq9Znm7wZ8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=GcES4xjrPQcsRDHO2yAPAy97aWt9M27BBGBO3a0ZABOED56SNrV1EAeoRRnw6sW+O 1bNSQ1Nc2206e7neLaxJKKGjPHI/di+IygQJEsJd6/WwVDnebZbrwju+vmpdNr6z+6 fkC5phKuMxcTF5rIozQL5ZdaAw1NxlG0whxjh/Kf1Bd58lE8frIaAzVedtHzCnaJVa 8kMdZeiTTSL/ua1g+vrlJFavdMvKIBnIqcOUkUqFp7EJrk89UL4OxLdvCbJdESD/0m vMD5PVnC5wkNo66R7rlUoj0vHOSpsrsP+0qXcVWl9xwd2Ad1/qbbJfJYIAZ+KXMpzm uc89zmrdNym3A== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements save and restore of PLL context. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry pll rate is stored and on resume it is restored back along with its state. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-pll.c | 121 ++++++++++++++++++++++++++++----------- drivers/clk/tegra/clk-tegra210.c | 2 +- drivers/clk/tegra/clk.h | 10 +++- 3 files changed, 99 insertions(+), 34 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 1583f5fc992f..f136964e6c44 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1008,6 +1008,59 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, return rate; } +void tegra_clk_sync_state_pll(struct clk_hw *hw) +{ + if (!__clk_get_enable_count(hw->clk)) + clk_pll_disable(hw); + else + clk_pll_enable(hw); +} + +static int tegra_clk_pll_save_context(struct clk_hw *hw) +{ + struct tegra_clk_pll *pll = to_clk_pll(hw); + u32 val = 0; + + pll->rate = clk_hw_get_rate(hw); + + if (pll->params->flags & TEGRA_PLLMB) + val = pll_readl_base(pll); + else if (pll->params->flags & TEGRA_PLLRE) + val = pll_readl_base(pll) & divp_mask_shifted(pll); + + pll->pllbase_ctx = val; + + return 0; +} + +static void tegra_clk_pll_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_pll *pll = to_clk_pll(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + u32 val; + + if (clk_pll_is_enabled(hw)) + return; + + if (pll->params->flags & TEGRA_PLLMB) { + pll_writel_base(pll->pllbase_ctx, pll); + } else if (pll->params->flags & TEGRA_PLLRE) { + val = pll_readl_base(pll); + val &= ~(divp_mask_shifted(pll)); + pll_writel_base(pll->pllbase_ctx | val, pll); + } + + if (pll->params->set_defaults) + pll->params->set_defaults(pll); + + clk_pll_set_rate(hw, pll->rate, parent_rate); + + /* do not sync pllx state here. pllx is sync'd after dfll resume */ + if (!(pll->params->flags & TEGRA_PLLX)) + tegra_clk_sync_state_pll(hw); +} + const struct clk_ops tegra_clk_pll_ops = { .is_enabled = clk_pll_is_enabled, .enable = clk_pll_enable, @@ -1015,6 +1068,8 @@ const struct clk_ops tegra_clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_round_rate, .set_rate = clk_pll_set_rate, + .save_context = tegra_clk_pll_save_context, + .restore_context = tegra_clk_pll_restore_context, }; const struct clk_ops tegra_clk_plle_ops = { @@ -1802,6 +1857,27 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw) return ret; } + +static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll) +{ + u32 val, val_aux; + + /* ensure parent is set to pll_ref */ + val = pll_readl_base(pll); + val_aux = pll_readl(pll->params->aux_reg, pll); + + if (val & PLL_BASE_ENABLE) { + if ((val_aux & PLLE_AUX_PLLRE_SEL) || + (val_aux & PLLE_AUX_PLLP_SEL)) + WARN(1, "pll_e enabled with unsupported parent %s\n", + (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : + "pll_re_vco"); + } else { + val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); + pll_writel(val_aux, pll->params->aux_reg, pll); + fence_udelay(1, pll->clk_base); + } +} #endif static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, @@ -2214,27 +2290,12 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name, { struct tegra_clk_pll *pll; struct clk *clk; - u32 val, val_aux; pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); if (IS_ERR(pll)) return ERR_CAST(pll); - /* ensure parent is set to pll_re_vco */ - - val = pll_readl_base(pll); - val_aux = pll_readl(pll_params->aux_reg, pll); - - if (val & PLL_BASE_ENABLE) { - if ((val_aux & PLLE_AUX_PLLRE_SEL) || - (val_aux & PLLE_AUX_PLLP_SEL)) - WARN(1, "pll_e enabled with unsupported parent %s\n", - (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : - "pll_re_vco"); - } else { - val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); - pll_writel(val_aux, pll_params->aux_reg, pll); - } + _clk_plle_tegra_init_parent(pll); clk = _tegra_clk_register_pll(pll, name, parent_name, flags, &tegra_clk_plle_tegra114_ops); @@ -2276,6 +2337,8 @@ static const struct clk_ops tegra_clk_pllss_ops = { .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_ramp_round_rate, .set_rate = clk_pllxc_set_rate, + .save_context = tegra_clk_pll_save_context, + .restore_context = tegra_clk_pll_restore_context, }; struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, @@ -2375,6 +2438,7 @@ struct clk *tegra_clk_register_pllre_tegra210(const char *name, pll_params->vco_min = pll_params->adjust_vco(pll_params, parent_rate); + pll_params->flags |= TEGRA_PLLRE; pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); if (IS_ERR(pll)) return ERR_CAST(pll); @@ -2520,11 +2584,19 @@ static void clk_plle_tegra210_disable(struct clk_hw *hw) spin_unlock_irqrestore(pll->lock, flags); } +static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_pll *pll = to_clk_pll(hw); + + _clk_plle_tegra_init_parent(pll); +} + static const struct clk_ops tegra_clk_plle_tegra210_ops = { .is_enabled = clk_plle_tegra210_is_enabled, .enable = clk_plle_tegra210_enable, .disable = clk_plle_tegra210_disable, .recalc_rate = clk_pll_recalc_rate, + .restore_context = tegra_clk_plle_t210_restore_context, }; struct clk *tegra_clk_register_plle_tegra210(const char *name, @@ -2535,27 +2607,12 @@ struct clk *tegra_clk_register_plle_tegra210(const char *name, { struct tegra_clk_pll *pll; struct clk *clk; - u32 val, val_aux; pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); if (IS_ERR(pll)) return ERR_CAST(pll); - /* ensure parent is set to pll_re_vco */ - - val = pll_readl_base(pll); - val_aux = pll_readl(pll_params->aux_reg, pll); - - if (val & PLLE_BASE_ENABLE) { - if ((val_aux & PLLE_AUX_PLLRE_SEL) || - (val_aux & PLLE_AUX_PLLP_SEL)) - WARN(1, "pll_e enabled with unsupported parent %s\n", - (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : - "pll_re_vco"); - } else { - val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); - pll_writel(val_aux, pll_params->aux_reg, pll); - } + _clk_plle_tegra_init_parent(pll); clk = _tegra_clk_register_pll(pll, name, parent_name, flags, &tegra_clk_plle_tegra210_ops); diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 4721ee030d1c..58397f93166c 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -1602,7 +1602,7 @@ static struct tegra_clk_pll_params pll_x_params = { .pdiv_tohw = pll_qlin_pdiv_to_hw, .div_nmp = &pllx_nmp, .freq_table = pll_x_freq_table, - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, + .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLLX, .dyn_ramp = tegra210_pllx_dyn_ramp, .set_defaults = tegra210_pllx_set_defaults, .calc_rate = tegra210_pll_fixed_mdiv_cfg, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index fb29a8c27873..8532f5150091 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -235,6 +235,8 @@ struct tegra_clk_pll; * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This * flag indicated that it is PLLMB. * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output + * TEGRA_PLLRE - Used to indicate that it is PLLRE. + * TEGRA_PLLX - Used to indicate that it is PLLX. */ struct tegra_clk_pll_params { unsigned long input_min; @@ -301,6 +303,8 @@ struct tegra_clk_pll_params { #define TEGRA_MDIV_NEW BIT(11) #define TEGRA_PLLMB BIT(12) #define TEGRA_PLL_VCO_OUT BIT(13) +#define TEGRA_PLLRE BIT(14) +#define TEGRA_PLLX BIT(15) /** * struct tegra_clk_pll - Tegra PLL clock @@ -310,6 +314,8 @@ struct tegra_clk_pll_params { * @pmc: address of PMC, required to read override bits * @lock: register lock * @params: PLL parameters + * @rate: rate during system suspend and resume + * @pllbase_ctx: pll base register value during suspend and resume */ struct tegra_clk_pll { struct clk_hw hw; @@ -317,6 +323,8 @@ struct tegra_clk_pll { void __iomem *pmc; spinlock_t *lock; struct tegra_clk_pll_params *params; + unsigned long rate; + u32 pllbase_ctx; }; #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) @@ -840,7 +848,7 @@ u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, u8 frac_width, u8 flags); - +void tegra_clk_sync_state_pll(struct clk_hw *hw); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Sun Jul 21 19:40:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="QRUf5mkN"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFWG4mpVz9s7T for ; Mon, 22 Jul 2019 05:42:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727472AbfGUTmR (ORCPT ); Sun, 21 Jul 2019 15:42:17 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15826 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727576AbfGUTlD (ORCPT ); Sun, 21 Jul 2019 15:41:03 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:09 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:02 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 21 Jul 2019 12:41:02 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:01 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:01 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:01 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 07/21] clk: tegra: Support for OSC context save and restore Date: Sun, 21 Jul 2019 12:40:46 -0700 Message-ID: <1563738060-30213-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738069; bh=ty/oblLyoU2dDxcIw3IkPwD9VcYg2tkFrQMwJuj7d9E=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=QRUf5mkN1/gJRgFKKDVvPZA2cLisqnqd4Hnran5LvXqu1gvBkPaQfc/gkrfY5Kmuf eDiGeES2sbkOeJchX6xJiMWG1CcJj+yPxFGLcNqG7ZKOjMU4f7PfkNEYuzF2WMKdlZ Z7wMgMlv+Z5q8mgE2Vm6hTN3muzBgo+YUSh6y1B+BTVkx5+KK6b21z6NzbQrMaeyJs qjD+sUWK+JHU7MPAdtG6nkeG2zapJNmkQrWwKEhJ+7CwLciNJwR5cvXv5/CkydZVcJ fc0YklqzCQmqxMJZe/AxqZ99Ji8GtVPVhc3EANAhgASxV3nTY4lByB6YN00JZpaYiB urYCROFUyHEEA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org X-NVConfidentiality: public This patch adds support for saving OSC clock frequency and the drive-strength during OSC clock init and creates an API to restore OSC control register value from the saved context. This API is invoked by Tegra210 clock driver during system resume to restore the OSC clock settings. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra-fixed.c | 15 +++++++++++++++ drivers/clk/tegra/clk.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c index 8d91b2b191cf..7c6c8abfcde6 100644 --- a/drivers/clk/tegra/clk-tegra-fixed.c +++ b/drivers/clk/tegra/clk-tegra-fixed.c @@ -17,6 +17,10 @@ #define OSC_CTRL 0x50 #define OSC_CTRL_OSC_FREQ_SHIFT 28 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 +#define OSC_CTRL_MASK (0x3f2 | \ + (0xf << OSC_CTRL_OSC_FREQ_SHIFT)) + +static u32 osc_ctrl_ctx; int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, unsigned long *input_freqs, unsigned int num, @@ -29,6 +33,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, unsigned osc_idx; val = readl_relaxed(clk_base + OSC_CTRL); + osc_ctrl_ctx = val & OSC_CTRL_MASK; osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT; if (osc_idx < num) @@ -96,3 +101,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks) *dt_clk = clk; } } + +void tegra_clk_osc_resume(void __iomem *clk_base) +{ + u32 val; + + val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK; + val |= osc_ctrl_ctx; + writel_relaxed(val, clk_base + OSC_CTRL); + fence_udelay(2, clk_base); +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 8532f5150091..3cd003b7512a 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -849,6 +849,7 @@ int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, u8 frac_width, u8 flags); void tegra_clk_sync_state_pll(struct clk_hw *hw); +void tegra_clk_osc_resume(void __iomem *clk_base); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Sun Jul 21 19:40:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134591 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Ed1KIkJ3"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFW92YlJz9sBF for ; Mon, 22 Jul 2019 05:42:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727620AbfGUTlI (ORCPT ); Sun, 21 Jul 2019 15:41:08 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15833 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727437AbfGUTlG (ORCPT ); Sun, 21 Jul 2019 15:41:06 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:11 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:03 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 21 Jul 2019 12:41:03 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:03 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:03 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:03 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:03 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 08/21] clk: tegra: clk-periph: Add save and restore support Date: Sun, 21 Jul 2019 12:40:47 -0700 Message-ID: <1563738060-30213-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738071; bh=K4EMK7Ckti8Q7Dg4JGSGEsr+mR5YceM/9vT0vz2nTmA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Ed1KIkJ3OkYSmHMKE5vh++DK0fVnQEMUzw1gRTxFObu8bhLy3TzeYcA/GV6QOdl9X UuirkdciiirJlOJfb13cjx4gbuqXcd4whLP8CPsyIqbvGUno63mSi9K5ecBUI5a5Z2 OWPmPyt6p2aFbnnj+F8zfpgQ8J9VPe+149nwH5awHg9uc/JOeScG+r0nRXAPH4zClb 2zCiSSa5hdBzRWA6jyuP8eT+6a9Ofe096sb2dlznWEsuzeupc22dyIXpbd+AeMwAst urDz5JZo1CJuhrIMYd7qikeVisFisknrwcSL6LCapX/kG0XAqyT136aUm4F3Gqv4FR 5j8Pl8BQ4TsRA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements save and restore context for peripheral fixed clock ops, peripheral gate clock ops, sdmmc mux clock ops, and peripheral clock ops. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry clock and reset state of peripherals is saved and on resume they are restored to have clocks back to same rate and state as before suspend. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-periph-fixed.c | 33 +++++++++++++++++++++++++++ drivers/clk/tegra/clk-periph-gate.c | 34 ++++++++++++++++++++++++++++ drivers/clk/tegra/clk-periph.c | 43 ++++++++++++++++++++++++++++++++++++ drivers/clk/tegra/clk-sdmmc-mux.c | 30 +++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 8 +++++++ 5 files changed, 148 insertions(+) diff --git a/drivers/clk/tegra/clk-periph-fixed.c b/drivers/clk/tegra/clk-periph-fixed.c index c088e7a280df..21b24530fa00 100644 --- a/drivers/clk/tegra/clk-periph-fixed.c +++ b/drivers/clk/tegra/clk-periph-fixed.c @@ -60,11 +60,44 @@ tegra_clk_periph_fixed_recalc_rate(struct clk_hw *hw, return (unsigned long)rate; } +static int tegra_clk_periph_fixed_save_context(struct clk_hw *hw) +{ + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); + u32 mask = 1 << (fixed->num % 32); + + fixed->enb_ctx = readl_relaxed(fixed->base + fixed->regs->enb_reg) & + mask; + fixed->rst_ctx = readl_relaxed(fixed->base + fixed->regs->rst_reg) & + mask; + + return 0; +} + +static void tegra_clk_periph_fixed_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); + u32 mask = 1 << (fixed->num % 32); + + if (fixed->enb_ctx) + writel_relaxed(mask, fixed->base + fixed->regs->enb_set_reg); + else + writel_relaxed(mask, fixed->base + fixed->regs->enb_clr_reg); + + udelay(2); + + if (!fixed->rst_ctx) { + udelay(5); /* reset propogation delay */ + writel_relaxed(mask, fixed->base + fixed->regs->rst_reg); + } +} + static const struct clk_ops tegra_clk_periph_fixed_ops = { .is_enabled = tegra_clk_periph_fixed_is_enabled, .enable = tegra_clk_periph_fixed_enable, .disable = tegra_clk_periph_fixed_disable, .recalc_rate = tegra_clk_periph_fixed_recalc_rate, + .save_context = tegra_clk_periph_fixed_save_context, + .restore_context = tegra_clk_periph_fixed_restore_context, }; struct clk *tegra_clk_register_periph_fixed(const char *name, diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 4b31beefc9fc..6ba5b08e0787 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -25,6 +25,8 @@ static DEFINE_SPINLOCK(periph_ref_lock); #define read_rst(gate) \ readl_relaxed(gate->clk_base + (gate->regs->rst_reg)) +#define write_rst_set(val, gate) \ + writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg)) #define write_rst_clr(val, gate) \ writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg)) @@ -110,10 +112,42 @@ static void clk_periph_disable(struct clk_hw *hw) spin_unlock_irqrestore(&periph_ref_lock, flags); } +static int clk_periph_gate_save_context(struct clk_hw *hw) +{ + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); + + gate->clk_state_ctx = read_enb(gate) & periph_clk_to_bit(gate); + gate->rst_state_ctx = read_rst(gate) & periph_clk_to_bit(gate); + + return 0; +} + +static void clk_periph_gate_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); + + if (gate->clk_state_ctx) + write_enb_set(periph_clk_to_bit(gate), gate); + else + write_enb_clr(periph_clk_to_bit(gate), gate); + + udelay(5); + + if (!(gate->flags & TEGRA_PERIPH_NO_RESET) && + !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) { + if (gate->rst_state_ctx) + write_rst_set(periph_clk_to_bit(gate), gate); + else + write_rst_clr(periph_clk_to_bit(gate), gate); + } +} + const struct clk_ops tegra_clk_periph_gate_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .save_context = clk_periph_gate_save_context, + .restore_context = clk_periph_gate_restore_context, }; struct clk *tegra_clk_register_periph_gate(const char *name, diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 58437da25156..b29a1ed2ec08 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -99,6 +100,42 @@ static void clk_periph_disable(struct clk_hw *hw) gate_ops->disable(gate_hw); } +static int clk_periph_save_context(struct clk_hw *hw) +{ + struct tegra_clk_periph *periph = to_clk_periph(hw); + const struct clk_ops *gate_ops = periph->gate_ops; + struct clk_hw *gate_hw = &periph->gate.hw; + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + if (!(periph->gate.flags & TEGRA_PERIPH_NO_GATE)) + gate_ops->save_context(gate_hw); + + if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV)) + periph->rate_ctx = clk_periph_recalc_rate(hw, parent_rate); + + periph->parent_ctx = clk_periph_get_parent(hw); + + return 0; +} + +static void clk_periph_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_periph *periph = to_clk_periph(hw); + const struct clk_ops *gate_ops = periph->gate_ops; + struct clk_hw *gate_hw = &periph->gate.hw; + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + clk_periph_set_parent(hw, periph->parent_ctx); + + if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV)) + clk_periph_set_rate(hw, periph->rate_ctx, parent_rate); + + if (!(periph->gate.flags & TEGRA_PERIPH_NO_GATE)) + gate_ops->restore_context(gate_hw); +} + const struct clk_ops tegra_clk_periph_ops = { .get_parent = clk_periph_get_parent, .set_parent = clk_periph_set_parent, @@ -108,6 +145,8 @@ const struct clk_ops tegra_clk_periph_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .save_context = clk_periph_save_context, + .restore_context = clk_periph_restore_context, }; static const struct clk_ops tegra_clk_periph_nodiv_ops = { @@ -116,6 +155,8 @@ static const struct clk_ops tegra_clk_periph_nodiv_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .save_context = clk_periph_save_context, + .restore_context = clk_periph_restore_context, }; static const struct clk_ops tegra_clk_periph_no_gate_ops = { @@ -124,6 +165,8 @@ static const struct clk_ops tegra_clk_periph_no_gate_ops = { .recalc_rate = clk_periph_recalc_rate, .round_rate = clk_periph_round_rate, .set_rate = clk_periph_set_rate, + .save_context = clk_periph_save_context, + .restore_context = clk_periph_restore_context, }; static struct clk *_tegra_clk_register_periph(const char *name, diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmmc-mux.c index a5cd3e31dbae..fffe08e02c10 100644 --- a/drivers/clk/tegra/clk-sdmmc-mux.c +++ b/drivers/clk/tegra/clk-sdmmc-mux.c @@ -194,6 +194,34 @@ static void clk_sdmmc_mux_disable(struct clk_hw *hw) gate_ops->disable(gate_hw); } +static int clk_sdmmc_mux_save_context(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + sdmmc_mux->rate_ctx = clk_sdmmc_mux_recalc_rate(hw, parent_rate); + sdmmc_mux->parent_ctx = clk_sdmmc_mux_get_parent(hw); + gate_ops->save_context(gate_hw); + + return 0; +} + +static void clk_sdmmc_mux_restore_context(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + clk_sdmmc_mux_set_parent(hw, sdmmc_mux->parent_ctx); + clk_sdmmc_mux_set_rate(hw, sdmmc_mux->rate_ctx, parent_rate); + gate_ops->restore_context(gate_hw); +} + static const struct clk_ops tegra_clk_sdmmc_mux_ops = { .get_parent = clk_sdmmc_mux_get_parent, .set_parent = clk_sdmmc_mux_set_parent, @@ -203,6 +231,8 @@ static const struct clk_ops tegra_clk_sdmmc_mux_ops = { .is_enabled = clk_sdmmc_mux_is_enabled, .enable = clk_sdmmc_mux_enable, .disable = clk_sdmmc_mux_disable, + .save_context = clk_sdmmc_mux_save_context, + .restore_context = clk_sdmmc_mux_restore_context, }; struct clk *tegra_clk_register_sdmmc_mux_div(const char *name, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 3cd003b7512a..ac6de3a0b91f 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -523,6 +523,8 @@ struct tegra_clk_periph_gate { int clk_num; int *enable_refcnt; const struct tegra_clk_periph_regs *regs; + bool clk_state_ctx; + bool rst_state_ctx; }; #define to_clk_periph_gate(_hw) \ @@ -549,6 +551,8 @@ struct tegra_clk_periph_fixed { unsigned int mul; unsigned int div; unsigned int num; + bool enb_ctx; + bool rst_ctx; }; struct clk *tegra_clk_register_periph_fixed(const char *name, @@ -581,6 +585,8 @@ struct tegra_clk_periph { const struct clk_ops *mux_ops; const struct clk_ops *div_ops; const struct clk_ops *gate_ops; + unsigned long rate_ctx; + u8 parent_ctx; }; #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) @@ -732,6 +738,8 @@ struct tegra_sdmmc_mux { const struct clk_ops *gate_ops; struct tegra_clk_periph_gate gate; u8 div_flags; + unsigned long rate_ctx; + u8 parent_ctx; }; #define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw) From patchwork Sun Jul 21 19:40:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134568 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="U75hOrfw"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFV446bQz9s8m for ; Mon, 22 Jul 2019 05:41:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727622AbfGUTlI (ORCPT ); Sun, 21 Jul 2019 15:41:08 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15841 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727601AbfGUTlG (ORCPT ); Sun, 21 Jul 2019 15:41:06 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:12 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:05 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:41:05 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:04 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:05 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:04 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Date: Sun, 21 Jul 2019 12:40:48 -0700 Message-ID: <1563738060-30213-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738072; bh=3K7x/Oh8TQ/N8+NUlmWQ/I1v4OLQzS5q7gcJIEIHpvw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=U75hOrfw9Zo6SQfx5tUtMiuAHkmqQ6n3fODs1qXTqxclkbzlZ41U3iKBhjnZW6+hO /t/Rk0n48gxj3qT3ct8xjZDueHfgx6YxynZF7/FdsV5NdYJqb2qPVAaTptqSeOcex5 b06gawEKA+aLghLMT7d/54aw2ADrsWde4ZtJTPM3QGewQ/Ccvo7V/enCBBR6MEyhZ7 BluJsj8aLn76Al81Xjf82q6sbiaVbOZEDBr1fpQOPn0Ayjsa5zZZCMT59vRbmqogeQ QhPdWW/s/VGS0M6smJNDZAlU7lqlkdVLxpeyLMKjnvDY3xwgPyXBtOPI+Wz5c7TaW2 Oa/CTRtBtaCDA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch has a fix to enable PLLP branches to CPU before changing the CPU clusters clock source to PLLP for Gen5 Super clock. During system suspend entry and exit, CPU source will be switched to PLLP and this needs PLLP branches to be enabled to CPU prior to the switch. On system resume, warmboot code enables PLLP branches to CPU and powers up the CPU with PLLP clock source. Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-super.c | 11 +++++++++++ drivers/clk/tegra/clk-tegra-super-gen4.c | 4 ++-- drivers/clk/tegra/clk.h | 4 ++++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c index 39ef31b46df5..d73c587e4853 100644 --- a/drivers/clk/tegra/clk-super.c +++ b/drivers/clk/tegra/clk-super.c @@ -28,6 +28,9 @@ #define super_state_to_src_shift(m, s) ((m->width * s)) #define super_state_to_src_mask(m) (((1 << m->width) - 1)) +#define CCLK_SRC_PLLP_OUT0 4 +#define CCLK_SRC_PLLP_OUT4 5 + static u8 clk_super_get_parent(struct clk_hw *hw) { struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); @@ -97,6 +100,14 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index) if (index == mux->div2_index) index = mux->pllx_index; } + + /* + * Enable PLLP branches to CPU before selecting PLLP source + */ + if ((mux->flags & TEGRA_CPU_CLK) && + ((index == CCLK_SRC_PLLP_OUT0) || (index == CCLK_SRC_PLLP_OUT4))) + tegra_clk_set_pllp_out_cpu(true); + val &= ~((super_state_to_src_mask(mux)) << shift); val |= (index & (super_state_to_src_mask(mux))) << shift; diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index cdfe7c9697e1..cd208d0eca2a 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -180,7 +180,7 @@ static void __init tegra_super_clk_init(void __iomem *clk_base, gen_info->num_cclk_g_parents, CLK_SET_RATE_PARENT, clk_base + CCLKG_BURST_POLICY, - 0, 4, 8, 0, NULL); + TEGRA_CPU_CLK, 4, 8, 0, NULL); } else { clk = tegra_clk_register_super_mux("cclk_g", gen_info->cclk_g_parents, @@ -201,7 +201,7 @@ static void __init tegra_super_clk_init(void __iomem *clk_base, gen_info->num_cclk_lp_parents, CLK_SET_RATE_PARENT, clk_base + CCLKLP_BURST_POLICY, - 0, 4, 8, 0, NULL); + TEGRA_CPU_CLK, 4, 8, 0, NULL); } else { clk = tegra_clk_register_super_mux("cclk_lp", gen_info->cclk_lp_parents, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index ac6de3a0b91f..c357b49e49b0 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -694,6 +694,9 @@ struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, * Flags: * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates * that this is LP cluster clock. + * TEGRA_CPU_CLK - This flag indicates this is CPU cluster clock. To use PLLP + * for CPU clock source, need to enable PLLP branches to CPU by setting the + * additional bit PLLP_OUT_CPU for gen5 super clock. */ struct tegra_clk_super_mux { struct clk_hw hw; @@ -710,6 +713,7 @@ struct tegra_clk_super_mux { #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) #define TEGRA_DIVIDER_2 BIT(0) +#define TEGRA_CPU_CLK BIT(1) extern const struct clk_ops tegra_clk_super_ops; struct clk *tegra_clk_register_super_mux(const char *name, From patchwork Sun Jul 21 19:40:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134593 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="aqIx5deN"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFWB24NPz9sML for ; Mon, 22 Jul 2019 05:42:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727631AbfGUTmM (ORCPT ); Sun, 21 Jul 2019 15:42:12 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12489 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727460AbfGUTlI (ORCPT ); Sun, 21 Jul 2019 15:41:08 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:07 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:06 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:41:06 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:06 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:06 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:06 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 10/21] clk: tegra: clk-super: Add save and restore support Date: Sun, 21 Jul 2019 12:40:49 -0700 Message-ID: <1563738060-30213-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738067; bh=UpaDe5/XKuz7sPTOfw95w7QpxrM2zZbYu41J4GgqNqE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=aqIx5deNisjmMGELv25qOxcO5Cq3V5YfHTK4p3JeuHYWVMYxdg9awisH53f2zSmk/ umjBb+B6dNmFWSTBEUUNoUu0pClnp5ZK6XNfd5GDhPMQ0AV+eC8VqMJchlNsUKHEy+ uotpOJELzgGDz+TA7HybY5Ns2cKlyZpA7i7Ru3O6jVXF8+xqfuxfZPCBwCsHw6rIlQ dXR6kfFpdvj8GXL4cab/75LeukB0bes5cBm3Gt9LjsHpCKTpLDVBVZiEn5MZV/RdHp BMxrToHwOazE9bqZq/iUKWi0OGYrW5EX6ChnXjaNaiBC5q5sHnlBd1jTzNEEgG4Z7B oKSSABsCGgfmw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements save and restore context for clk_super_mux and clk_super. During system supend, core power goes off the and context of Tegra CAR registers is lost. So during suspend entry, context of super clock registers are saved through save_context clk_ops and are restored through restore_context clk_ops to have them in same state as before suspend. Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-super.c | 40 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 1 + 2 files changed, 41 insertions(+) diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c index d73c587e4853..84492afd3f1d 100644 --- a/drivers/clk/tegra/clk-super.c +++ b/drivers/clk/tegra/clk-super.c @@ -121,9 +121,27 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index) return err; } +static int clk_super_mux_save_context(struct clk_hw *hw) +{ + struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); + + mux->parent_index_ctx = clk_super_get_parent(hw); + + return 0; +} + +static void clk_super_mux_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); + + clk_super_set_parent(hw, mux->parent_index_ctx); +} + static const struct clk_ops tegra_clk_super_mux_ops = { .get_parent = clk_super_get_parent, .set_parent = clk_super_set_parent, + .save_context = clk_super_mux_save_context, + .restore_context = clk_super_mux_restore_context, }; static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate, @@ -159,12 +177,34 @@ static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate, return super->div_ops->set_rate(div_hw, rate, parent_rate); } +static int clk_super_save_context(struct clk_hw *hw) +{ + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); + struct clk_hw *div_hw = &super->frac_div.hw; + + super->parent_index_ctx = clk_super_get_parent(hw); + + return super->div_ops->save_context(div_hw); +} + +static void clk_super_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); + struct clk_hw *div_hw = &super->frac_div.hw; + + clk_super_set_parent(hw, super->parent_index_ctx); + + super->div_ops->restore_context(div_hw); +} + const struct clk_ops tegra_clk_super_ops = { .get_parent = clk_super_get_parent, .set_parent = clk_super_set_parent, .set_rate = clk_super_set_rate, .round_rate = clk_super_round_rate, .recalc_rate = clk_super_recalc_rate, + .save_context = clk_super_save_context, + .restore_context = clk_super_restore_context, }; struct clk *tegra_clk_register_super_mux(const char *name, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index c357b49e49b0..562a3ee2d537 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -708,6 +708,7 @@ struct tegra_clk_super_mux { u8 div2_index; u8 pllx_index; spinlock_t *lock; + u8 parent_index_ctx; }; #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) From patchwork Sun Jul 21 19:40:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134588 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="o7K0FD3h"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFW20vdTz9sBF for ; Mon, 22 Jul 2019 05:42:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727632AbfGUTlL (ORCPT ); Sun, 21 Jul 2019 15:41:11 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:9007 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727625AbfGUTlJ (ORCPT ); Sun, 21 Jul 2019 15:41:09 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:06 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:08 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:41:08 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:08 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:08 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:07 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:08 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 11/21] clk: tegra: clk-dfll: Add suspend and resume support Date: Sun, 21 Jul 2019 12:40:50 -0700 Message-ID: <1563738060-30213-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738066; bh=9ijUqrJ/k0zBr3NzGVytMDfceIsaTvOJsIgwEsZOjyU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=o7K0FD3hUXnH6w7/M9TkXLZDDz9Ew8X7EVG+DkLNNEr3rd0RdW2kCQ5kB0yKqkRW4 XQFgIzKrMeRO+LF4be7clX3hhGMRa3CdvaAEi65MvljhDP72lGqlr277ACf4/JYohY XxTcwl0VXlyYlP2QKUPWK68/0WWkx0O6IkMI8eFWfxwpl7NDxnR4GsHLI7ADdxB7Zk t5FtA/5/VcyqZ3BymBmZmR5yPZfHUXTjRQTCBDKrCgmvV96D5TbRW7c9hdx+OGgbSv Ad9xL/RVcgtP7wxYBxH21z7TdZUSexd/Mx1OHNR1pe12rUPEP8Rz8WB4TtmBMHHhyi xwwh8bglRjFjw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements DFLL suspend and resume operation. During system suspend entry, CPU clock will switch CPU to safe clock source of PLLP and disables DFLL clock output. DFLL driver suspend confirms DFLL disable state and errors out on being active. DFLL is re-initialized during the DFLL driver resume as it goes through complete reset during suspend entry. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-dfll.c | 44 ++++++++++++++++++++++++++++++ drivers/clk/tegra/clk-dfll.h | 2 ++ drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 1 + 3 files changed, 47 insertions(+) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index f8688c2ddf1a..7dcad4ccd0ae 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -1513,6 +1513,50 @@ static int dfll_init(struct tegra_dfll *td) return ret; } +/** + * tegra_dfll_suspend - check DFLL is disabled + * @dev: DFLL device * + * + * DFLL clock should be disabled by the CPUFreq driver. So, make + * sure it is disabled and disable all clocks needed by the DFLL. + */ +int tegra_dfll_suspend(struct device *dev) +{ + struct tegra_dfll *td = dev_get_drvdata(dev); + + if (dfll_is_running(td)) { + dev_warn(td->dev, "failed disabling the dfll\n"); + return -EBUSY; + } + + pm_runtime_disable(dev); + + clk_unprepare(td->ref_clk); + clk_unprepare(td->soc_clk); + clk_unprepare(td->i2c_clk); + + reset_control_assert(td->dvco_rst); + + return 0; +} +EXPORT_SYMBOL(tegra_dfll_suspend); + +/** + * tegra_dfll_resume - reinitialize DFLL on resume + * @pdev: DFLL instance + * + * Re-initialize DFLL on resume as it gets disabled and reset during + * suspend entry. DFLL clock is enabled in closed loop mode later + * and CPU frequency will be switched to DFLL output. + */ +int tegra_dfll_resume(struct device *dev) +{ + struct tegra_dfll *td = dev_get_drvdata(dev); + + return dfll_init(td); +} +EXPORT_SYMBOL(tegra_dfll_resume); + /* * DT data fetch */ diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index 1b14ebe7268b..fb209eb5f365 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -42,5 +42,7 @@ int tegra_dfll_register(struct platform_device *pdev, struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev); int tegra_dfll_runtime_suspend(struct device *dev); int tegra_dfll_runtime_resume(struct device *dev); +int tegra_dfll_suspend(struct device *dev); +int tegra_dfll_resume(struct device *dev); #endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */ diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index e84b6d52cbbd..2ac2679d696d 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -631,6 +631,7 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev) static const struct dev_pm_ops tegra124_dfll_pm_ops = { SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend, tegra_dfll_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(tegra_dfll_suspend, tegra_dfll_resume) }; static struct platform_driver tegra124_dfll_fcpu_driver = { From patchwork Sun Jul 21 19:40:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134589 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="NME1X1iT"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFW62Hccz9sBF for ; Mon, 22 Jul 2019 05:42:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727777AbfGUTmF (ORCPT ); Sun, 21 Jul 2019 15:42:05 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15853 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727631AbfGUTlL (ORCPT ); Sun, 21 Jul 2019 15:41:11 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:17 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:10 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 21 Jul 2019 12:41:10 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:09 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:09 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:09 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:09 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 12/21] cpufreq: tegra124: Add suspend and resume support Date: Sun, 21 Jul 2019 12:40:51 -0700 Message-ID: <1563738060-30213-13-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738077; bh=ERM45gzILmBTa9m60jszJM5aBp4VqzLlD5QiVJxaQLQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=NME1X1iTJsBLu1Mi6wjnP50EmLtURbBbGNdHSSYOvhm7CBrXin0jYMspYYKTotsbY medU6u9QbGFnlXNmisA3dDS//8X+mk0fWMc4DqS0teHcmTSBOtoLMURehnXI4TOOGK SGKn5ddgTyxDXhBYigSHWVruen95P63hm53XQIcB9KZf5B/7qAIRC+sc2yKqNJWaXO ylHtfRTr9hT7r9FyFf+h7flv0Bul0YuUQ0r9W5ez5/SSSW6rA87/SeeqBVhUF3gfq+ oAY15IrjQcqoCe2ydht2MykT9eRNvxikI8MaP+9w+ouq9vnS2Bezt9gVyTQBizWmKX dygWqDFahnlbQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch adds suspend and resume pm ops for cpufreq driver. PLLP is the safe clock source for CPU during system suspend and resume as PLLP rate is below the CPU Fmax at Vmin. CPUFreq driver suspend switches the CPU clock source to PLLP and disables the DFLL clock. During system resume, warmboot code powers up the CPU with PLLP clock source. So CPUFreq driver resume enabled DFLL clock and switches CPU back to DFLL clock source. Signed-off-by: Sowjanya Komatineni --- drivers/cpufreq/tegra124-cpufreq.c | 46 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index 4f0c637b3b49..4eff63379b0f 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -6,6 +6,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include @@ -128,8 +129,53 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) return ret; } +static int tegra124_cpufreq_suspend(struct device *dev) +{ + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev); + + /* + * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to + * use during suspend and resume. So, switch the CPU clock source + * to PLLP and disable DFLL. + */ + clk_set_parent(priv->cpu_clk, priv->pllp_clk); + + /* disable DFLL clock */ + clk_disable_unprepare(priv->dfll_clk); + + return 0; +} + +static int tegra124_cpufreq_resume(struct device *dev) +{ + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev); + int ret = 0; + + /* + * Warmboot code powers up the CPU with PLLP clock source. + * Enable DFLL clock and switch CPU clock source back to DFLL. + */ + ret = clk_prepare_enable(priv->dfll_clk); + if (ret) { + dev_warn(dev, "failed to enable DFLL clock for CPU\n"); + clk_set_parent(priv->cpu_clk, priv->pllp_clk); + disable_cpufreq(); + return ret; + } + + clk_set_parent(priv->cpu_clk, priv->dfll_clk); + + return ret; +} + +static const struct dev_pm_ops tegra124_cpufreq_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend, + tegra124_cpufreq_resume) +}; + static struct platform_driver tegra124_cpufreq_platdrv = { .driver.name = "cpufreq-tegra124", + .driver.pm = &tegra124_cpufreq_pm_ops, .probe = tegra124_cpufreq_probe, }; From patchwork Sun Jul 21 19:40:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134569 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Nz7jF2mv"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFV54Rz5z9sMr for ; Mon, 22 Jul 2019 05:41:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727660AbfGUTlN (ORCPT ); Sun, 21 Jul 2019 15:41:13 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:9018 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727647AbfGUTlM (ORCPT ); Sun, 21 Jul 2019 15:41:12 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:09 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:11 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:41:11 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:11 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:11 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:11 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 13/21] clk: tegra210: Use fence_udelay during PLLU init Date: Sun, 21 Jul 2019 12:40:52 -0700 Message-ID: <1563738060-30213-14-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738069; bh=MqRiGcV15fZ3EzTQ+28GrOZLwzwn/Vk43BBlg4BM8S4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Nz7jF2mv9CLzYSb3lx2v+Ffjpd7QmI+2f113dGNa7IzSKCmcFpUJzQc1P57ijuLD+ JAyJ3yCsujN5FwmwpuVNfTklJBydUbZiww8skquTnS0WntqMWps0pFLTVFPvdVXuTR LCKGRR4FldthdjmuDyjQf80BGCTQZmP1yomCTpneqlDRPbXoLdoIAF6V4JcizWWzhk ck1R/HK0DHau+GSPpyu9evpsHqrZeu5VccnEDnJlS6jODE2lWcRbR1dW0kWKEIq6J/ b58oUO89zQPG4tprSuLhWJ2/0KbXL8CNnwxtNm/iKaIdZ3SR/Y5GNEDYR9pD6UzxU1 q/Wfr2F1TUsHg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch uses fence_udelay rather than udelay during PLLU initialization to ensure writes to clock registers happens before waiting for specified delay. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 58397f93166c..55a88c0824a5 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2841,7 +2841,7 @@ static int tegra210_enable_pllu(void) reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); reg &= ~BIT(pllu.params->iddq_bit_idx); writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); - udelay(5); + fence_udelay(5, clk_base); reg = readl_relaxed(clk_base + PLLU_BASE); reg &= ~GENMASK(20, 0); @@ -2849,7 +2849,7 @@ static int tegra210_enable_pllu(void) reg |= fentry->n << 8; reg |= fentry->p << 16; writel(reg, clk_base + PLLU_BASE); - udelay(1); + fence_udelay(1, clk_base); reg |= PLL_ENABLE; writel(reg, clk_base + PLLU_BASE); @@ -2895,12 +2895,12 @@ static int tegra210_init_pllu(void) reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); - udelay(1); + fence_udelay(1, clk_base); reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); - udelay(1); + fence_udelay(1, clk_base); reg = readl_relaxed(clk_base + PLLU_BASE); reg &= ~PLLU_BASE_CLKENABLE_USB; From patchwork Sun Jul 21 19:40:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134583 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="fnPQrRla"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFVr0jLLz9sML for ; Mon, 22 Jul 2019 05:41:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727719AbfGUTlR (ORCPT ); Sun, 21 Jul 2019 15:41:17 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15863 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727693AbfGUTlP (ORCPT ); Sun, 21 Jul 2019 15:41:15 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:21 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:14 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:41:14 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:13 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:12 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:12 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:12 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 14/21] clk: tegra210: Add suspend and resume support Date: Sun, 21 Jul 2019 12:40:53 -0700 Message-ID: <1563738060-30213-15-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738081; bh=0khD/rB4QyPbALxHvhU2heh9OJs2apoCE/hDpvp8TRQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=fnPQrRlaqUXdR9bcOvrkzQuhOFSFI5TeV9NdK00gKnBfUmvlU5+oNnpNraf4+s9q2 3NFpTf7GqqtH2unLiqXdzvR5dLOYBb+BFDAZNx0wR0hoLawM8qLMAU38+aoJ5fk6Qe kEvs3XQoSt2KVH8d28OAYIo7UL91z7VT/BJSOjoZTlQEQatiIXvoNSV20Rk42JUTTS W25vbzZLZ32ynKLeO8KyiLGhyrRgjlh9sTDsZs/HjDWg/uZvCsGWNtamurvrzlRveT 2xtsEi0hMvJjIjqBUGGbBoJCClggP883Lsw+vHEnBCQNo9yLNWiJd7aeax+V28K2Kn GuRGZTeYEt5zg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch adds support for clk: tegra210: suspend-resume. All the CAR controller settings are lost on suspend when core power goes off. This patch has implementation for saving and restoring all PLLs and clocks context during system suspend and resume to have the clocks back to same state for normal operation. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 68 ++++++++++++++++++++++++++++++++++++++-- drivers/clk/tegra/clk.c | 14 +++++++++ drivers/clk/tegra/clk.h | 1 + 3 files changed, 80 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 55a88c0824a5..68271873acc1 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -220,11 +221,15 @@ #define CLK_M_DIVISOR_SHIFT 2 #define CLK_M_DIVISOR_MASK 0x3 +#define CLK_MASK_ARM 0x44 +#define MISC_CLK_ENB 0x48 + #define RST_DFLL_DVCO 0x2f4 #define DVFS_DFLL_RESET_SHIFT 0 #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac +#define CPU_SOFTRST_CTRL 0x380 #define LVL2_CLK_GATE_OVRA 0xf8 #define LVL2_CLK_GATE_OVRC 0x3a0 @@ -2825,6 +2830,7 @@ static int tegra210_enable_pllu(void) struct tegra_clk_pll_freq_table *fentry; struct tegra_clk_pll pllu; u32 reg; + int ret; for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) { if (fentry->input_rate == pll_ref_freq) @@ -2853,9 +2859,8 @@ static int tegra210_enable_pllu(void) reg |= PLL_ENABLE; writel(reg, clk_base + PLLU_BASE); - readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg, - reg & PLL_BASE_LOCK, 2, 1000); - if (!(reg & PLL_BASE_LOCK)) { + ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK); + if (ret) { pr_err("Timed out waiting for PLL_U to lock\n"); return -ETIMEDOUT; } @@ -3288,6 +3293,56 @@ static void tegra210_disable_cpu_clock(u32 cpu) } #ifdef CONFIG_PM_SLEEP +#define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4)) +#define car_writel(_val, _base, _off) \ + writel_relaxed(_val, clk_base + (_base) + ((_off) * 4)) + +static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx; +static u32 cpu_softrst_ctx[3]; + +static int tegra210_clk_suspend(void) +{ + unsigned int i; + + clk_save_context(); + + /* + * save the bootloader configured clock registers SPARE_REG0, + * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL + */ + spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0); + misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB); + clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM); + + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++) + cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i); + + return 0; +} + +static void tegra210_clk_resume(void) +{ + unsigned int i; + + tegra_clk_osc_resume(clk_base); + + /* + * restore the bootloader configured clock registers SPARE_REG0, + * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL from saved context. + */ + writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0); + writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB); + writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM); + + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++) + car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i); + + fence_udelay(5, clk_base); + + tegra210_init_pllu(); + clk_restore_context(); +} + static void tegra210_cpu_clock_suspend(void) { /* switch coresite to clk_m, save off original source */ @@ -3303,6 +3358,11 @@ static void tegra210_cpu_clock_resume(void) } #endif +static struct syscore_ops tegra_clk_syscore_ops = { + .suspend = tegra210_clk_suspend, + .resume = tegra210_clk_resume, +}; + static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { .wait_for_reset = tegra210_wait_cpu_in_reset, .disable_clock = tegra210_disable_cpu_clock, @@ -3587,5 +3647,7 @@ static void __init tegra210_clock_init(struct device_node *np) tegra210_mbist_clk_init(); tegra_cpu_car_ops = &tegra210_cpu_car_ops; + + register_syscore_ops(&tegra_clk_syscore_ops); } CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 573e3c967ae1..eb08047fd02f 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -23,6 +23,7 @@ #define CLK_OUT_ENB_W 0x364 #define CLK_OUT_ENB_X 0x280 #define CLK_OUT_ENB_Y 0x298 +#define CLK_ENB_PLLP_OUT_CPU BIT(31) #define CLK_OUT_ENB_SET_L 0x320 #define CLK_OUT_ENB_CLR_L 0x324 #define CLK_OUT_ENB_SET_H 0x328 @@ -199,6 +200,19 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid) } } +void tegra_clk_set_pllp_out_cpu(bool enable) +{ + u32 val; + + val = readl_relaxed(clk_base + CLK_OUT_ENB_Y); + if (enable) + val |= CLK_ENB_PLLP_OUT_CPU; + else + val &= ~CLK_ENB_PLLP_OUT_CPU; + + writel_relaxed(val, clk_base + CLK_OUT_ENB_Y); +} + struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) { clk_base = regs; diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 562a3ee2d537..0ffa763c755b 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -863,6 +863,7 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, u8 frac_width, u8 flags); void tegra_clk_sync_state_pll(struct clk_hw *hw); void tegra_clk_osc_resume(void __iomem *clk_base); +void tegra_clk_set_pllp_out_cpu(bool enable); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Sun Jul 21 19:40:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134584 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="AITjM1aG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFVs2j3Mz9s3l for ; Mon, 22 Jul 2019 05:41:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726983AbfGUTlz (ORCPT ); Sun, 21 Jul 2019 15:41:55 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12505 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727701AbfGUTlQ (ORCPT ); Sun, 21 Jul 2019 15:41:16 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:14 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:41:14 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:14 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:14 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:14 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:14 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 15/21] soc/tegra: pmc: Allow to support more tegras wake Date: Sun, 21 Jul 2019 12:40:54 -0700 Message-ID: <1563738060-30213-16-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738075; bh=2GvhhOatfsM2bYQzuVGHbcx4hR8oEy2cTWpoIl1r38Y=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=AITjM1aGPdD4lmUUk4uXns+fzXBCEl4XkC6g3344P45IH4QHtug8/UJA0fK35KTVf AAMxr4XDrwLtqt1mxPS1Gct+QcwdF+w3fLEBsoO+H8JrfzLH2+2ofc/aMH2UY1Sm1D cB1BCevO/uCzHUEGdqIHlnWweJoKp7b00Yi57hE4/ku+GTf4UgPVXfBwFJoEG1Yeup 5DodkQwChmNcX1gWNDnZ+4sFBrVmMyBPBMV1nyIi75lQURenovAsYtqYDrsahgf+g3 XfLDBWt6PhJ0pE0FGq/n/vMtZWowIKknJqWehBaulLLYX+CcTasEkzjkfqOXtK5N6f XAT+hIAgPGe3A== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch allows to create separate irq_set_wake and irq_set_type implementations for different tegra designs PMC that has different wake models which require difference wake registers and different programming sequence. AOWAKE model support is available for Tegra186 and Tegra194 only and it resides within PMC and supports tiered wake architecture. Tegra210 and prior tegra designs uses PMC directly to receive wake events and coordinate the wake sequence. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 9f9c1c677cf4..91c84d0e66ae 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -226,6 +226,8 @@ struct tegra_pmc_soc { void (*setup_irq_polarity)(struct tegra_pmc *pmc, struct device_node *np, bool invert); + int (*irq_set_wake)(struct irq_data *data, unsigned int on); + int (*irq_set_type)(struct irq_data *data, unsigned int type); const char * const *reset_sources; unsigned int num_reset_sources; @@ -1920,7 +1922,7 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; -static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); unsigned int offset, bit; @@ -1952,7 +1954,7 @@ static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } -static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type) +static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); u32 value; @@ -2006,8 +2008,8 @@ static int tegra_pmc_irq_init(struct tegra_pmc *pmc) pmc->irq.irq_unmask = irq_chip_unmask_parent; pmc->irq.irq_eoi = irq_chip_eoi_parent; pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent; - pmc->irq.irq_set_type = tegra_pmc_irq_set_type; - pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake; + pmc->irq.irq_set_type = pmc->soc->irq_set_type; + pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, &tegra_pmc_irq_domain_ops, pmc); @@ -2680,6 +2682,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .regs = &tegra186_pmc_regs, .init = NULL, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, + .irq_set_wake = tegra186_pmc_irq_set_wake, + .irq_set_type = tegra186_pmc_irq_set_type, .reset_sources = tegra186_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), .reset_levels = tegra186_reset_levels, From patchwork Sun Jul 21 19:40:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134571 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="d4kvHjIU"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFV74BGKz9s8m for ; Mon, 22 Jul 2019 05:41:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727743AbfGUTlS (ORCPT ); Sun, 21 Jul 2019 15:41:18 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:9029 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727714AbfGUTlR (ORCPT ); Sun, 21 Jul 2019 15:41:17 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:14 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:16 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:41:16 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:16 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:15 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:16 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 16/21] soc/tegra: pmc: Add pmc wake support for tegra210 Date: Sun, 21 Jul 2019 12:40:55 -0700 Message-ID: <1563738060-30213-17-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738074; bh=uTBMUavar0IObaFwrQ7k0QY6BXOBGSIExQCwf2k7ktg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=d4kvHjIUT/Vo1bNMCkzS3txIQh7SI435DigUViI5SGEd1I1leA9P7eE1lulld3hWu N3rjzk4M2Z9lmqPV1xQ0QjVHg8w3TDL4+UTulm+JAc0ZiLTaUfV57MN8STxWsJBEff SgkKEmKV+pm+9EwOCE16QfBkq1/9YWs1koxur8p7T71yhPTRlAdWqK0CUX2zbedE7M QhpXI0nbJFPXDJBTAO6sspJjhiHDrO9Cr7GrEYpfUraJAbUr7vwuHcEKbRsfEFtOzL SFaCI7Pncc+3jj7fI8gZGXcYJ2+nouVIGxfYhaQSpqcmoqZlSP04j480vCE+AgRcb9 nccfebXm7dNVQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch implements PMC wakeup sequence for Tegra210 and defines common used RTC alarm wake event. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 91c84d0e66ae..c556f38874e1 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -57,6 +57,12 @@ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ #define PMC_CNTRL_MAIN_RST BIT(4) +#define PMC_CNTRL_LATCH_WAKEUPS BIT(5) + +#define PMC_WAKE_MASK 0x0c +#define PMC_WAKE_LEVEL 0x10 +#define PMC_WAKE_STATUS 0x14 +#define PMC_SW_WAKE_STATUS 0x18 #define DPD_SAMPLE 0x020 #define DPD_SAMPLE_ENABLE BIT(0) @@ -87,6 +93,11 @@ #define PMC_SCRATCH41 0x140 +#define PMC_WAKE2_MASK 0x160 +#define PMC_WAKE2_LEVEL 0x164 +#define PMC_WAKE2_STATUS 0x168 +#define PMC_SW_WAKE2_STATUS 0x16c + #define PMC_SENSOR_CTRL 0x1b0 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) @@ -1922,6 +1933,55 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; +static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + /* + * Latch wakeups to SW_WAKE_STATUS register to capture events + * that would not make it into wakeup event register during LP0 exit. + */ + value = tegra_pmc_readl(pmc, PMC_CNTRL); + value |= PMC_CNTRL_LATCH_WAKEUPS; + tegra_pmc_writel(pmc, value, PMC_CNTRL); + udelay(120); + + value &= ~PMC_CNTRL_LATCH_WAKEUPS; + tegra_pmc_writel(pmc, value, PMC_CNTRL); + udelay(120); + + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); + + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); + + /* enable PMC wake */ + if (data->hwirq >= 32) + offset = PMC_WAKE2_MASK; + else + offset = PMC_WAKE_MASK; + + value = tegra_pmc_readl(pmc, offset); + + if (on) + value |= 1 << bit; + else + value &= ~(1 << bit); + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -1954,6 +2014,49 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + if (data->hwirq >= 32) + offset = PMC_WAKE2_LEVEL; + else + offset = PMC_WAKE_LEVEL; + + value = tegra_pmc_readl(pmc, offset); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_LEVEL_HIGH: + value |= 1 << bit; + break; + + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_LEVEL_LOW: + value &= ~(1 << bit); + break; + + case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: + value ^= 1 << bit; + break; + + default: + return -EINVAL; + } + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -2540,6 +2643,10 @@ static const struct pinctrl_pin_desc tegra210_pin_descs[] = { TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) }; +static const struct tegra_wake_event tegra210_wake_events[] = { + TEGRA_WAKE_IRQ("rtc", 16, 2), +}; + static const struct tegra_pmc_soc tegra210_pmc_soc = { .num_powergates = ARRAY_SIZE(tegra210_powergates), .powergates = tegra210_powergates, @@ -2557,10 +2664,14 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .irq_set_wake = tegra210_pmc_irq_set_wake, + .irq_set_type = tegra210_pmc_irq_set_type, .reset_sources = tegra210_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, + .num_wake_events = ARRAY_SIZE(tegra210_wake_events), + .wake_events = tegra210_wake_events, }; #define TEGRA186_IO_PAD_TABLE(_pad) \ From patchwork Sun Jul 21 19:40:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134581 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="XKatg5BM"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFVn4vvYz9sML for ; Mon, 22 Jul 2019 05:41:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727753AbfGUTlU (ORCPT ); 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Sun, 21 Jul 2019 12:41:17 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 17/21] arm64: tegra: Enable wake from deep sleep on RTC alarm. Date: Sun, 21 Jul 2019 12:40:56 -0700 Message-ID: <1563738060-30213-18-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738076; bh=r/7sch8XJz5tT01ckyUKnesfNR9nppNjP97KIR+puRI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=XKatg5BMYhd1l1mZyFttY82ElDwsjSu57utLBxqhcl7Amk7dHKK/ekHbY/+pM0q4i ETQGWDXdMicqBpDQ/NnJVBMWDLLq2HdaZgdtpwhYl5a9ExqOjLnVRB6ePYp/cLxQzx n+s+QD0L1yec31PMTgSVX7ey6sRnXYuZzsRKRPiJCCZ3c+Au/pmtNhP2IgNei62kpF kgKydXIzjrzwYUb8rxLVUnnMMHuvq7wfo+8dwFUEIBLcSnPk4O6AjXQHavrS5iYv+/ 0bAuM0ExcZmxBgcWw2q9Nd1MBcoEZf8OKwDZy1hYVnSHXP3d1Q3syUakNXxI3W3RgZ kRBTNTak2SGTQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch updates device tree for RTC and PMC to allow system wake from deep sleep on RTC alarm. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 659753118e96..30a7c48385a2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -768,7 +768,8 @@ rtc@7000e000 { compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = ; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pmc>; clocks = <&tegra_car TEGRA210_CLK_RTC>; clock-names = "rtc"; }; @@ -778,6 +779,8 @@ reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #interrupt-cells = <2>; + interrupt-controller; powergates { pd_audio: aud { From patchwork Sun Jul 21 19:40:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134573 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="cq3Jy4Tg"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFVC52Lrz9s3l for ; Mon, 22 Jul 2019 05:41:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727777AbfGUTlW (ORCPT ); Sun, 21 Jul 2019 15:41:22 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15871 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727747AbfGUTlV (ORCPT ); Sun, 21 Jul 2019 15:41:21 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:27 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:19 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:41:19 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:19 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:19 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:19 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 18/21] soc/tegra: pmc: Configure core power request polarity Date: Sun, 21 Jul 2019 12:40:57 -0700 Message-ID: <1563738060-30213-19-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738087; bh=vgWkSV598c3dO93KPU1w6w/1sZicmNlPI5d9nXeZu1I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=cq3Jy4TgoHuRTQ5sooawz3Lsk63blyBRUIycGuHFcRae8SdRFUF4Bacr1McSp6eaR W/jHjECVHPZzpWxRElejV9SoqHlDZfTce+kZwxz2uZVHJMkoT1bUAvAfZztOqcd5Zb aMOEpVtDMjOi8sNtGYiTOb8ZjeVfPP7yULdKj0uBQWma2nczY3/oukEoojxGbcSS+k g5wLBiYeGYPmCEPR+L5hlXTFdhjInORw230fff1vuuO/5C4LfRJHCQK2K4L9plc/8t Fsjf8uftIxgrAVmdyXUjKr2nPGvyCfYx+p0fDAqkn5jXxASbzUrOzTsuUHw0rQaWgL 32lW9FSsB9VCg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch configures polarity of the core power request signal in PMC control register based on the device tree property. PMC asserts and de-asserts power request signal based on it polarity when it need to power-up and power-down the core rail during SC7. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index c556f38874e1..7521394b94ab 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -56,6 +56,7 @@ #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ +#define PMC_CNTRL_PWRREQ_POLARITY BIT(8) #define PMC_CNTRL_MAIN_RST BIT(4) #define PMC_CNTRL_LATCH_WAKEUPS BIT(5) @@ -2303,6 +2304,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) else value |= PMC_CNTRL_SYSCLK_POLARITY; + if (pmc->corereq_high) + value &= ~PMC_CNTRL_PWRREQ_POLARITY; + else + value |= PMC_CNTRL_PWRREQ_POLARITY; + /* configure the output polarity while the request is tristated */ tegra_pmc_writel(pmc, value, PMC_CNTRL); From patchwork Sun Jul 21 19:40:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134574 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="aehCUWhP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFVF0rtwz9s3l for ; Mon, 22 Jul 2019 05:41:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727794AbfGUTlY (ORCPT ); Sun, 21 Jul 2019 15:41:24 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15879 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727779AbfGUTlX (ORCPT ); Sun, 21 Jul 2019 15:41:23 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:29 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:22 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:41:22 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:21 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:21 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:21 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:21 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 19/21] soc/tegra: pmc: Configure deep sleep control settings Date: Sun, 21 Jul 2019 12:40:58 -0700 Message-ID: <1563738060-30213-20-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738089; bh=Jfk6xJnCfov0z3hLLm+3iLOW+N0kk3KDGipzWIXZYNQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=aehCUWhPKxIv6/mfsdgcRFAgK00Zmz00J5lYwPTdxg+aWiarZWK7KxhmySntxEWVR 5/DTJkiF2PNOrTNqhwJwdPCmlduicZsuvd3gNXKdXlHIko9ZNVje99kjtuYM2GLhJr fKPskXU+axzkIm2PPoCfRzprEzwFcFCikZ5DZKjd4Zc3xcBq1b4ZS8F7LkZ2QgNgcm RXMHgXZLj3XB96IDzYG2aKG9IsyZa5NwAlE5WAvPKoBFt/qNG3aua0TsFg+o3iekGj Oy5TkZ5wbkq1A26ZH9Wd8dQznUhsr8j5HAVe87ShgMTGQB2J8XDljE+ibjNIlSZS8t Qj0E3CUaH1JjA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra210 and prior Tegra chips have deep sleep entry and wakeup related timings which are platform specific that should be configured before entering into deep sleep. Below are the timing specific configurations for deep sleep entry and wakeup. - Core rail power-on stabilization timer - OSC clock stabilization timer after SOC rail power is stabilized. - Core power off time is the minimum wake delay to keep the system in deep sleep state irrespective of any quick wake event. These values depends on the discharge time of regulators and turn OFF time of the PMIC to allow the complete system to finish entering into deep sleep state. These values vary based on the platform design and are specified through the device tree. This patch has implementation to configure these timings which are must to have for proper deep sleep and wakeup operations. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 7521394b94ab..16df35bdbd4b 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -89,6 +89,8 @@ #define PMC_CPUPWRGOOD_TIMER 0xc8 #define PMC_CPUPWROFF_TIMER 0xcc +#define PMC_COREPWRGOOD_TIMER 0x3c +#define PMC_COREPWROFF_TIMER 0xe0 #define PMC_PWR_DET_VALUE 0xe4 @@ -2290,7 +2292,7 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = { static void tegra20_pmc_init(struct tegra_pmc *pmc) { - u32 value; + u32 value, osc, pmu, off; /* Always enable CPU power request */ value = tegra_pmc_readl(pmc, PMC_CNTRL); @@ -2316,6 +2318,15 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) value = tegra_pmc_readl(pmc, PMC_CNTRL); value |= PMC_CNTRL_SYSCLK_OE; tegra_pmc_writel(pmc, value, PMC_CNTRL); + + osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); + pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); + off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); + if (osc && pmu) + tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), + PMC_COREPWRGOOD_TIMER); + if (off) + tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); } static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, From patchwork Sun Jul 21 19:40:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134575 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="JCWQcj6t"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFVH4PP0z9s3l for ; Mon, 22 Jul 2019 05:41:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727816AbfGUTl0 (ORCPT ); Sun, 21 Jul 2019 15:41:26 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:9048 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727789AbfGUTlY (ORCPT ); Sun, 21 Jul 2019 15:41:24 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:21 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:23 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 21 Jul 2019 12:41:23 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:23 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:23 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:23 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:22 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 20/21] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Date: Sun, 21 Jul 2019 12:40:59 -0700 Message-ID: <1563738060-30213-21-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738081; bh=3ikE8x0cNN1fPtdTTddMKObVTKhfyEJPwIrj8ksa4Wg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=JCWQcj6t2Al1/3wfAwKVDbachJHpK8DPkhBoyZlXgY2I35vfiN9lmt4lfZPgfcQP7 XAR7JbXylLqK1xfxCLTqO3k18353DhVgC2DNsFDkZOFDClW+pNTymuuQjIW+5DXz2E VJ83lkqyVsWj1+WG3hfZevlq39ok2PnPvvudfCNzpaqtGUtZBfnClA58M5fW/GKsvl s00ubtMiEeZNd3xwgDUM4WDFKquvrCtX4nudMATqELVOzsd/NptDgIpPlRDofeRyrc QAAy2Uk2T0dn5rZHWFsih4o4NgJPGGnbGrTYNYaJype7ji4xYaYRRG7a0RWV+UEpDK Ld62lQHG0xHQQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch has Jetson TX1 platform specific SC7 timing configuration in device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 27723829d033..cb58f79deb48 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -279,6 +279,13 @@ pmc@7000e400 { nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; /* eMMC */ From patchwork Sun Jul 21 19:41:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1134577 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="favAcW5N"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45sFVj5JcPz9sMr for ; Mon, 22 Jul 2019 05:41:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727822AbfGUTl1 (ORCPT ); Sun, 21 Jul 2019 15:41:27 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15890 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727807AbfGUTl0 (ORCPT ); Sun, 21 Jul 2019 15:41:26 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jul 2019 12:41:32 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jul 2019 12:41:25 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jul 2019 12:41:25 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:25 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jul 2019 19:41:24 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jul 2019 19:41:25 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.85]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jul 2019 12:41:24 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V6 21/21] arm64: dts: tegra210-p3450: Jetson nano SC7 timings Date: Sun, 21 Jul 2019 12:41:00 -0700 Message-ID: <1563738060-30213-22-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> References: <1563738060-30213-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1563738092; bh=8JdWFRl5TXtdoBU9Fit60MOTWGsIX8C4g1afQYDDwlw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=favAcW5Ny6pjIr3iC10CwvLH0j4JJ01RTUxefJDjW1eotF2r50QozBaPXj4K+o/8w n7mxiFh35Hm8ZLXwZW7Q65D89qpXUBtmnIAJf+6IYH6AOwkMA3wvf4XQvBa2Nrn8lK /ToQJv8yLGaLl5JbpYd5Jj9BYgQwg9aP9tE394LmH68hVECvd5CB9NyvJ5gAaxmLXO vkr3A54XJIBR+5kB6vOxYDDyIM6PFnl4G/XiEMIWCmSyZB8Gyu1EfT7CxPTaz07fhf VUO3Y5D9g18AuZrRw6vSC5jIRfKJZUV1i17mbYlKuvT7bgM852vIN7eAQTPuTPLKDV Th1TJsVIctVzQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch adds Jetson nano platform specific SC7 timing configuration in the device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9d17ec707bce..b525e69c172a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -382,6 +382,13 @@ pmc@7000e400 { nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; hda@70030000 {