From patchwork Fri Jul 19 11:25:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1134018 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-505333-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="b8UPTX/l"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45qpbY32lPz9s00 for ; Fri, 19 Jul 2019 21:25:59 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=LY/uMhjpXGO77CW6EhrZaKpP5HdFUjmnrw0DAMkP12yeR2UikRbAU oXguvlQ/Xe/Z2InKRuTEFyP1eEP2rw2dyTnuVsQtgtqDkSFDwzp7AF54z3mxIzcU R/bW3fLt+w7uwvRJjYcORXhmM8fz4dunzGJNcN1nnAiVrosMaYbDlY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=ptk1ujfIxWRS5WdTeHlvNEiARjw=; b=b8UPTX/lZFUbHKqTYQ8u /Oyzhab0YLLgSrpp3GGju7YCwZ702OcgKfaiCUxnxDSCFvhpzGAh6SuFvlLBW1d8 3cYmfsQZZlzREnj6zYbf5URcIOs02xRgJ48u3CIx3iq2dwYkepEeVexhblqvlAVb NbqI+X1r08A9dTpl7xYBAkg= Received: (qmail 81217 invoked by alias); 19 Jul 2019 11:25:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 81208 invoked by uid 89); 19 Jul 2019 11:25:50 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.1 spammy=enabling, SVE X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 19 Jul 2019 11:25:48 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2FE2C337 for ; Fri, 19 Jul 2019 04:25:47 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CA3CA3F71A for ; Fri, 19 Jul 2019 04:25:46 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Rename +bitperm to +sve2-bitperm Date: Fri, 19 Jul 2019 12:25:45 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes After some discussion, we've decided to rename the +bitperm feature flag to +sve2-bitperm, so that it's consistent with the other SVE2 feature flags. The associated macro was already __ARM_FEATURE_SVE2_BITPERM, so only the feature flag itself needs to change. Tested on aarch64-linux-gnu and applied as r273600. Richard 2019-07-19 Richard Sandiford gcc/ * doc/invoke.texi: Rename the AArch64 +bitperm extension flag to +sve-bitperm. * config/aarch64/aarch64-option-extensions.def: Likewise. ------------------------------------------------------------------------------ Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi 2019-07-16 09:11:05.077427347 +0100 +++ gcc/doc/invoke.texi 2019-07-19 12:22:30.128041121 +0100 @@ -16083,7 +16083,7 @@ not affect code generation. This option @item sve2 Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE instructions. -@item bitperm +@item sve2-bitperm Enable SVE2 bitperm instructions. This also enables SVE2 instructions. @item sve2-sm4 Enable SVE2 sm4 instructions. This also enables SVE2 instructions. Index: gcc/config/aarch64/aarch64-option-extensions.def =================================================================== --- gcc/config/aarch64/aarch64-option-extensions.def 2019-05-29 10:49:36.240711500 +0100 +++ gcc/config/aarch64/aarch64-option-extensions.def 2019-07-19 12:22:30.124041152 +0100 @@ -58,13 +58,13 @@ /* Enabling "fp" just enables "fp". Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2", "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and - "bitperm". */ + "sve2-bitperm". */ AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "fp") /* Enabling "simd" also enables "fp". Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3", - "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and "bitperm". - */ + "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and + "sve2-bitperm". */ AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "asimd") /* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2". @@ -80,7 +80,7 @@ AARCH64_OPT_EXTENSION("lse", AARCH64_FL_ /* Enabling "fp16" also enables "fp". Disabling "fp16" disables "fp16", "fp16fml", "sve", "sve2", "sve2-aes", - "sve2-sha3", "sve2-sm4", and "bitperm". */ + "sve2-sha3", "sve2-sm4", and "sve2-bitperm". */ AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "fphp asimdhp") /* Enabling or disabling "rcpc" only changes "rcpc". */ @@ -116,7 +116,7 @@ AARCH64_OPT_EXTENSION("fp16fml", AARCH64 /* Enabling "sve" also enables "fp16", "fp" and "simd". Disabling "sve" disables "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4" - and "bitperm". */ + and "sve2-bitperm". */ AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "sve") /* Enabling/Disabling "profile" does not enable/disable any other feature. */ @@ -139,7 +139,7 @@ AARCH64_OPT_EXTENSION("predres", AARCH64 /* Enabling "sve2" also enables "sve", "fp16", "fp", and "simd". Disabling "sve2" disables "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and - "bitperm". */ + "sve2-bitperm". */ AARCH64_OPT_EXTENSION("sve2", AARCH64_FL_SVE2, AARCH64_FL_SVE | AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "") /* Enabling "sve2-sm4" also enables "sm4", "simd", "fp16", "fp", "sve", and @@ -154,8 +154,8 @@ AARCH64_OPT_EXTENSION("sve2-aes", AARCH6 "sve2". Disabling "sve2-sha3" just disables "sve2-sha3". */ AARCH64_OPT_EXTENSION("sve2-sha3", AARCH64_FL_SVE2_SHA3, AARCH64_FL_SHA3 | AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "") -/* Enabling "bitperm" also enables "simd", "fp16", "fp", "sve", and "sve2". - Disabling "bitperm" just disables "bitperm". */ -AARCH64_OPT_EXTENSION("bitperm", AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "") +/* Enabling "sve2-bitperm" also enables "simd", "fp16", "fp", "sve", and + "sve2". Disabling "sve2-bitperm" just disables "sve2-bitperm". */ +AARCH64_OPT_EXTENSION("sve2-bitperm", AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "") #undef AARCH64_OPT_EXTENSION