From patchwork Thu Jul 18 20:06:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1133837 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-505302-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45qQCK0Xzfz9s3Z for ; Fri, 19 Jul 2019 06:07:00 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=YnSLDKOdUb3yTYu/p98VgieozvA5TedDqrdDqu1WV5sfvI Q6iy2wkC90USdlOLjm27SaP/u3SQRIFcSFfCc/hDtbf8ns3fOl/N/sPjdXOWuv9V t5P25OCopaSpPyiiYtvqB7CCGeCp1m7mD46Z7HMgCpfEP8KjxtzzmZQZCaPwQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=XvCESIkTfYuDOloHPHGwM2GzRxg=; b=jWf3hDjmHtXOQQin5ChV KLRj1NCSgucWAVPvcxZhVUkKcK2KYD14bubeZKyjLcEPK6Qs2R79nhUw5q6jV5aG cb9F2ltPoqaBAM6FrVgApr7waiG4RUXy2jrA/hWTK51KJPNxwheXf6cRE6Etdqnf XdOV3UhmimwYGKAVQZK/on4= Received: (qmail 82717 invoked by alias); 18 Jul 2019 20:06:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 82709 invoked by uid 89); 18 Jul 2019 20:06:53 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-7.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=qq, QQ X-HELO: mail-io1-f48.google.com Received: from mail-io1-f48.google.com (HELO mail-io1-f48.google.com) (209.85.166.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 18 Jul 2019 20:06:52 +0000 Received: by mail-io1-f48.google.com with SMTP id o9so53676234iom.3 for ; Thu, 18 Jul 2019 13:06:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=Q2du9Od41bCN/BrGRkfZzTWkZTxr1WtX6A1d4+mMOas=; b=IniQxP3ieH1/vZBbMTyH2Gr904XC5snUmt42tXumBNj6n2lp2eyKvZvpj4GNP8ZYDQ UIBsXRI32wPLF8TLmNQ+wrL5wTbSEWaFrXr5SzqLSh0PZwCeDnCb+V49LX53Lm2+fIEq x+mcWdsRSj8EOFlvXlqqPu7mmW956ur03WkNI9+nXNTvN6HMk0w5HdwmPLtzmpi4/55a Z3KJ3QrBiuo1TsQwgAxIklNjj6vmo63vzpfS4OzXcALHwi38lM9rk+5ZFOmuw194QkLv dx8CjMFn/nohM2EybHwvTkafgBP55LeKgQGN1jqtek4ucJbQ1Ne+o8jUOu1bhEvUFsjQ YZLg== MIME-Version: 1.0 From: Uros Bizjak Date: Thu, 18 Jul 2019 22:06:38 +0200 Message-ID: Subject: [PATCH, i386]: Remove *qi_2_slp insn patterns To: "gcc-patches@gcc.gnu.org" These insn patterns are just too complex to ever match. Remove them. 2019-07-18 Uroš Bizjak * config/i386/i386.md (*addqi_2_slp): Remove. (*qi_2_slp): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. For the reference, the correct form would be: --cut here-- (define_insn "*and_2_slp" [(set (reg FLAGS_REG) (compare (and:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0") (match_operand:SWI12 2 "general_operand" "mn")) (const_int 0))) (set (strict_low_part (match_operand:SWI12 0 "register_operand" "+")) (and:SWI12 (match_dup 1) (match_dup 2)))] "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && ix86_match_ccmode (insn, CCNOmode) /* FIXME: without this LRA can't reload this pattern, see PR82524. */ && (rtx_equal_p (operands[0], operands[1]) || rtx_equal_p (operands[0], operands[2]))" "and{}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "")]) (define_insn "*_2_slp" [(set (reg FLAGS_REG) (compare (any_or:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0") (match_operand:SWI12 2 "general_operand" "mn")) (const_int 0))) (set (strict_low_part (match_operand:SWI12 0 "register_operand" "+")) (any_or:SWI12 (match_dup 1) (match_dup 2)))] "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && ix86_match_ccmode (insn, CCNOmode) /* FIXME: without this LRA can't reload this pattern, see PR82524. */ && (rtx_equal_p (operands[0], operands[1]) || rtx_equal_p (operands[0], operands[2]))" "{}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "")]) --cut here-- Uros. Index: i386.md =================================================================== --- i386.md (revision 273578) +++ i386.md (working copy) @@ -8723,20 +8723,6 @@ [(set_attr "type" "alu") (set_attr "mode" "")]) -(define_insn "*andqi_2_slp" - [(set (reg FLAGS_REG) - (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "+qm,q") - (match_operand:QI 1 "nonimmediate_operand" "qn,m")) - (const_int 0))) - (set (strict_low_part (match_dup 0)) - (and:QI (match_dup 0) (match_dup 1)))] - "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCNOmode) - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "and{b}\t{%1, %0|%0, %1}" - [(set_attr "type" "alu1") - (set_attr "mode" "QI")]) - (define_insn "andqi_ext_1" [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q,Q") (const_int 8) @@ -9155,20 +9141,6 @@ [(set_attr "type" "alu") (set_attr "mode" "SI")]) -(define_insn "*qi_2_slp" - [(set (reg FLAGS_REG) - (compare (any_or:QI (match_operand:QI 0 "nonimmediate_operand" "+qm,q") - (match_operand:QI 1 "general_operand" "qn,m")) - (const_int 0))) - (set (strict_low_part (match_dup 0)) - (any_or:QI (match_dup 0) (match_dup 1)))] - "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) - && ix86_match_ccmode (insn, CCNOmode) - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "{q}\t{%1, %0|%0, %1}" - [(set_attr "type" "alu1") - (set_attr "mode" "QI")]) - (define_insn "*_3" [(set (reg FLAGS_REG) (compare (any_or:SWI