From patchwork Thu Jul 18 15:13:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Baluta X-Patchwork-Id: 1133761 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45qHj83ftkz9sND for ; Fri, 19 Jul 2019 01:14:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390802AbfGRPNx (ORCPT ); Thu, 18 Jul 2019 11:13:53 -0400 Received: from inva020.nxp.com ([92.121.34.13]:44720 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727921AbfGRPNw (ORCPT ); Thu, 18 Jul 2019 11:13:52 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 67AC21A02BB; Thu, 18 Jul 2019 17:13:50 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 5AA0D1A0127; Thu, 18 Jul 2019 17:13:50 +0200 (CEST) Received: from fsr-ub1864-103.ea.freescale.net (fsr-ub1864-103.ea.freescale.net [10.171.82.17]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 63D46205C7; Thu, 18 Jul 2019 17:13:49 +0200 (CEST) From: Daniel Baluta To: shawnguo@kernel.org Cc: robh+dt@kernel.org, mark.rutland@arm.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, daniel.baluta@nxp.com, shengjiu.wang@nxp.com, paul.olaru@nxp.com, aisheng.dong@nxp.com, leonard.crestez@nxp.com, anson.huang@nxp.com, peng.fan@nxp.com, Frank.Li@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sound-open-firmware@alsa-project.org Subject: [PATCH 1/3] clk: imx8: Add DSP related clocks Date: Thu, 18 Jul 2019 18:13:44 +0300 Message-Id: <20190718151346.3523-2-daniel.baluta@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190718151346.3523-1-daniel.baluta@nxp.com> References: <20190718151346.3523-1-daniel.baluta@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org i.MX8QXP contains Hifi4 DSP. There are four clocks associated with DSP: * dsp_lpcg_core_clk * dsp_lpcg_ipg_clk * dsp_lpcg_adb_aclk * ocram_lpcg_ipg_clk Signed-off-by: Daniel Baluta Reviewed-by: Dong Aisheng --- drivers/clk/imx/clk-imx8qxp-lpcg.c | 5 +++++ include/dt-bindings/clock/imx8-clock.h | 6 +++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index fb6edf1b8aa2..c0aff7ca6374 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -72,6 +72,11 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = { { IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, }, { IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, }, { IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, }, + + { IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, }, + { IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, }, + { IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, }, }; static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = { diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index 4236818e3be5..673a8c662340 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -283,7 +283,11 @@ #define IMX_ADMA_LPCG_PWM_IPG_CLK 38 #define IMX_ADMA_LPCG_LCD_PIX_CLK 39 #define IMX_ADMA_LPCG_LCD_APB_CLK 40 +#define IMX_ADMA_LPCG_DSP_ADB_CLK 41 +#define IMX_ADMA_LPCG_DSP_IPG_CLK 42 +#define IMX_ADMA_LPCG_DSP_CORE_CLK 43 +#define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44 -#define IMX_ADMA_LPCG_CLK_END 41 +#define IMX_ADMA_LPCG_CLK_END 45 #endif /* __DT_BINDINGS_CLOCK_IMX_H */ From patchwork Thu Jul 18 15:13:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Baluta X-Patchwork-Id: 1133760 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45qHj62SHrz9sND for ; Fri, 19 Jul 2019 01:14:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390872AbfGRPN6 (ORCPT ); Thu, 18 Jul 2019 11:13:58 -0400 Received: from inva020.nxp.com ([92.121.34.13]:44792 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727781AbfGRPNy (ORCPT ); Thu, 18 Jul 2019 11:13:54 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 5D1A11A035C; Thu, 18 Jul 2019 17:13:52 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 508B41A011E; Thu, 18 Jul 2019 17:13:52 +0200 (CEST) Received: from fsr-ub1864-103.ea.freescale.net (fsr-ub1864-103.ea.freescale.net [10.171.82.17]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 769DB205C7; Thu, 18 Jul 2019 17:13:51 +0200 (CEST) From: Daniel Baluta To: shawnguo@kernel.org Cc: robh+dt@kernel.org, mark.rutland@arm.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, daniel.baluta@nxp.com, shengjiu.wang@nxp.com, paul.olaru@nxp.com, aisheng.dong@nxp.com, leonard.crestez@nxp.com, anson.huang@nxp.com, peng.fan@nxp.com, Frank.Li@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sound-open-firmware@alsa-project.org Subject: [PATCH 3/3] dt-bindings: dsp: fsl: Add DSP core binding support Date: Thu, 18 Jul 2019 18:13:46 +0300 Message-Id: <20190718151346.3523-4-daniel.baluta@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190718151346.3523-1-daniel.baluta@nxp.com> References: <20190718151346.3523-1-daniel.baluta@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This describes the DSP device tree node. Signed-off-by: Daniel Baluta --- .../devicetree/bindings/dsp/fsl,dsp.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp.yaml diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml new file mode 100644 index 000000000000..d112486eda0e --- /dev/null +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,dsp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8 DSP core + +maintainers: + - Daniel Baluta + +description: | + Some boards from i.MX8 family contain a DSP core used for + advanced pre- and post- audio processing. + +properties: + compatible: + enum: + - fsl,imx8qxp-dsp + + reg: + description: Should contain register location and length + + clocks: + items: + - description: ipg clock + - description: ocram clock + - description: core clock + + clock-names: + items: + - const: ipg + - const: ocram + - const: core + + power-domains: + description: + List of phandle and PM domain specifier as documented in + Documentation/devicetree/bindings/power/power_domain.txt + + mboxes: + description: + List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB + (see mailbox/fsl,mu.txt) + maxItems: 4 + + mbox-names: + items: + - const: txdb0 + - const: txdb1 + - const: rxdb0 + - const: rxdb1 + + memory-region: + description: + phandle to a node describing reserved memory (System RAM memory) + used by DSP (see bindings/reserved-memory/reserved-memory.txt) + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - mboxes + - mbox-names + - memory-region + +examples: + - | + #include + #include + dsp@596e8000 { + compatbile = "fsl,imx8qxp-dsp"; + reg = <0x596e8000 0x88000>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, + <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, + <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; + clock-names = "ipg", "ocram", "core"; + power-domains = <&pd IMX_SC_R_MU_13A>, + <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>; + };