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Wed, 17 Jul 2019 08:48:07 +0000 From: To: , Subject: [PATCH 1/5] mtd: spi-nor: fix description for int (*flash_is_locked)() Thread-Topic: [PATCH 1/5] mtd: spi-nor: fix description for int (*flash_is_locked)() Thread-Index: AQHVPHxaKG+eJEFhOUur/Urn3TTMig== Date: Wed, 17 Jul 2019 08:48:06 +0000 Message-ID: <20190717084745.19322-2-tudor.ambarus@microchip.com> References: <20190717084745.19322-1-tudor.ambarus@microchip.com> In-Reply-To: <20190717084745.19322-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P195CA0085.EURP195.PROD.OUTLOOK.COM (2603:10a6:802:59::38) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4f688b50-a3b9-449a-2c6e-08d70a937cc8 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); 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Signed-off-by: Tudor Ambarus Reviewed-by: Vignesh Raghavendra --- include/linux/mtd/spi-nor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 9f57cdfcc93d..c4c2c5971284 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -372,10 +372,10 @@ struct flash_info; * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is + * completely locked * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode * @clear_sr_bp: [FLASH-SPECIFIC] clears the Block Protection Bits from * the SPI NOR Status Register. - * completely locked * @priv: the private data */ struct spi_nor { From patchwork Wed Jul 17 08:48:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 1133200 X-Patchwork-Delegate: tudor.ambarus@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 17 Jul 2019 08:48:09 +0000 From: To: , Subject: [PATCH 2/5] mtd: spi-nor: group the code about the write protection at power-up Thread-Topic: [PATCH 2/5] mtd: spi-nor: group the code about the write protection at power-up Thread-Index: AQHVPHxbXzKnWnPqC02RF1i1z4jGIA== Date: Wed, 17 Jul 2019 08:48:09 +0000 Message-ID: <20190717084745.19322-3-tudor.ambarus@microchip.com> References: <20190717084745.19322-1-tudor.ambarus@microchip.com> In-Reply-To: <20190717084745.19322-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P195CA0085.EURP195.PROD.OUTLOOK.COM (2603:10a6:802:59::38) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 725769e7-69a2-4086-391b-08d70a937e36 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); 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Group the code in spi_nor_init() as the pointer to spansion_quad_enable() can be retrieved from nor->quad_enable. While touching this code, rename nor->clear_sr_bp() to nor->disable_write_protection() to better indicate its scope: it disables the default write protection after a power-on reset cycle. No functional change intended. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 39 ++++++++++++++++++++++++--------------- include/linux/mtd/spi-nor.h | 6 +++--- 2 files changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 03cc788511d5..e9e441f91b68 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -3780,8 +3780,6 @@ static int spi_nor_init_params(struct spi_nor *nor, default: /* Kept only for backward compatibility purpose. */ params->quad_enable = spansion_quad_enable; - if (nor->clear_sr_bp) - nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp; break; } @@ -4034,11 +4032,32 @@ static int spi_nor_init(struct spi_nor *nor) { int err; - if (nor->clear_sr_bp) { - err = nor->clear_sr_bp(nor); + /* + * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up + * with the software protection bits set. + */ + if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || + JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || + JEDEC_MFR(nor->info) == SNOR_MFR_SST || + nor->info->flags & SPI_NOR_HAS_LOCK) { + nor->disable_write_protection = spi_nor_clear_sr_bp; + + /* + * In case of spansion flashes, when the configuration register + * Quad Enable bit is one, only the the Write Status (01h) + * command with two data bytes may be used to clear the block + * protection bits. + */ + if (nor->quad_enable == spansion_quad_enable) + nor->disable_write_protection = + spi_nor_spansion_clear_sr_bp; + } + + if (nor->disable_write_protection) { + err = nor->disable_write_protection(nor); if (err) { dev_err(nor->dev, - "fail to clear block protection bits\n"); + "failed to unlock the flash at init\n"); return err; } } @@ -4165,16 +4184,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, if (info->flags & SPI_S3AN) nor->flags |= SNOR_F_READY_XSR_RDY; - /* - * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up - * with the software protection bits set. - */ - if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || - JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || - JEDEC_MFR(nor->info) == SNOR_MFR_SST || - nor->info->flags & SPI_NOR_HAS_LOCK) - nor->clear_sr_bp = spi_nor_clear_sr_bp; - /* Parse the Serial Flash Discoverable Parameters table. */ ret = spi_nor_init_params(nor, ¶ms); if (ret) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index c4c2c5971284..6c3273760700 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -374,8 +374,8 @@ struct flash_info; * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is * completely locked * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode - * @clear_sr_bp: [FLASH-SPECIFIC] clears the Block Protection Bits from - * the SPI NOR Status Register. + * @disable_write_protection: [FLASH-SPECIFIC] disable write protection during + * power-up * @priv: the private data */ struct spi_nor { @@ -412,7 +412,7 @@ struct spi_nor { int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); int (*quad_enable)(struct spi_nor *nor); - int (*clear_sr_bp)(struct spi_nor *nor); + int (*disable_write_protection)(struct spi_nor *nor); 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Wed, 17 Jul 2019 08:48:11 +0000 From: To: , Subject: [PATCH 3/5] mtd: spi-nor: add Global Block Unlock support Thread-Topic: [PATCH 3/5] mtd: spi-nor: add Global Block Unlock support Thread-Index: AQHVPHxdqQl/GMdi9ECDdSKG+lyMoQ== Date: Wed, 17 Jul 2019 08:48:11 +0000 Message-ID: <20190717084745.19322-4-tudor.ambarus@microchip.com> References: <20190717084745.19322-1-tudor.ambarus@microchip.com> In-Reply-To: <20190717084745.19322-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P195CA0085.EURP195.PROD.OUTLOOK.COM (2603:10a6:802:59::38) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 31001b2b-fce1-46e0-3107-08d70a937f8a x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); 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A Global Block-Protection Unlock command offers a single command cycle that unlocks the entire memory array. This is identical with what other nor flashes are doing by clearing the block protection bits from the status register: disable the write protection after a power-on reset cycle. We can't determine this purely by manufacturer type and it's not autodetectable by anything like SFDP, so make a new flag for it: UNLOCK_GLOBAL_BLOCK. Note that the Global Block Unlock command has different names depending on the manufacturer, but always the same command value: 0x98. Macronix's MX25U12835F names it Gang Block Unlock, Winbound's W25Q128FV names it Global Block Unlock and Microchip's SST26VF064B names it Global Block Protection Unlock. Signed-off-by: Tudor Ambarus Reviewed-by: Vignesh Raghavendra --- drivers/mtd/spi-nor/spi-nor.c | 21 ++++++++++++++++++++- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index e9e441f91b68..767e2e6eb1b8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -250,7 +250,7 @@ struct flash_info { u16 page_size; u16 addr_width; - u16 flags; + u32 flags; #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ #define SST_WRITE BIT(2) /* use SST byte programming */ @@ -279,6 +279,7 @@ struct flash_info { #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ #define USE_CLSR BIT(14) /* use CLSR command */ #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ +#define UNLOCK_GLOBAL_BLOCK BIT(16) /* Unlock global block protection */ /* Part specific fixup hooks. */ const struct spi_nor_fixups *fixups; @@ -1725,6 +1726,20 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor) return spi_nor_clear_sr_bp(nor); } +static int spi_nor_unlock_global_block_protection(struct spi_nor *nor) +{ + int ret; + + write_enable(nor); + + ret = nor->write_reg(nor, SPINOR_OP_ULBPR, NULL, 0); + if (ret < 0) { + dev_err(nor->dev, "error %d on ULBPR\n", ret); + return ret; + } + return spi_nor_wait_till_ready(nor); +} + /* Used when the "_ext_id" is two bytes at most */ #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ .id = { \ @@ -4053,6 +4068,10 @@ static int spi_nor_init(struct spi_nor *nor) spi_nor_spansion_clear_sr_bp; } + if (nor->info->flags & UNLOCK_GLOBAL_BLOCK) + nor->disable_write_protection = + spi_nor_unlock_global_block_protection; + if (nor->disable_write_protection) { err = nor->disable_write_protection(nor); if (err) { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 6c3273760700..84d279fd287e 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -65,6 +65,7 @@ #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ +#define SPINOR_OP_ULBPR 0x98 /* Global Block Unlock Protection */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ From patchwork Wed Jul 17 08:48:13 2019 Content-Type: text/plain; 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Wed, 17 Jul 2019 08:48:14 +0000 From: To: , Subject: [PATCH 4/5] mtd: spi-nor: unlock global block protection on sst26vf064b Thread-Topic: [PATCH 4/5] mtd: spi-nor: unlock global block protection on sst26vf064b Thread-Index: AQHVPHxeihfxjuggyEqOfqXDefj3kw== Date: Wed, 17 Jul 2019 08:48:13 +0000 Message-ID: <20190717084745.19322-5-tudor.ambarus@microchip.com> References: <20190717084745.19322-1-tudor.ambarus@microchip.com> In-Reply-To: <20190717084745.19322-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P195CA0085.EURP195.PROD.OUTLOOK.COM (2603:10a6:802:59::38) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1d20c345-0228-41c6-69ca-08d70a9380e4 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); 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X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.154.123 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tudor.Ambarus@microchip.com, richard@nod.at, linux-kernel@vger.kernel.org, Nicolas.Ferre@microchip.com, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, computersforpeace@gmail.com, dwmw2@infradead.org Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Tudor Ambarus To avoid inadvertent writes during power-up, sst26vf064b is write-protected by default after a power-on reset cycle. Unlock the serial flash memory by using the Global Block Protection Unlock command - it offers a single command cycle that unlocks the entire memory array. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 767e2e6eb1b8..ffb53740031c 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -2075,7 +2075,9 @@ static const struct flash_info spi_nor_ids[] = { { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, - { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + UNLOCK_GLOBAL_BLOCK) }, /* ST Microelectronics -- newer production may have feature updates */ { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, From patchwork Wed Jul 17 08:48:16 2019 Content-Type: text/plain; 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Wed, 17 Jul 2019 08:48:16 +0000 From: To: , Subject: [PATCH 5/5] mtd: spi-nor: add Kconfig option to disable write protection at power-up Thread-Topic: [PATCH 5/5] mtd: spi-nor: add Kconfig option to disable write protection at power-up Thread-Index: AQHVPHxf57xp/vrlsEWVvsFB8NifHg== Date: Wed, 17 Jul 2019 08:48:16 +0000 Message-ID: <20190717084745.19322-6-tudor.ambarus@microchip.com> References: <20190717084745.19322-1-tudor.ambarus@microchip.com> In-Reply-To: <20190717084745.19322-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P195CA0085.EURP195.PROD.OUTLOOK.COM (2603:10a6:802:59::38) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3ba4e511-15fb-4a3a-7210-08d70a938254 x-microsoft-antispam: BCL:0; PCL:0; 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X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.149.84 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tudor.Ambarus@microchip.com, richard@nod.at, linux-kernel@vger.kernel.org, Nicolas.Ferre@microchip.com, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, computersforpeace@gmail.com, dwmw2@infradead.org Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Tudor Ambarus Some spi-nor flashes come write protected by default after a power-on sequence to avoid destructing commands (erase, write) during power-up. Backward compatibility imposes to disable the write protection at power-up by default. Add a Kconfig option to let the user benefit of the power-up write protection. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/Kconfig | 8 ++++++++ drivers/mtd/spi-nor/spi-nor.c | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index 6de83277ce8b..b550e10657f1 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -22,6 +22,14 @@ config MTD_SPI_NOR_USE_4K_SECTORS Please note that some tools/drivers/filesystems may not work with 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum). +config MTD_SPI_NOR_DISABLE_POWER_UP_WRITE_PROTECTION + bool "Disable write protection during power-up" + default y + help + Some spi-nor flashes are write protected by default after a power-on + reset cycle, in order to avoid inadvertend writes during power-up. + Disable the write protection during power-up. + config SPI_ASPEED_SMC tristate "Aspeed flash controllers in SPI mode" depends on ARCH_ASPEED || COMPILE_TEST diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index ffb53740031c..e5627fa6b1cd 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -4049,6 +4049,7 @@ static int spi_nor_init(struct spi_nor *nor) { int err; +#ifdef CONFIG_MTD_SPI_NOR_DISABLE_POWER_UP_WRITE_PROTECTION /* * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up * with the software protection bits set. @@ -4082,6 +4083,7 @@ static int spi_nor_init(struct spi_nor *nor) return err; } } +#endif if (nor->quad_enable) { err = nor->quad_enable(nor);