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Tue, 16 Jul 2019 12:32:51 +0000 Received: from VI1PR0801MB2127.eurprd08.prod.outlook.com ([fe80::dcfd:3eda:5cf:aef7]) by VI1PR0801MB2127.eurprd08.prod.outlook.com ([fe80::dcfd:3eda:5cf:aef7%5]) with mapi id 15.20.2073.012; Tue, 16 Jul 2019 12:32:50 +0000 From: Wilco Dijkstra To: GCC Patches CC: nd Subject: [COMMITTED][GCC8] Fix Thumb-1 ldm (PR89190) Date: Tue, 16 Jul 2019 12:32:50 +0000 Message-ID: Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; X-Microsoft-Antispam-Untrusted: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020); SRVR:VI1PR0801MB1968; x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:8273;OLM:8273; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM; SFS:(10009020)(4636009)(136003)(396003)(366004)(376002)(346002)(39860400002)(199004)(189003)(54534003)(7696005)(86362001)(486006)(102836004)(9686003)(66066001)(6506007)(55016002)(316002)(6436002)(476003)(6116002)(81156014)(7736002)(478600001)(4326008)(33656002)(25786009)(14454004)(2906002)(3846002)(6916009)(8936002)(305945005)(186003)(74316002)(26005)(71200400001)(71190400001)(8676002)(76116006)(256004)(66556008)(66446008)(66476007)(64756008)(99286004)(91956017)(66946007)(68736007)(14444005)(5660300002)(81166006)(52536014)(53936002); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0801MB1968; H:VI1PR0801MB2127.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info-Original: sYUdLoMWc03q6ChsmuwBFiguaENmPWMqXwhKqKAbpojatLjjOq5eqVXbORaR9R3BUcMYeh2OYwCavAgcyIJdfLk7dT+TVDNJOWMX+x9qxXGQy83+A9tQncRlM5rp1R1kyaR+pk4xv+HrKpbgxHVs6inH1/YBbUy4AfG+3col/U6/qX7lpJJNmDYQsDjCfC48BV8a7k6grPhNvIU4Y1mOGp9Oci+lVnvq0y+8rbkI7fJnZNtkG1sS7soA4cLESu/1pY0fCR89BMAYhYtGLiUcBWgCrhaXNK9QlRzz61Dn29lZSQYc/ZuFjIg76n8ofhC+DY73uk0rHcj8PKjC7PUIQEM8NfS+QMs9sJA0JNi9EXjVnR0Ly1v0+tHpGCjvzeqaBgySU/JCAOsLUeRyVtc0Inkcne6kb5tAhYknwPGGqSI= MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5EUR03FT003.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: c4eb386c-3940-46fe-dcf2-08d709e9b7af Hi, I've backported PR89190 to GCC8 so it's now fixed on all active branches. Also added pr89190.c testcase to GCC9 and trunk since it was accidentally not committed. Wilco This patch fixes an ICE in the Thumb-1 LDM peepholer. Thumb-1 LDMs always update the base register except if the base is loaded. The current implementation rejects LDMs where the base is not dead, however this doesn't exclude the case where the base is loaded as well as dead. Fix this by explicitly checking whether the base is loaded. Also enable LDMs which load the first register. ChangeLog: 2019-02-04 Wilco Dijkstra PR target/89190 * config/arm/arm.c (ldm_stm_operation_p) Set addr_reg_in_reglist correctly for first register. (load_multiple_sequence): Remove dead base check. (gen_ldm_seq): Correctly set write_back for Thumb-1. PR target/89190 * gcc.target/arm/pr89190.c: New test. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 16e22eed871ca34d56c83c334688e5a95970638e..c4c9b4a667100d81d918196713e40b01ee232ee2 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -13191,6 +13191,9 @@ ldm_stm_operation_p (rtx op, bool load, machine_mode mode, if (load && (REGNO (reg) == SP_REGNUM) && (REGNO (addr) != SP_REGNUM)) return false; + if (regno == REGNO (addr)) + addr_reg_in_reglist = true; + for (; i < count; i++) { elt = XVECEXP (op, 0, i); @@ -13385,7 +13388,6 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, int unsorted_regs[MAX_LDM_STM_OPS]; HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; int order[MAX_LDM_STM_OPS]; - rtx base_reg_rtx = NULL; int base_reg = -1; int i, ldm_case; @@ -13430,7 +13432,6 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, if (i == 0) { base_reg = REGNO (reg); - base_reg_rtx = reg; if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) return 0; } @@ -13489,10 +13490,6 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, *load_offset = unsorted_offsets[order[0]]; } - if (TARGET_THUMB1 - && !peep2_reg_dead_p (nops, base_reg_rtx)) - return 0; - if (unsorted_offsets[order[0]] == 0) ldm_case = 1; /* ldmia */ else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) @@ -13868,9 +13865,17 @@ gen_ldm_seq (rtx *operands, int nops, bool sort_regs) if (TARGET_THUMB1) { - gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx)); gcc_assert (ldm_case == 1 || ldm_case == 5); - write_back = TRUE; + + /* Thumb-1 ldm uses writeback except if the base is loaded. */ + write_back = true; + for (i = 0; i < nops; i++) + if (base_reg == regs[i]) + write_back = false; + + /* Ensure the base is dead if it is updated. */ + if (write_back && !peep2_reg_dead_p (nops, base_reg_rtx)) + return false; } if (ldm_case == 5) @@ -13878,8 +13883,7 @@ gen_ldm_seq (rtx *operands, int nops, bool sort_regs) rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]); emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset))); offset = 0; - if (!TARGET_THUMB1) - base_reg_rtx = newbase; + base_reg_rtx = newbase; } for (i = 0; i < nops; i++) diff --git a/gcc/testsuite/gcc.target/arm/pr89190.c b/gcc/testsuite/gcc.target/arm/pr89190.c new file mode 100644 index 0000000000000000000000000000000000000000..e622d7081ed01a6318e2c4b3e07598d495bd7e0f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr89190.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +long long a; +int b, c; +int d(int e, int f) { return e << f; } +void g() { + long long h; + char i = d(b >= 7, 2); + c = i == 0 ?: 1 / i; + h = c && a ?: c + a; + b = h; +}