From patchwork Tue Jul 16 08:21:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Marginean X-Patchwork-Id: 1132514 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45ntfy5xnZz9sDB for ; Tue, 16 Jul 2019 18:22:18 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 80F97C21DA1; Tue, 16 Jul 2019 08:21:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4E090C21BE5; Tue, 16 Jul 2019 08:21:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1E4E0C21DFA; Tue, 16 Jul 2019 08:21:35 +0000 (UTC) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lists.denx.de (Postfix) with ESMTPS id 3081CC21DF8 for ; Tue, 16 Jul 2019 08:21:32 +0000 (UTC) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A8C7D1A0163; Tue, 16 Jul 2019 10:21:31 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 9CE181A00E4; Tue, 16 Jul 2019 10:21:31 +0200 (CEST) Received: from fsr-ub1864-115.ea.freescale.net (fsr-ub1864-115.ea.freescale.net [10.171.82.26]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 652802061D; Tue, 16 Jul 2019 10:21:31 +0200 (CEST) From: Alex Marginean To: u-boot@lists.denx.de Date: Tue, 16 Jul 2019 11:21:17 +0300 Message-Id: <20190716082118.30181-1-alexandru.marginean@nxp.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Cc: Joe Hershberger Subject: [U-Boot] [PATCH v2 1/2] drivers: net: driver for MDIO muxes controlled over I2C X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This driver is used for MDIO muxes driven over I2C. This is currently used on Freescale LS1028A QDS board, on which the physical MDIO MUX is controlled by an on-board FPGA which in turn is configured through I2C. Signed-off-by: Alex Marginean Acked-by: Joe Hershberger Reviewed-by: Bin Meng --- Changes in v2: - renamed APIs, config options to mdio_mux_i2creg (instead of i2c_reg) drivers/net/Kconfig | 8 +++ drivers/net/Makefile | 1 + drivers/net/mdio_mux_i2creg.c | 108 ++++++++++++++++++++++++++++++++++ 3 files changed, 117 insertions(+) create mode 100644 drivers/net/mdio_mux_i2creg.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4d85fb1716..883b849b78 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -595,4 +595,12 @@ config FSL_ENETC This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. +config MDIO_MUX_I2CREG + bool "MDIO MUX accessed as a register over I2C" + depends on DM_MDIO_MUX && DM_I2C + help + This driver is used for MDIO muxes driven by writing to a register of + an I2C chip. The board it was developed for uses a mux controlled by + on-board FPGA which in turn is accessed as a chip over I2C. + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 97119cec7c..6122bcdb81 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -80,3 +80,4 @@ obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o +obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o diff --git a/drivers/net/mdio_mux_i2creg.c b/drivers/net/mdio_mux_i2creg.c new file mode 100644 index 0000000000..3e82898f46 --- /dev/null +++ b/drivers/net/mdio_mux_i2creg.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 + * Alex Marginean, NXP + */ + +#include +#include +#include +#include + +/* + * This driver is used for MDIO muxes driven by writing to a register of an I2C + * chip. The board it was developed for uses a mux controlled by on-board FPGA + * which in turn is accessed as a chip over I2C. + */ + +struct mdio_mux_i2creg_priv { + struct udevice *chip; + int reg; + int mask; +}; + +static int mdio_mux_i2creg_select(struct udevice *mux, int cur, int sel) +{ + struct mdio_mux_i2creg_priv *priv = dev_get_priv(mux); + u8 val, val_old; + + /* if last selection didn't change we're good to go */ + if (cur == sel) + return 0; + + val_old = dm_i2c_reg_read(priv->chip, priv->reg); + val = (val_old & ~priv->mask) | (sel & priv->mask); + debug("%s: chip %s, reg %x, val %x => %x\n", __func__, priv->chip->name, + priv->reg, val_old, val); + dm_i2c_reg_write(priv->chip, priv->reg, val); + + return 0; +} + +static const struct mdio_mux_ops mdio_mux_i2creg_ops = { + .select = mdio_mux_i2creg_select, +}; + +static int mdio_mux_i2creg_probe(struct udevice *dev) +{ + struct mdio_mux_i2creg_priv *priv = dev_get_priv(dev); + ofnode chip_node, bus_node; + struct udevice *i2c_bus; + u32 reg_mask[2]; + u32 chip_addr; + int err; + + /* read the register addr/mask pair */ + err = dev_read_u32_array(dev, "mux-reg-masks", reg_mask, 2); + if (err) { + debug("%s: error reading mux-reg-masks property\n", __func__); + return err; + } + + /* parent should be an I2C chip, grandparent should be an I2C bus */ + chip_node = ofnode_get_parent(dev->node); + bus_node = ofnode_get_parent(chip_node); + + err = uclass_get_device_by_ofnode(UCLASS_I2C, bus_node, &i2c_bus); + if (err) { + debug("%s: can't find I2C bus for node %s\n", __func__, + ofnode_get_name(bus_node)); + return err; + } + + err = ofnode_read_u32(chip_node, "reg", &chip_addr); + if (err) { + debug("%s: can't read chip address in %s\n", __func__, + ofnode_get_name(chip_node)); + return err; + } + + err = i2c_get_chip(i2c_bus, (uint)chip_addr, 1, &priv->chip); + if (err) { + debug("%s: can't find i2c chip device for addr %x\n", __func__, + chip_addr); + return err; + } + + priv->reg = (int)reg_mask[0]; + priv->mask = (int)reg_mask[1]; + + debug("%s: chip %s, reg %x, mask %x\n", __func__, priv->chip->name, + priv->reg, priv->mask); + + return 0; +} + +static const struct udevice_id mdio_mux_i2creg_ids[] = { + { .compatible = "mdio-mux-i2creg" }, + { } +}; + +U_BOOT_DRIVER(mdio_mux_i2creg) = { + .name = "mdio_mux_i2creg", + .id = UCLASS_MDIO_MUX, + .of_match = mdio_mux_i2creg_ids, + .probe = mdio_mux_i2creg_probe, + .ops = &mdio_mux_i2creg_ops, + .priv_auto_alloc_size = sizeof(struct mdio_mux_i2creg_priv), +}; From patchwork Tue Jul 16 08:21:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Marginean X-Patchwork-Id: 1132515 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45ntgM2kq7z9sDB for ; Tue, 16 Jul 2019 18:22:39 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 160DEC21DED; Tue, 16 Jul 2019 08:22:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 035D8C21E15; Tue, 16 Jul 2019 08:21:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B77BAC21C29; Tue, 16 Jul 2019 08:21:35 +0000 (UTC) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lists.denx.de (Postfix) with ESMTPS id 77C40C21E02 for ; Tue, 16 Jul 2019 08:21:32 +0000 (UTC) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id EFB81200196; Tue, 16 Jul 2019 10:21:31 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E396C20022C; Tue, 16 Jul 2019 10:21:31 +0200 (CEST) Received: from fsr-ub1864-115.ea.freescale.net (fsr-ub1864-115.ea.freescale.net [10.171.82.26]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id AC2F7205F3; Tue, 16 Jul 2019 10:21:31 +0200 (CEST) From: Alex Marginean To: u-boot@lists.denx.de Date: Tue, 16 Jul 2019 11:21:18 +0300 Message-Id: <20190716082118.30181-2-alexandru.marginean@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190716082118.30181-1-alexandru.marginean@nxp.com> References: <20190716082118.30181-1-alexandru.marginean@nxp.com> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Cc: Joe Hershberger Subject: [U-Boot] [PATCH v2 2/2] doc: bindings: Add binding for register driven MDIO muxes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This binding documents two properties that describe the registers used to perform MUX selection. Signed-off-by: Alex Marginean Acked-by: Joe Hershberger Reviewed-by: Bin Meng --- Changes in v2: - renamed APIs, config options to mdio_mux_i2creg (instead of i2c_reg) - expanded example to include all QDS card slots doc/device-tree-bindings/net/mdio-mux-reg.txt | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 doc/device-tree-bindings/net/mdio-mux-reg.txt diff --git a/doc/device-tree-bindings/net/mdio-mux-reg.txt b/doc/device-tree-bindings/net/mdio-mux-reg.txt new file mode 100644 index 0000000000..0ac34dc423 --- /dev/null +++ b/doc/device-tree-bindings/net/mdio-mux-reg.txt @@ -0,0 +1,82 @@ +Device tree structures used by register based MDIO muxes is described here. +This binding is based on reg-mux.txt binding in Linux and is currently used by +mdio-mux-i2creg driver in U-Boot. + +Required properties: +#mux-control-cells = <1> indicates how many registers are used for mux + selection. mux-reg-mask property described below must + include this number of pairs. +mux-reg-masks = describes pairs of register offset and register mask. + Register bits enabled in mask are set to the selection + value defined in reg property of child MDIOs to control + selection. +Properties described in mdio-mux.txt also apply. + +Example structure, used on Freescale LS1028A QDS board: + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf0>; + mdio-parent-bus = <&mdio0>; + + /* on-board MDIO with a single RGMII PHY */ + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + /* on-board 1G RGMII PHY */ + qds_phy0: phy@5 { + reg = <5>; + }; + }; + /* card slot 1 */ + mdio@40 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40>; + /* VSC8234 1G SGMII card */ + sgmii_port0: phy@1c { + reg = <0x1c>; + }; + }; + /* card slot 2 */ + mdio@50 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x50>; + }; + /* card slot 3 */ + mdio@60 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x60>; + }; + /* card slot 4 */ + mdio@70 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; + }; + }; +}; + +/* Parent MDIO, defined in SoC .dtsi file, just enabled here */ +&mdio0 { + status = "okay"; +};