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[79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:45 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 01/13] ARM: tegra: Remove cpuidle drivers to replace them with a new driver Date: Mon, 15 Jul 2019 20:26:17 +0300 Message-Id: <20190715172629.4437-2-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Remove the old drivers to replace them cleanly with a new one later on. Please note that old Tegra20 CPUIDLE driver used pen-locking in order to block secondary CPU waking-up if IRQ happened to raise during of the entering into CC6 and primary CPU already crossed point of no return, but that is unnecessary in practice because CPUIDLE simply won't enter the coupled CC6 state if there is some CPU activity going on. The new driver will ensure that all secondary CPUs parked successfully at first and thus primary CPU won't be racing with the secondaries, hence the pen-locking functionality isn't needed anymore at all. This is the most notable thing of this patch. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/Makefile | 13 -- arch/arm/mach-tegra/cpuidle-tegra114.c | 89 ----------- arch/arm/mach-tegra/cpuidle-tegra20.c | 212 ------------------------- arch/arm/mach-tegra/cpuidle-tegra30.c | 132 --------------- arch/arm/mach-tegra/cpuidle.c | 50 ------ arch/arm/mach-tegra/cpuidle.h | 21 --- arch/arm/mach-tegra/irq.c | 1 - arch/arm/mach-tegra/irq.h | 11 -- arch/arm/mach-tegra/pm.c | 7 - arch/arm/mach-tegra/pm.h | 1 - arch/arm/mach-tegra/reset-handler.S | 11 -- arch/arm/mach-tegra/reset.h | 9 +- arch/arm/mach-tegra/sleep-tegra20.S | 170 -------------------- arch/arm/mach-tegra/sleep.h | 12 -- arch/arm/mach-tegra/tegra.c | 3 - drivers/soc/tegra/Kconfig | 1 - include/soc/tegra/cpuidle.h | 4 - 17 files changed, 2 insertions(+), 745 deletions(-) delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra114.c delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra20.c delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra30.c delete mode 100644 arch/arm/mach-tegra/cpuidle.c delete mode 100644 arch/arm/mach-tegra/cpuidle.h delete mode 100644 arch/arm/mach-tegra/irq.h diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 6c1dff2eccc2..5d93a0b36866 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -8,29 +8,16 @@ obj-y += reset.o obj-y += reset-handler.o obj-y += sleep.o obj-y += tegra.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o -endif obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o -endif obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o -endif obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o -endif obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c deleted file mode 100644 index 5118f777fd66..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include "cpuidle.h" -#include "pm.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -#define TEGRA114_MAX_STATES 2 -#else -#define TEGRA114_MAX_STATES 1 -#endif - -#ifdef CONFIG_PM_SLEEP -static int tegra114_idle_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - local_fiq_disable(); - - tegra_set_cpu_in_lp2(); - cpu_pm_enter(); - - call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2); - - /* Do suspend by ourselves if the firmware does not implement it */ - if (call_firmware_op(do_idle, 0) == -ENOSYS) - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); - - cpu_pm_exit(); - tegra_clear_cpu_in_lp2(); - - local_fiq_enable(); - - return index; -} - -static void tegra114_idle_enter_s2idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - tegra114_idle_power_down(dev, drv, index); -} -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, - .state_count = TEGRA114_MAX_STATES, - .states = { - [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - [1] = { - .enter = tegra114_idle_power_down, - .enter_s2idle = tegra114_idle_enter_s2idle, - .exit_latency = 500, - .target_residency = 1000, - .flags = CPUIDLE_FLAG_TIMER_STOP, - .power_usage = 0, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, -}; - -int __init tegra114_cpuidle_init(void) -{ - if (!psci_smp_available()) - return cpuidle_register(&tegra_idle_driver, NULL); - - return 0; -} diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c deleted file mode 100644 index 2447427cb4a8..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ /dev/null @@ -1,212 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include "cpuidle.h" -#include "iomap.h" -#include "irq.h" -#include "pm.h" -#include "reset.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -static bool abort_flag; -static atomic_t abort_barrier; -static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index); -#define TEGRA20_MAX_STATES 2 -#else -#define TEGRA20_MAX_STATES 1 -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, - .states = { - ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - { - .enter = tegra20_idle_lp2_coupled, - .exit_latency = 5000, - .target_residency = 10000, - .power_usage = 0, - .flags = CPUIDLE_FLAG_COUPLED | - CPUIDLE_FLAG_TIMER_STOP, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, - .state_count = TEGRA20_MAX_STATES, - .safe_state_index = 0, -}; - -#ifdef CONFIG_PM_SLEEP -#ifdef CONFIG_SMP -static int tegra20_reset_sleeping_cpu_1(void) -{ - int ret = 0; - - tegra_pen_lock(); - - if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE) - tegra20_cpu_shutdown(1); - else - ret = -EINVAL; - - tegra_pen_unlock(); - - return ret; -} - -static void tegra20_wake_cpu1_from_reset(void) -{ - tegra_pen_lock(); - - tegra20_cpu_clear_resettable(); - - /* enable cpu clock on cpu */ - tegra_enable_cpu_clock(1); - - /* take the CPU out of reset */ - tegra_cpu_out_of_reset(1); - - /* unhalt the cpu */ - flowctrl_write_cpu_halt(1, 0); - - tegra_pen_unlock(); -} - -static int tegra20_reset_cpu_1(void) -{ - if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1()) - return 0; - - tegra20_wake_cpu1_from_reset(); - return -EBUSY; -} -#else -static inline void tegra20_wake_cpu1_from_reset(void) -{ -} - -static inline int tegra20_reset_cpu_1(void) -{ - return 0; -} -#endif - -static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - while (tegra20_cpu_is_resettable_soon()) - cpu_relax(); - - if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready()) - return false; - - tegra_idle_lp2_last(); - - if (cpu_online(1)) - tegra20_wake_cpu1_from_reset(); - - return true; -} - -#ifdef CONFIG_SMP -static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - cpu_suspend(0, tegra20_sleep_cpu_secondary_finish); - - tegra20_cpu_clear_resettable(); - - return true; -} -#else -static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - return true; -} -#endif - -static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - bool entered_lp2 = false; - - if (tegra_pending_sgi()) - WRITE_ONCE(abort_flag, true); - - cpuidle_coupled_parallel_barrier(dev, &abort_barrier); - - if (abort_flag) { - cpuidle_coupled_parallel_barrier(dev, &abort_barrier); - abort_flag = false; /* clean flag for next coming */ - return -EINTR; - } - - local_fiq_disable(); - - tegra_set_cpu_in_lp2(); - cpu_pm_enter(); - - if (dev->cpu == 0) - entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index); - else - entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index); - - cpu_pm_exit(); - tegra_clear_cpu_in_lp2(); - - local_fiq_enable(); - - smp_rmb(); - - return entered_lp2 ? index : 0; -} -#endif - -/* - * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether - * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around - * this, simply disable LP2 if the PCI driver and DT node are both enabled. - */ -void tegra20_cpuidle_pcie_irqs_in_use(void) -{ - pr_info_once( - "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n"); - tegra_idle_driver.states[1].disabled = true; -} - -int __init tegra20_cpuidle_init(void) -{ - return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); -} diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c deleted file mode 100644 index c6128526877d..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "cpuidle.h" -#include "pm.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -static int tegra30_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index); -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, -#ifdef CONFIG_PM_SLEEP - .state_count = 2, -#else - .state_count = 1, -#endif - .states = { - [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - [1] = { - .enter = tegra30_idle_lp2, - .exit_latency = 2000, - .target_residency = 2200, - .power_usage = 0, - .flags = CPUIDLE_FLAG_TIMER_STOP, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, -}; - -#ifdef CONFIG_PM_SLEEP -static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - /* All CPUs entering LP2 is not working. - * Don't let CPU0 enter LP2 when any secondary CPU is online. - */ - if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) { - cpu_do_idle(); - return false; - } - - tegra_idle_lp2_last(); - - return true; -} - -#ifdef CONFIG_SMP -static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - smp_wmb(); - - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); - - return true; -} -#else -static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - return true; -} -#endif - -static int tegra30_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - bool entered_lp2 = false; - bool last_cpu; - - local_fiq_disable(); - - last_cpu = tegra_set_cpu_in_lp2(); - cpu_pm_enter(); - - if (dev->cpu == 0) { - if (last_cpu) - entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, - index); - else - cpu_do_idle(); - } else { - entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index); - } - - cpu_pm_exit(); - tegra_clear_cpu_in_lp2(); - - local_fiq_enable(); - - smp_rmb(); - - return (entered_lp2) ? index : 0; -} -#endif - -int __init tegra30_cpuidle_init(void) -{ - return cpuidle_register(&tegra_idle_driver, NULL); -} diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c deleted file mode 100644 index d565c44cfc93..000000000000 --- a/arch/arm/mach-tegra/cpuidle.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-tegra/cpuidle.c - * - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include - -#include - -#include "cpuidle.h" - -void __init tegra_cpuidle_init(void) -{ - switch (tegra_get_chip_id()) { - case TEGRA20: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) - tegra20_cpuidle_init(); - break; - case TEGRA30: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) - tegra30_cpuidle_init(); - break; - case TEGRA114: - case TEGRA124: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) - tegra114_cpuidle_init(); - break; - } -} - -void tegra_cpuidle_pcie_irqs_in_use(void) -{ - switch (tegra_get_chip_id()) { - case TEGRA20: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) - tegra20_cpuidle_pcie_irqs_in_use(); - break; - } -} diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h deleted file mode 100644 index 4e1f459f5bd8..000000000000 --- a/arch/arm/mach-tegra/cpuidle.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. - */ - -#ifndef __MACH_TEGRA_CPUIDLE_H -#define __MACH_TEGRA_CPUIDLE_H - -#ifdef CONFIG_CPU_IDLE -int tegra20_cpuidle_init(void); -void tegra20_cpuidle_pcie_irqs_in_use(void); -int tegra30_cpuidle_init(void); -int tegra114_cpuidle_init(void); -void tegra_cpuidle_init(void); -void tegra_cpuidle_pcie_irqs_in_use(void); -#else -static inline void tegra_cpuidle_init(void) {} -static inline void tegra_cpuidle_pcie_irqs_in_use(void) {} -#endif - -#endif diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index ace7a390b5fe..4c065b54cbe7 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -20,7 +20,6 @@ #include "board.h" #include "iomap.h" -#include "irq.h" #define SGI_MASK 0xFFFF diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h deleted file mode 100644 index 7a94cf121448..000000000000 --- a/arch/arm/mach-tegra/irq.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. - */ - -#ifndef __TEGRA_IRQ_H -#define __TEGRA_IRQ_H - -bool tegra_pending_sgi(void); - -#endif diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 3cab81b82866..6aaacb5757e1 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -137,18 +137,11 @@ bool tegra_set_cpu_in_lp2(void) if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) last_cpu = true; - else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1) - tegra20_cpu_set_resettable_soon(); spin_unlock(&tegra_lp2_lock); return last_cpu; } -int tegra_cpu_do_idle(void) -{ - return cpu_do_idle(); -} - static int tegra_sleep_cpu(unsigned long v2p) { /* diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 569151b3edc0..1e51a9b636eb 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -25,7 +25,6 @@ void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); bool tegra_set_cpu_in_lp2(void); -int tegra_cpu_do_idle(void); void tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 67b763fea005..df44828a34d3 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -183,17 +183,6 @@ after_errata: bleq __die @ CPU not present (to OS) #endif -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - /* Are we on Tegra20? */ - cmp r6, #TEGRA20 - bne 1f - /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ - mov r0, #CPU_NOT_RESETTABLE - cmp r10, #0 - strbne r0, [r12, #RESET_DATA(RESETTABLE_STATUS)] -1: -#endif - /* Waking up from LP1? */ ldr r8, [r12, #RESET_DATA(MASK_LP1)] tst r8, r11 @ if in_lp1 diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h index a4cfc08159f6..51265592cb1a 100644 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h @@ -16,9 +16,8 @@ #define TEGRA_RESET_STARTUP_SECONDARY 3 #define TEGRA_RESET_STARTUP_LP2 4 #define TEGRA_RESET_STARTUP_LP1 5 -#define TEGRA_RESET_RESETTABLE_STATUS 6 -#define TEGRA_RESET_TF_PRESENT 7 -#define TEGRA_RESET_DATA_SIZE 8 +#define TEGRA_RESET_TF_PRESENT 6 +#define TEGRA_RESET_DATA_SIZE 7 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) @@ -42,10 +41,6 @@ void __tegra_cpu_reset_handler_end(void); (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ (u32)__tegra_cpu_reset_handler_start))) -#define tegra20_cpu1_resettable_status \ - (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ - ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \ - (u32)__tegra_cpu_reset_handler_start))) #endif #define tegra_cpu_reset_handler_offset \ diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 9a89f30d53ca..0e00ba8cf646 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -43,9 +43,6 @@ #define APB_MISC_XM2CFGCPADCTRL2 0x8e4 #define APB_MISC_XM2CFGDPADCTRL2 0x8e8 -#define __tegra20_cpu1_resettable_status_offset \ - (__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS)) - .macro pll_enable, rd, r_car_base, pll_base ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30) @@ -90,10 +87,6 @@ ENDPROC(tegra20_hotplug_shutdown) ENTRY(tegra20_cpu_shutdown) cmp r0, #0 reteq lr @ must not be called for CPU 0 - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_RESETTABLE - strb r12, [r1, r2] cpu_to_halt_reg r1, r0 ldr r3, =TEGRA_FLOW_CTRL_VIRT @@ -116,107 +109,6 @@ ENDPROC(tegra20_cpu_shutdown) #endif #ifdef CONFIG_PM_SLEEP -/* - * tegra_pen_lock - * - * spinlock implementation with no atomic test-and-set and no coherence - * using Peterson's algorithm on strongly-ordered registers - * used to synchronize a cpu waking up from wfi with entering lp2 on idle - * - * The reference link of Peterson's algorithm: - * http://en.wikipedia.org/wiki/Peterson's_algorithm - * - * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm) - * on cpu 0: - * r2 = flag[0] (in SCRATCH38) - * r3 = flag[1] (in SCRATCH39) - * on cpu1: - * r2 = flag[1] (in SCRATCH39) - * r3 = flag[0] (in SCRATCH38) - * - * must be called with MMU on - * corrupts r0-r3, r12 - */ -ENTRY(tegra_pen_lock) - mov32 r3, TEGRA_PMC_VIRT - cpu_id r0 - add r1, r3, #PMC_SCRATCH37 - cmp r0, #0 - addeq r2, r3, #PMC_SCRATCH38 - addeq r3, r3, #PMC_SCRATCH39 - addne r2, r3, #PMC_SCRATCH39 - addne r3, r3, #PMC_SCRATCH38 - - mov r12, #1 - str r12, [r2] @ flag[cpu] = 1 - dsb - str r12, [r1] @ !turn = cpu -1: dsb - ldr r12, [r3] - cmp r12, #1 @ flag[!cpu] == 1? - ldreq r12, [r1] - cmpeq r12, r0 @ !turn == cpu? - beq 1b @ while !turn == cpu && flag[!cpu] == 1 - - ret lr @ locked -ENDPROC(tegra_pen_lock) - -ENTRY(tegra_pen_unlock) - dsb - mov32 r3, TEGRA_PMC_VIRT - cpu_id r0 - cmp r0, #0 - addeq r2, r3, #PMC_SCRATCH38 - addne r2, r3, #PMC_SCRATCH39 - mov r12, #0 - str r12, [r2] - ret lr -ENDPROC(tegra_pen_unlock) - -/* - * tegra20_cpu_clear_resettable(void) - * - * Called to clear the "resettable soon" flag in IRAM variable when - * it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_clear_resettable) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_NOT_RESETTABLE - strb r12, [r1, r2] - ret lr -ENDPROC(tegra20_cpu_clear_resettable) - -/* - * tegra20_cpu_set_resettable_soon(void) - * - * Called to set the "resettable soon" flag in IRAM variable when - * it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_set_resettable_soon) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_RESETTABLE_SOON - strb r12, [r1, r2] - ret lr -ENDPROC(tegra20_cpu_set_resettable_soon) - -/* - * tegra20_cpu_is_resettable_soon(void) - * - * Returns true if the "resettable soon" flag in IRAM variable has been - * set because it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_is_resettable_soon) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - ldrb r12, [r1, r2] - cmp r12, #CPU_RESETTABLE_SOON - moveq r0, #1 - movne r0, #0 - ret lr -ENDPROC(tegra20_cpu_is_resettable_soon) - /* * tegra20_sleep_core_finish(unsigned long v2p) * @@ -242,68 +134,6 @@ ENTRY(tegra20_sleep_core_finish) ret r3 ENDPROC(tegra20_sleep_core_finish) -/* - * tegra20_sleep_cpu_secondary_finish(unsigned long v2p) - * - * Enters WFI on secondary CPU by exiting coherency. - */ -ENTRY(tegra20_sleep_cpu_secondary_finish) - stmfd sp!, {r4-r11, lr} - - mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency - - /* Flush and disable the L1 data cache */ - mov r0, #TEGRA_FLUSH_CACHE_LOUIS - bl tegra_disable_clean_inv_dcache - - mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT - ldr r4, =__tegra20_cpu1_resettable_status_offset - mov r3, #CPU_RESETTABLE - strb r3, [r0, r4] - - bl tegra_cpu_do_idle - - /* - * cpu may be reset while in wfi, which will return through - * tegra_resume to cpu_resume - * or interrupt may wake wfi, which will return here - * cpu state is unchanged - MMU is on, cache is on, coherency - * is off, and the data cache is off - * - * r11 contains the original actlr - */ - - bl tegra_pen_lock - - mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT - ldr r4, =__tegra20_cpu1_resettable_status_offset - mov r3, #CPU_NOT_RESETTABLE - strb r3, [r0, r4] - - bl tegra_pen_unlock - - /* Re-enable the data cache */ - mrc p15, 0, r10, c1, c0, 0 - orr r10, r10, #CR_C - mcr p15, 0, r10, c1, c0, 0 - isb - - mcr p15, 0, r11, c1, c0, 1 @ reenable coherency - - /* Invalidate the TLBs & BTAC */ - mov r1, #0 - mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs - mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC - dsb - isb - - /* the cpu was running with coherency disabled, - * caches may be out of date */ - bl v7_flush_kern_cache_louis - - ldmfd sp!, {r4 - r11, pc} -ENDPROC(tegra20_sleep_cpu_secondary_finish) - /* * tegra20_tear_down_cpu * diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 78ef32a907c8..d219872b7546 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -114,8 +114,6 @@ .endm #else -void tegra_pen_lock(void); -void tegra_pen_unlock(void); void tegra_resume(void); int tegra_sleep_cpu_finish(unsigned long); void tegra_disable_clean_inv_dcache(u32 flag); @@ -125,16 +123,6 @@ void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); #endif -void tegra20_cpu_shutdown(int cpu); -int tegra20_cpu_is_resettable_soon(void); -void tegra20_cpu_clear_resettable(void); -#ifdef CONFIG_ARCH_TEGRA_2x_SOC -void tegra20_cpu_set_resettable_soon(void); -#else -static inline void tegra20_cpu_set_resettable_soon(void) {} -#endif - -int tegra20_sleep_cpu_secondary_finish(unsigned long); void tegra20_tear_down_cpu(void); int tegra30_sleep_cpu_secondary_finish(unsigned long); void tegra30_tear_down_cpu(void); diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index e512e606eabd..d9237769a37c 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -40,9 +40,7 @@ #include "board.h" #include "common.h" -#include "cpuidle.h" #include "iomap.h" -#include "irq.h" #include "pm.h" #include "reset.h" #include "sleep.h" @@ -86,7 +84,6 @@ static void __init tegra_dt_init(void) static void __init tegra_dt_init_late(void) { tegra_init_suspend(); - tegra_cpuidle_init(); if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("compal,paz00")) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index c8ef05d6b8c7..d98c69efb7e0 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -6,7 +6,6 @@ if ARM config ARCH_TEGRA_2x_SOC bool "Enable support for Tegra20 family" - select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARM_ERRATA_720789 select ARM_ERRATA_754327 if SMP select ARM_ERRATA_764369 if SMP diff --git a/include/soc/tegra/cpuidle.h b/include/soc/tegra/cpuidle.h index 029ba1f4b2cc..f758808342b6 100644 --- a/include/soc/tegra/cpuidle.h +++ b/include/soc/tegra/cpuidle.h @@ -6,12 +6,8 @@ #ifndef __SOC_TEGRA_CPUIDLE_H__ #define __SOC_TEGRA_CPUIDLE_H__ -#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_TEGRA) && defined(CONFIG_CPU_IDLE) -void tegra_cpuidle_pcie_irqs_in_use(void); -#else static inline void tegra_cpuidle_pcie_irqs_in_use(void) { } -#endif #endif /* __SOC_TEGRA_CPUIDLE_H__ */ From patchwork Mon Jul 15 17:26:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132139 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Jst9Ui9q"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVtH0NmWz9sMQ for ; Tue, 16 Jul 2019 03:30:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731804AbfGOR3w (ORCPT ); Mon, 15 Jul 2019 13:29:52 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:39008 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731656AbfGOR3t (ORCPT ); Mon, 15 Jul 2019 13:29:49 -0400 Received: by mail-lj1-f194.google.com with SMTP id v18so17086498ljh.6; Mon, 15 Jul 2019 10:29:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wAZS/gHavS5YSEczNZRmVNHcV03HXfR9BNASQHjKGJI=; b=Jst9Ui9qHEGJyoR820DT+dbzNqmoyU0griYCNuZ+AAWmlsLDSbF4r4hKBnx9FiGw6s oqMpVKkdKs3dwznQ9d0PKfyxuuI8cPmU59grmhvotih4QLX3FJkKCL6yLghvu05Fbc5H la0RYf84/EMum0P2XfBh13fdfWn7OYABemb0hJawquoRbUB4dDRnZNWIXR0utvX2dnLW mcHgtrH7GNnAaKQCkPAWF3yBW9MY8O3Z2gsBNpnl18rO0+OTXeLd9U9HV23+M8rzjW/+ OZ3ecwiWSduDbZYK5iZwDoDqUtmlmNPJLBI7C1Q42+W1nE1kZ7GgGDjZTx1XPxJjNRVF dzbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wAZS/gHavS5YSEczNZRmVNHcV03HXfR9BNASQHjKGJI=; b=DUu796qmThvHHQOI/otRylGNr0XFqzKaByzFE6TdSMhsmt1N1a0CCG5Xv2kQ1rkSrg p5bMMuoc7FCj6iJTt1ksnjCjTtNHRN62vehBw7zmCdmG5nw+YYWI6b8bGhyABo/tknko iId2unYrpR6G0j/nMk1UNgTsH/mc4jP9HDSmsWsqK6i+sS0F3/aeaR+dXPRMSnXl38FW s85RtMwRMKX6HSA5KktxXC5nrB8LASxdeoaZO0+Sh3Vs79pughN8odwpvRtGrci9YeyU NT33dQ90SM1efpwZMeDH1HYcsu86fpOo3Js3gA39OCwxh7wjhIfQpKF7BAqNGrSWkxsb MyMw== X-Gm-Message-State: APjAAAWrcRrVxZZ4PpS34vltHO59wDLidYfkHVfAbbWP0MpREwijEjxw 58D8FtcgrlAf/eJv5uHaDKI= X-Google-Smtp-Source: APXvYqz/YOgCfk53IIHGcYQxyANpzzg7RT4bR0PVoEUmFsvNwc8I9plE9nCfBGaGoEESIt9W98AkeA== X-Received: by 2002:a2e:7818:: with SMTP id t24mr14310263ljc.210.1563211786801; Mon, 15 Jul 2019 10:29:46 -0700 (PDT) Received: from localhost.localdomain (ppp79-139-233-208.pppoe.spdop.ru. [79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:46 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/13] ARM: tegra: Change tegra_set_cpu_in_lp2() type to void Date: Mon, 15 Jul 2019 20:26:18 +0300 Message-Id: <20190715172629.4437-3-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The old Tegra30 CPUIDLE driver had intention to check whether primary CPU was the last CPU that entered LP2 (CC6) idle-state, but that functionality never got utilized by the old-removed driver because it never supported the CC6 while secondary CPUs were online. The new driver will properly support CC6 on Tegra30, including the case where secondary CPUs are online, and that knowledge about what CPUs entered CC6 won't be needed at all because new driver will use different approach by making use of the coupled idle-state and explicitly parking secondary CPUs before entering into CC6. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 8 +------- arch/arm/mach-tegra/pm.h | 2 +- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 6aaacb5757e1..2f6fb54be9f8 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -123,11 +123,9 @@ void tegra_clear_cpu_in_lp2(void) spin_unlock(&tegra_lp2_lock); } -bool tegra_set_cpu_in_lp2(void) +void tegra_set_cpu_in_lp2(void) { int phy_cpu_id = cpu_logical_map(smp_processor_id()); - bool last_cpu = false; - cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; spin_lock(&tegra_lp2_lock); @@ -135,11 +133,7 @@ bool tegra_set_cpu_in_lp2(void) BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); *cpu_in_lp2 |= BIT(phy_cpu_id); - if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) - last_cpu = true; - spin_unlock(&tegra_lp2_lock); - return last_cpu; } static int tegra_sleep_cpu(unsigned long v2p) diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 1e51a9b636eb..3f3164ad04b7 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -24,7 +24,7 @@ void tegra30_lp1_iram_hook(void); void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); -bool tegra_set_cpu_in_lp2(void); +void tegra_set_cpu_in_lp2(void); void tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); From patchwork Mon Jul 15 17:26:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132141 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YCxjBQ0d"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVtK2CvPz9sMQ for ; Tue, 16 Jul 2019 03:30:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731763AbfGOR3w (ORCPT ); Mon, 15 Jul 2019 13:29:52 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:35004 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730774AbfGOR3u (ORCPT ); Mon, 15 Jul 2019 13:29:50 -0400 Received: by mail-lj1-f196.google.com with SMTP id x25so17126918ljh.2; Mon, 15 Jul 2019 10:29:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RatHWh+WSZJO51BDaAO/tJPgTyTi6HlHiiIlwIODHqM=; b=YCxjBQ0dgT+LIdjwWrqKjoEqsb1bDymfKP3kPV6zR9IjEopiAu0/EqlOebUUfHDX5w zz+4Tvgg0oDcoZ2pVEGcgghbm0LXuJN142WjlGSdRDdgrpRvwAHQ+jNjbsKkhyhGAElY P5D6/38/7GcB1LVFXGCNkSLfs8eLXr/pIwRbh9lm2+HvDzYK7mbn2snTjQ3+5J8GR5aV ehv5RjiXuc74y3AEAXMa0yBTmOWtGeGLlqc6pUj+A2YfHTXnM/GHXjEadwLyUBrDK3le x1JgQS5hd85AZzGH0WxnyNnEuxnGNW8PEbDcWM1IxSjE9cnDlr4lViHNlTq8LPkQ+bWu oZig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RatHWh+WSZJO51BDaAO/tJPgTyTi6HlHiiIlwIODHqM=; b=BPjXXAHQWmtj9Aryjy+qx6ijFkxaYkxVg1Y2Y+0KfMzJMpyP9JKH29/V4R7/FtFAD9 w9gYp9yKornjpniRpZzrx6IcD617CMxeQ8q8z1tqiYlEBv0WuE5w9zPOME5bqzjzs8Lc aPPNARBfU9PqrcDypqVvJ8b7MwaU1vJdWEAR3Ys5WFZiv+NYGI9RQooEBbhZ7V5lM9S+ gD9jY41UATjy/LEmtz6DzAq2UryAHqsxi9GShdkxcCePvG9ZnYjAF7nGCZ8iPtuWXuiJ oy4Esk3JkAiCjW4BSp5e3rsvnhjxxKlkRcTGN+b+au/PE+Cr33BSXhUAqfRjwkLCZzqU BUkw== X-Gm-Message-State: APjAAAUrIOMcAHaPcniJWXYfojYrEZq+SppsMlwF/yMf20/j7x7hXfUB nc2R6K3d4aSEAk9UD9OresI= X-Google-Smtp-Source: APXvYqybrC/BDz0zU8yBa2W+gs2MV9KsGr77hQlEYneiZ1tKRQSVHKyXIgKDtPbQLztrw5DYuoDAWA== X-Received: by 2002:a2e:80d6:: with SMTP id r22mr14795572ljg.83.1563211787757; Mon, 15 Jul 2019 10:29:47 -0700 (PDT) Received: from localhost.localdomain (ppp79-139-233-208.pppoe.spdop.ru. [79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:47 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 03/13] ARM: tegra: Propagate error from tegra_idle_lp2_last() Date: Mon, 15 Jul 2019 20:26:19 +0300 Message-Id: <20190715172629.4437-4-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The cpu_suspend() may fail, it's never good to lose information about failure because it may become very useful for the caller. The new CPUIDLE driver will handle all of possible error cases, including the case of tegra_idle_lp2_last() failure. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 8 ++++++-- arch/arm/mach-tegra/pm.h | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 2f6fb54be9f8..f9c9bce9e15d 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -189,14 +189,16 @@ static void tegra_pm_set(enum tegra_suspend_mode mode) tegra_pmc_enter_suspend_mode(mode); } -void tegra_idle_lp2_last(void) +int tegra_idle_lp2_last(void) { + int err; + tegra_pm_set(TEGRA_SUSPEND_LP2); cpu_cluster_pm_enter(); suspend_cpu_complex(); - cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); + err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); /* * Resume L2 cache if it wasn't re-enabled early during resume, @@ -208,6 +210,8 @@ void tegra_idle_lp2_last(void) restore_cpu_complex(); cpu_cluster_pm_exit(); + + return err; } enum tegra_suspend_mode tegra_pm_validate_suspend_mode( diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 3f3164ad04b7..ae68fc7db576 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -25,7 +25,7 @@ void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); void tegra_set_cpu_in_lp2(void); -void tegra_idle_lp2_last(void); +int tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); #ifdef CONFIG_PM_SLEEP From patchwork Mon Jul 15 17:26:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132140 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vCDCTz4k"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVtH5gH2z9sND for ; Tue, 16 Jul 2019 03:30:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731783AbfGOR3w (ORCPT ); Mon, 15 Jul 2019 13:29:52 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:33991 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731748AbfGOR3u (ORCPT ); Mon, 15 Jul 2019 13:29:50 -0400 Received: by mail-lj1-f196.google.com with SMTP id p17so17128846ljg.1; Mon, 15 Jul 2019 10:29:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FDvoYJijQDj0e5NVUU9jZaC+GnZsfGAQXtnAmVIR6ZQ=; b=vCDCTz4k6ibrzwfwNdeN+QpnCYvtQK66tnraZCMhEnIysb+LegW/a5Uc64VRj4SaU2 8Guoou6qyCgc364/AgBeS6Oj9/PRUt5lhi/C25kV5E0jZ+2IWfgGw91u0PBTrWXDwjcn aMaOOvwW+PYPX8vhhpxRw0TjW8cIRyHVj51xe3ZaS3GrLIVwWM5U23xNq87CH+y0cycH r5arqIdqvAClhNL9WNLnllouWyl3JNkQA9RJ/go+uJuFtoVaSYxubNenlPueb1o7WW/W swt5B/PhZC8orVlaNFvTw8M8gH4f2SSveJtKIypnEOXWMeWuGzbCJtzjT/BTtJJhk7Cf 8SFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FDvoYJijQDj0e5NVUU9jZaC+GnZsfGAQXtnAmVIR6ZQ=; b=RYl+imMH1buzi1WCdqJJGcba9OtM04tanHnFR2pHBdgdUS1YQBjLTjmVHQ2rSwg7dA p6zuLdZJprSuafkZNSVNqD25fwsuUfM5vtYk/DwwmaMClKmHbui7NX+KXOCAXKaxncbH QzrjF1Ez/sCSq3DCePRKf5OclEHu04QqObixSYQZJNYAnlOOQ1XiPcj6/XaXdY/wWgiq eXxt+S968U8+k3pIkQI8wixx96pS0uEhKz0Or23QXBN8QGGlU5W1w3AV0XHmOt3PfA1n baqK0nMDqyqpGft3x3Pdkb39mlQh45gHYz7Jy8qK3kVKng900WRSYbHVr0pkv2CYBi2h 33rA== X-Gm-Message-State: APjAAAW1msrPlLHk/XgJYrAOGvYZW6fLOac3e9WQkbksj5OfCCwASmCI Y1o/ovrjcq9RjS4YjkQcaFM= X-Google-Smtp-Source: APXvYqzGgMxupCB4y5ESBKTMjENgc8s/BGZx9EIFl4ilpmAfr/qequ4G3zvviFCti3oOxbKWcNwAcQ== X-Received: by 2002:a2e:301a:: with SMTP id w26mr14325712ljw.76.1563211788725; Mon, 15 Jul 2019 10:29:48 -0700 (PDT) Received: from localhost.localdomain (ppp79-139-233-208.pppoe.spdop.ru. [79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:48 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 04/13] ARM: tegra: Compile sleep-tegra20/30.S unconditionally Date: Mon, 15 Jul 2019 20:26:20 +0300 Message-Id: <20190715172629.4437-5-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The sleep-tegra*.S provides functionality required for suspend/resume and CPU hotplugging. The new unified CPUIDLE driver will support multiple hardware generations starting from Terga20 and ending with Tegra124, the driver will utilize functions that are provided by the assembly and thus it is cleaner to compile that code without any build-dependencies in order to avoid churning with #ifdef's. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/Makefile | 10 ++++------ arch/arm/mach-tegra/sleep.h | 2 -- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 5d93a0b36866..3bb44246d928 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -8,16 +8,14 @@ obj-y += reset.o obj-y += reset-handler.o obj-y += sleep.o obj-y += tegra.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o +obj-y += sleep-tegra20.o +obj-y += sleep-tegra30.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index d219872b7546..4978def9db46 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -118,10 +118,8 @@ void tegra_resume(void); int tegra_sleep_cpu_finish(unsigned long); void tegra_disable_clean_inv_dcache(u32 flag); -#ifdef CONFIG_HOTPLUG_CPU void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); -#endif void tegra20_tear_down_cpu(void); int tegra30_sleep_cpu_secondary_finish(unsigned long); From patchwork Mon Jul 15 17:26:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132138 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="RWQpIYdo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVtG38Wmz9sNH for ; Tue, 16 Jul 2019 03:30:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731810AbfGOR3x (ORCPT ); Mon, 15 Jul 2019 13:29:53 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:35006 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731749AbfGOR3v (ORCPT ); Mon, 15 Jul 2019 13:29:51 -0400 Received: by mail-lj1-f195.google.com with SMTP id x25so17127020ljh.2; Mon, 15 Jul 2019 10:29:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RWP8nyImS39zSZSpsquwa+7h83m45I0RXPq4864glDw=; b=RWQpIYdoamyKmsukWr13hJKtqCnneWSq7yu7efc2V+0BLViyoxGqimT0vQG+N9f+0O zHpnUDGzaMXjKc4DP/e9FLmXS3frE8y/S15vaw54SFmIjEboEsRt2E9s98CFEiCIPaJD w8LM4N2C+okvLbnYWxVma0ZF6mQhd9bJKugJ6sklqJ/kIcN4h5vlgNWl/ai9bQUffWom LXZYl7QqJrZ7COD1pQyzYwM49UB/3RLsw7Tz2EYh8EgTiPmhnnsqdnyQANEFAIOCE2+5 pgizxgEs77aCxJMBfvsbsxskUMc6z+9NR1G0MghmRGnyBPUcYtckCXkV2kMFGr6INU5O PbMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RWP8nyImS39zSZSpsquwa+7h83m45I0RXPq4864glDw=; b=tl9SYeMiOErvszcMdWI7gBiKCxHzevS+1T2vwI0BzIobR+pdZjLwRjiLeHtWWy2MWf MaCmNwY3hcL9wUMCYLKgw3MA5/bddIvBhA5jJlXMT9sKoJnuZj4EWpo4VFLipDFGvEnV m8PGrtoQOwvkaFnl7B7WQjabjoPefkK1wDR7it1L1g/A5+Y4mWW6RgjLT6jObtvYHdLg 5rA1xZxtZE1dKk8V97MsrR3IDcenRb2g1Sx1N3bM26dQLPw6dhKmoPgWWG5q2hM032RF klggusoCc29VLS8l2Svi7quPpHJw80xs4RtYdz3fLH2e56CwWsKtfFm2tSv72q2Wj7TJ n4Rg== X-Gm-Message-State: APjAAAUHXle/lLX+5gbb3wqPBjirXMUtpAeuNmrjy2OYN1hZaePEIS2V V02nNNpAJEF4ezi+2U3Sj0I= X-Google-Smtp-Source: APXvYqw8bOGPiSnN9XxJlrOgVc0nqpbRzNvMF09KebTKnS4GmvoNRJ9SePz7z9OknQhgOqy29kWAvg== X-Received: by 2002:a2e:a415:: with SMTP id p21mr14666214ljn.111.1563211789666; Mon, 15 Jul 2019 10:29:49 -0700 (PDT) Received: from localhost.localdomain (ppp79-139-233-208.pppoe.spdop.ru. [79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:49 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 05/13] ARM: tegra: Expose PM functions required for new cpuidle driver Date: Mon, 15 Jul 2019 20:26:21 +0300 Message-Id: <20190715172629.4437-6-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The upcoming unified CPUIDLE driver will be added to the drivers/cpuidle/ directory and it will require all these exposed Tegra PM-core functions. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/irq.c | 2 ++ arch/arm/mach-tegra/pm.h | 3 --- arch/arm/mach-tegra/sleep.h | 1 - include/soc/tegra/irq.h | 13 +++++++++++++ include/soc/tegra/pm.h | 25 +++++++++++++++++++++++++ 5 files changed, 40 insertions(+), 4 deletions(-) create mode 100644 include/soc/tegra/irq.h diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 4c065b54cbe7..4e1ee70b2a3f 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -18,6 +18,8 @@ #include #include +#include + #include "board.h" #include "iomap.h" diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index ae68fc7db576..81525f5f4a44 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -23,9 +23,6 @@ void tegra20_sleep_core_init(void); void tegra30_lp1_iram_hook(void); void tegra30_sleep_core_init(void); -void tegra_clear_cpu_in_lp2(void); -void tegra_set_cpu_in_lp2(void); -int tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); #ifdef CONFIG_PM_SLEEP diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 4978def9db46..4718a3cb45a1 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -122,7 +122,6 @@ void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); void tegra20_tear_down_cpu(void); -int tegra30_sleep_cpu_secondary_finish(unsigned long); void tegra30_tear_down_cpu(void); #endif diff --git a/include/soc/tegra/irq.h b/include/soc/tegra/irq.h new file mode 100644 index 000000000000..8eb11a7109e4 --- /dev/null +++ b/include/soc/tegra/irq.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. + */ + +#ifndef __SOC_TEGRA_IRQ_H +#define __SOC_TEGRA_IRQ_H + +#if defined(CONFIG_ARM) +bool tegra_pending_sgi(void); +#endif + +#endif /* __SOC_TEGRA_IRQ_H */ diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index 951fcd738d55..bc1abdf41d61 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -6,6 +6,8 @@ #ifndef __SOC_TEGRA_PM_H__ #define __SOC_TEGRA_PM_H__ +#include + enum tegra_suspend_mode { TEGRA_SUSPEND_NONE = 0, TEGRA_SUSPEND_LP2, /* CPU voltage off */ @@ -20,6 +22,11 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode); /* low-level resume entry point */ void tegra_resume(void); + +int tegra30_sleep_cpu_secondary_finish(unsigned long arg); +void tegra_clear_cpu_in_lp2(void); +void tegra_set_cpu_in_lp2(void); +int tegra_idle_lp2_last(void); #else static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) @@ -30,6 +37,24 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) static inline void tegra_resume(void) { } + +static inline int tegra30_sleep_cpu_secondary_finish(unsigned long arg) +{ + return -ENOTSUPP; +} + +static inline void tegra_clear_cpu_in_lp2(void) +{ +} + +static inline void tegra_set_cpu_in_lp2(void) +{ +} + +static inline int tegra_idle_lp2_last(void) +{ + return -ENOTSUPP; +} #endif /* CONFIG_PM_SLEEP */ #endif /* __SOC_TEGRA_PM_H__ */ From patchwork Mon Jul 15 17:26:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132137 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BbJ828kF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVtF0Vv9z9sMQ for ; Tue, 16 Jul 2019 03:30:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731831AbfGOR3x (ORCPT ); Mon, 15 Jul 2019 13:29:53 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:46934 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731751AbfGOR3x (ORCPT ); Mon, 15 Jul 2019 13:29:53 -0400 Received: by mail-lj1-f196.google.com with SMTP id v24so17113087ljg.13; Mon, 15 Jul 2019 10:29:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NH6XObUnMoJEgSclRt0t6O4vavDHd+pv9Qe4go8awrw=; b=BbJ828kFCqPNTHApzW5LDPTdpAdpOwvsLzCFty608E8wDMgsP1XkZCNm7VMV+2E+06 fPJJDJbk+YlyIxpbivZhHOw8RYbiaOkQr7jq2C+7YxgMIb9RTi8dndZRSiZKsyWF6F7a NHib5eRuSxu3ILrJBn6F5AL5FAoLbFrG0CUGWSO4KHqIB+4F2xms0rN6VmxZA1Z7+f6j Owkh83S8itTZknckh30yC5xAz5MKqBV7fNbD9O0CkKnPPdlsjm4i+gfZr6od7NACjn9n 4s+aWfZlPjiOCoJg6tdXQXMqBrsNR1Mvd3gX2RfBSBpV3LqQBgT1N+1EQILk2XQ3o8/z /PAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NH6XObUnMoJEgSclRt0t6O4vavDHd+pv9Qe4go8awrw=; b=tsTsk7/rD4GAp2BsUV7GLi9w1oESzyB6OIHG7l6NKYjdiEwlM7Sk4eDO0xZlIIfIDB z6uwzurm3eOFVG3xlXem7jz5gkPoi032Y9Gxb7B8igoN4D4A3U4uuaELiIdLxldQ0HBz i5zt+J6o7a/qSbmaKkUwpIrlN+8qTIAIEhfUmR47DuWMAwhTrrhzifzGUOGqxuAx9Aij Q2i16SlpOEyWODsXHenN0t+rpJX8VLq6Q+clKIXJ5wHTE9prDfWL7CPlGmbDpH/yQyhU A5j3Oo4RgGpRZ9N778BxWQrrJhrQrDbwZ20hUgkl9LV8sjrYaTWUYCgTfQTmmd+A+eMY WAEg== X-Gm-Message-State: APjAAAUztB8pINtYcFSUoHtRlnO4OAwhgsm+QSZSxerasR1SEQMsli4E u3MJORzruYuq5Smc1HwD2J0= X-Google-Smtp-Source: APXvYqxaW6beHBsuSFoN5AgBhdc8iDZOUW0gyu9p6ltekagezmd/bo3Hdv/3qXfmwFIUlezdv0Y1ug== X-Received: by 2002:a2e:98d7:: with SMTP id s23mr14381746ljj.179.1563211790667; Mon, 15 Jul 2019 10:29:50 -0700 (PDT) Received: from localhost.localdomain (ppp79-139-233-208.pppoe.spdop.ru. [79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:50 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 06/13] ARM: tegra: Rename some of the newly exposed PM functions Date: Mon, 15 Jul 2019 20:26:22 +0300 Message-Id: <20190715172629.4437-7-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Rename some of the recently exposed PM functions, prefixing them with "tegra_pm_" and making naming of those functions more meaningful, for consistency. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 10 +++++----- arch/arm/mach-tegra/sleep-tegra30.S | 6 +++--- include/soc/tegra/pm.h | 16 ++++++++-------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index f9c9bce9e15d..4cc64a135a3e 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -110,7 +110,7 @@ static void suspend_cpu_complex(void) flowctrl_cpu_suspend_enter(cpu); } -void tegra_clear_cpu_in_lp2(void) +void tegra_pm_clear_cpu_in_lp2(void) { int phy_cpu_id = cpu_logical_map(smp_processor_id()); u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; @@ -123,7 +123,7 @@ void tegra_clear_cpu_in_lp2(void) spin_unlock(&tegra_lp2_lock); } -void tegra_set_cpu_in_lp2(void) +void tegra_pm_set_cpu_in_lp2(void) { int phy_cpu_id = cpu_logical_map(smp_processor_id()); u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; @@ -189,7 +189,7 @@ static void tegra_pm_set(enum tegra_suspend_mode mode) tegra_pmc_enter_suspend_mode(mode); } -int tegra_idle_lp2_last(void) +int tegra_pm_enter_lp2(void) { int err; @@ -356,7 +356,7 @@ static int tegra_suspend_enter(suspend_state_t state) tegra_suspend_enter_lp1(); break; case TEGRA_SUSPEND_LP2: - tegra_set_cpu_in_lp2(); + tegra_pm_set_cpu_in_lp2(); break; default: break; @@ -377,7 +377,7 @@ static int tegra_suspend_enter(suspend_state_t state) tegra_suspend_exit_lp1(); break; case TEGRA_SUSPEND_LP2: - tegra_clear_cpu_in_lp2(); + tegra_pm_clear_cpu_in_lp2(); break; default: break; diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index b408fa56eb89..386319a3d2d2 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -262,11 +262,11 @@ ENTRY(tegra30_sleep_core_finish) ENDPROC(tegra30_sleep_core_finish) /* - * tegra30_sleep_cpu_secondary_finish(unsigned long v2p) + * tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg) * * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. */ -ENTRY(tegra30_sleep_cpu_secondary_finish) +ENTRY(tegra30_pm_secondary_cpu_suspend) mov r7, lr /* Flush and disable the L1 data cache */ @@ -278,7 +278,7 @@ ENTRY(tegra30_sleep_cpu_secondary_finish) bl tegra30_cpu_shutdown mov r0, #1 @ never return here ret r7 -ENDPROC(tegra30_sleep_cpu_secondary_finish) +ENDPROC(tegra30_pm_secondary_cpu_suspend) /* * tegra30_tear_down_cpu diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index bc1abdf41d61..2fbee9efda21 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -23,10 +23,10 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode); /* low-level resume entry point */ void tegra_resume(void); -int tegra30_sleep_cpu_secondary_finish(unsigned long arg); -void tegra_clear_cpu_in_lp2(void); -void tegra_set_cpu_in_lp2(void); -int tegra_idle_lp2_last(void); +int tegra30_pm_secondary_cpu_suspend(unsigned long arg); +void tegra_pm_clear_cpu_in_lp2(void); +void tegra_pm_set_cpu_in_lp2(void); +int tegra_pm_enter_lp2(void); #else static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) @@ -38,20 +38,20 @@ static inline void tegra_resume(void) { } -static inline int tegra30_sleep_cpu_secondary_finish(unsigned long arg) +static inline int tegra30_pm_secondary_cpu_suspend(unsigned long arg) { return -ENOTSUPP; } -static inline void tegra_clear_cpu_in_lp2(void) +static inline void tegra_pm_clear_cpu_in_lp2(void) { } -static inline void tegra_set_cpu_in_lp2(void) +static inline void tegra_pm_set_cpu_in_lp2(void) { } -static inline int tegra_idle_lp2_last(void) +static inline int tegra_pm_enter_lp2(void) { return -ENOTSUPP; } From patchwork Mon Jul 15 17:26:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132135 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cDT1znoq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVt600vQz9sMQ for ; Tue, 16 Jul 2019 03:30:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731844AbfGOR3z (ORCPT ); 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[79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:51 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 07/13] ARM: tegra: Add tegra_pm_park_secondary_cpu() Date: Mon, 15 Jul 2019 20:26:23 +0300 Message-Id: <20190715172629.4437-8-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This function resembles tegra_cpu_die() of the hotplug code, but this variant is more suitable to be used for CPU PM because it's made specifically to be used by cpu_suspend(). In short this function puts secondary CPU offline, it will be used by the new CPUIDLE driver. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 14 ++++++++++++++ include/soc/tegra/pm.h | 6 ++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 4cc64a135a3e..7d9ef26e52a7 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -427,4 +427,18 @@ void __init tegra_init_suspend(void) suspend_set_ops(&tegra_suspend_ops); } + +int tegra_pm_park_secondary_cpu(unsigned long cpu) +{ + if (cpu > 0) { + tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS); + + if (tegra_get_chip_id() == TEGRA20) + tegra20_hotplug_shutdown(); + else + tegra30_hotplug_shutdown(); + } + + return -EINVAL; +} #endif diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index 2fbee9efda21..08477d7bfab9 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -27,6 +27,7 @@ int tegra30_pm_secondary_cpu_suspend(unsigned long arg); void tegra_pm_clear_cpu_in_lp2(void); void tegra_pm_set_cpu_in_lp2(void); int tegra_pm_enter_lp2(void); +int tegra_pm_park_secondary_cpu(unsigned long cpu); #else static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) @@ -55,6 +56,11 @@ static inline int tegra_pm_enter_lp2(void) { return -ENOTSUPP; } + +static inline int tegra_pm_park_secondary_cpu(unsigned long cpu) +{ + return -ENOTSUPP; +} #endif /* CONFIG_PM_SLEEP */ #endif /* __SOC_TEGRA_PM_H__ */ From patchwork Mon Jul 15 17:26:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132136 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="G9r1UpHe"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVt71tgkz9sMr for ; Tue, 16 Jul 2019 03:30:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732127AbfGORai (ORCPT ); Mon, 15 Jul 2019 13:30:38 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:43447 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731820AbfGOR3y (ORCPT ); Mon, 15 Jul 2019 13:29:54 -0400 Received: by mail-lj1-f195.google.com with SMTP id 16so17082390ljv.10; Mon, 15 Jul 2019 10:29:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YB/K51J2yBjrGqQBOAGlFNTt2rdW770Na58VRvSkzkE=; b=G9r1UpHe9emFel8CP1Z4Q/bhOOyPPtMwUPGjut2D2WJ5X7sg4agszqUKUO42WEeXxO 1P7iKfqH87IK9lPCUtqFtNDS7Y7ETgi9VOuufW9wEt0GpnZzfvUgQIczex830SIwXAQe tgAppGVlXy7vn1hY6MRXISj6MJH0nksjUdyEtOtf+oG1AbeQ3HgTr8BiFfwmNxx2Q0aT +k4pdY/TSo0M8pbgIibURbNgg+Czv6saq/6yVQlzWO5VnMDYV77Im8fdJnCKkfaKceJy HKmHmt/U/lii15n2Cev059HpaEWR5zxR57bEnrPjRTNJqxiZ/n3rHPFHx6RSnZjzDSLi MmSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YB/K51J2yBjrGqQBOAGlFNTt2rdW770Na58VRvSkzkE=; b=UZFDIVNCvCPW1SRDrj9dhrFjv4FLkWzDfkDD+z+XMfWluM0VVE2vHBGtOHRcdUarMb mS4YrnQqnrY6KKHuRjPpv45FaIUAZKEm2SUCcOcp6gCmPAuujfEOmTqMZaleN6zSbUl4 xjQBEogb2te9Yd1AEtOfXZGRe4Gq987XwyNf4KvFqIr29phzrtMlYOke+9Jr8rJT3BhC W+iZIxXhDNa6qJyxEjBeqdy0P/n8A+1It5TymcPUqRcVoz1ORxXM4Jtw1QkZAkwvlmvO I0WPcdujtoOTEK3TX9Pe7LIAGRkcOXZtQQSjkG2HanObbnzPlkfDfxncnP87WJmy+q1y hsdA== X-Gm-Message-State: APjAAAU6ZNDLLWkvD9Qpjnzqvf68MoCoNGfuvDgP40LbNoRS5ygmJTwY cOVh1mRkZAW2KiBWIqwzSNQ= X-Google-Smtp-Source: APXvYqzYar7cir4nEVfsw6pDWLzHKGGrWy3yMbYTr6PHAK+wnKscoo/k7Aj37D/0aOCGiOjSrG7D/g== X-Received: by 2002:a2e:9213:: with SMTP id k19mr12089693ljg.237.1563211792709; Mon, 15 Jul 2019 10:29:52 -0700 (PDT) Received: from localhost.localdomain (ppp79-139-233-208.pppoe.spdop.ru. [79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:52 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 08/13] clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP Date: Mon, 15 Jul 2019 20:26:24 +0300 Message-Id: <20190715172629.4437-9-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The new CPUIDLE driver uses the Tegra's CLK API and that driver won't strictly depend on CONFIG_PM_SLEEP, hence add the required stubs in order to allow compiling of the new driver with the CONFIG_PM_SLEEP=n. Signed-off-by: Dmitry Osipenko --- include/linux/clk/tegra.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index b8aef62cc3f5..cf0f2cb5e109 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -108,6 +108,19 @@ static inline void tegra_cpu_clock_resume(void) tegra_cpu_car_ops->resume(); } +#else +static inline bool tegra_cpu_rail_off_ready(void) +{ + return false; +} + +static inline void tegra_cpu_clock_suspend(void) +{ +} + +static inline void tegra_cpu_clock_resume(void) +{ +} #endif extern void tegra210_xusb_pll_hw_control_enable(void); From patchwork Mon Jul 15 17:26:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132134 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Xxd5N+R1"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVt43WN6z9sNF for ; Tue, 16 Jul 2019 03:30:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731866AbfGOR35 (ORCPT ); Mon, 15 Jul 2019 13:29:57 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:44556 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731838AbfGOR35 (ORCPT ); Mon, 15 Jul 2019 13:29:57 -0400 Received: by mail-lf1-f65.google.com with SMTP id r15so6695577lfm.11; Mon, 15 Jul 2019 10:29:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rlXTyJMYpzUBstnyetLObobNUoJMGaePqJSvqyF2PiA=; b=Xxd5N+R1yuSFK2m29GZXIIIei+oP32X4nswgxWjBtlwJ9BTaBGR1PKUPdRpXlyCfu9 u7HBgp3QpifHCtoXbY07XCrmbeacfANqjjUvfBr6TCasG445AFa+M+2867HEpD9neRj2 aLNRpZfw16J1Pv8l2MUQ5sFXEdWkQ1R8Ntpd2ey1IsXjeSsSRul8SjxDmsnr7+s/NRdr tX9H0KrScgk+fAB3yqQ4fQJzFvIEKpS5hq/I0Kqepsk+V3Vv93ZvJ5MgU8PCxd21gSr4 AU6urDxd5zEDvoojDoJfDzk1Y+ieAmCN1Xt1cPMeV3PeBIOwQVo7Dy0bhq9jOXiB1nG+ WBJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rlXTyJMYpzUBstnyetLObobNUoJMGaePqJSvqyF2PiA=; b=mrj5z0O4Xqwik2K5Hh3g07ZfdbI5mgYtoAA2XM2ok4feZt/8ZydWBYyJjV1d3IFZw1 ht5erIK1xW7nG38+r+6WMmGHLFyeMcBR7autavIhmu0qU6tvazDkFz9HYHJWDM74EbuN lWJI/fyBW35CJWjVrFjCD97mWqe+L6Zs1m6iO0E1V0QPV7WD0RJ250oENPoAUWO/YjNP 8K7s7fOaIlRooBEm1r/kI3fHbJQ9EmWssYwoYPstRilMrv8KcNms4DMLjcmkn81o7pZq W6law1dwz3lSQYHu4apQv3T6D/sqnn9dOIDvmczuYGqIubwBeqd28SHe2LdJjJFUbUDG jfGA== X-Gm-Message-State: APjAAAUHj31AVb7Hhty4lQwQGlF9EN1uAmINEYrhhU3c0qSzu82zZK6a qUWwlLzg/f0B1Q4ieKmyGrGmAtMG X-Google-Smtp-Source: APXvYqzeVvr5rcFgYQUGHViEgd49oF3olYH6OA8job4Itt/VkiqMrXV5Lmnpcz5gbGli7GhoWkVbig== X-Received: by 2002:ac2:5c1d:: with SMTP id r29mr11100976lfp.72.1563211793736; Mon, 15 Jul 2019 10:29:53 -0700 (PDT) Received: from localhost.localdomain (ppp79-139-233-208.pppoe.spdop.ru. [79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:53 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 09/13] cpuidle: Introduce unified driver for NVIDIA Tegra SoCs Date: Mon, 15 Jul 2019 20:26:25 +0300 Message-Id: <20190715172629.4437-10-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The new driver is based on the old CPU Idle drivers that are removed now from arm/arch/mach-tegra/ directory. Those removed drivers were reworked and squashed into a single unified driver that covers multiple hardware generations, starting from Tegra20 and ending with Tegra124. The new driver takes slightly different approach in regards to handling of CC6 state by parking secondary CPUs explicitly into offline state, in contrast to CPUs suspend/resume racing that old Tegra20 had. The new driver doesn't ignore any possible errors and provides useful diagnostics information in a case of failure. Signed-off-by: Dmitry Osipenko --- drivers/cpuidle/Kconfig.arm | 8 + drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-tegra.c | 349 ++++++++++++++++++++++++++++++++ include/soc/tegra/cpuidle.h | 4 + 4 files changed, 362 insertions(+) create mode 100644 drivers/cpuidle/cpuidle-tegra.c diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 48cb3d4bb7d1..d90861361f1d 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -76,3 +76,11 @@ config ARM_MVEBU_V7_CPUIDLE depends on ARCH_MVEBU && !ARM64 help Select this to enable cpuidle on Armada 370, 38x and XP processors. + +config ARM_TEGRA_CPUIDLE + bool "CPU Idle Driver for NVIDIA Tegra SoCs" + depends on ARCH_TEGRA && !ARM64 + select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP + select ARM_CPU_SUSPEND + help + Select this to enable cpuidle for NVIDIA Tegra20/30/114/124 SoCs. diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 9d7176cee3d3..470d17fa8746 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o obj-$(CONFIG_ARM_CPUIDLE) += cpuidle-arm.o +obj-$(CONFIG_ARM_TEGRA_CPUIDLE) += cpuidle-tegra.o ############################################################################### # MIPS drivers diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c new file mode 100644 index 000000000000..2ab293343069 --- /dev/null +++ b/drivers/cpuidle/cpuidle-tegra.c @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * CPU idle driver for Tegra CPUs + * + * Copyright (c) 2010-2013, NVIDIA Corporation. + * Copyright (c) 2011 Google, Inc. + * Author: Colin Cross + * Gary King + * + * Rework for 3.3 by Peter De Schrijver + * + * Tegra20/124 driver unification by Dmitry Osipenko + */ + +#define pr_fmt(fmt) "tegra-cpuidle: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define TEGRA_C1 0 +#define TEGRA_C7 1 +#define TEGRA_CC6 2 + +static atomic_t tegra_idle_barrier; +static atomic_t tegra_abort_flag; + +static inline bool tegra_cpuidle_using_firmware(void) +{ + return firmware_ops->prepare_idle && firmware_ops->do_idle; +} + +static void tegra_cpuidle_report_cpus_state(void) +{ + unsigned int cpu, lcpu; + + for_each_cpu(lcpu, cpu_possible_mask) { + cpu = cpu_logical_map(lcpu); + + pr_err("cpu%u: online=%d flowctrl_csr=0x%08x\n", + cpu, cpu_online(lcpu), flowctrl_read_cpu_csr(cpu)); + } +} + +static int tegra_cpuidle_wait_for_secondary_cpus_parking(void) +{ + ktime_t timeout = ktime_add_ms(ktime_get(), 100); + + /* + * The primary CPU0 core shall wait for the secondaries shutdown + * in order to power-off CPU's cluster safely. The timeout value + * depends on the current CPU frequency, it takes about 40-150us + * in average and over 1000us in a worst case scenario. + */ + do { + if (tegra_cpu_rail_off_ready()) + return 0; + + } while (ktime_compare(ktime_get(), timeout) < 0); + + /* postmortem */ + tegra_cpuidle_report_cpus_state(); + + return -ETIMEDOUT; +} + +static void tegra_cpuidle_unpark_secondary_cpus(void) +{ + unsigned int cpu, lcpu; + + for_each_cpu(lcpu, cpu_online_mask) { + cpu = cpu_logical_map(lcpu); + + if (cpu > 0) { + tegra_enable_cpu_clock(cpu); + tegra_cpu_out_of_reset(cpu); + flowctrl_write_cpu_halt(cpu, 0); + } + } +} + +static int tegra_cpuidle_cc6_enter(unsigned int cpu) +{ + int err; + + if (cpu > 0) { + err = cpu_suspend(cpu, tegra_pm_park_secondary_cpu); + } else { + err = tegra_cpuidle_wait_for_secondary_cpus_parking(); + if (err) + return err; + + err = tegra_pm_enter_lp2(); + + tegra_cpuidle_unpark_secondary_cpus(); + } + + return err; +} + +static int tegra_cpuidle_c7_enter(void) +{ + int err; + + if (tegra_cpuidle_using_firmware()) { + err = call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2); + if (err) + return err; + + return call_firmware_op(do_idle, 0); + } + + return cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); +} + +static int tegra_cpuidle_coupled_barrier(struct cpuidle_device *dev) +{ + if (tegra_pending_sgi()) { + /* + * CPU got local interrupt that will be lost after GIC's + * shutdown because GIC driver doesn't save/restore the + * pending SGI state across CPU cluster PM. Abort and retry + * next time. + */ + atomic_set(&tegra_abort_flag, 1); + } + + cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier); + + if (atomic_read(&tegra_abort_flag)) { + cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier); + atomic_set(&tegra_abort_flag, 0); + return -EINTR; + } + + return 0; +} + +static int tegra_cpuidle_state_enter(struct cpuidle_device *dev, + int index, unsigned int cpu) +{ + int err; + + /* + * CC6 state is the "CPU cluster power-off" state. In order to + * enter this state, at first the secondary CPU cores need to be + * parked into offline mode, then the last CPU should clean out + * remaining dirty cache lines into DRAM and trigger Flow Controller + * logic that turns off the cluster's power domain (which includes + * CPU cores, GIC and L2 cache). + */ + if (index == TEGRA_CC6) { + err = tegra_cpuidle_coupled_barrier(dev); + if (err) + return err; + } + + local_fiq_disable(); + tegra_pm_set_cpu_in_lp2(); + cpu_pm_enter(); + + switch (index) { + case TEGRA_C7: + err = tegra_cpuidle_c7_enter(); + break; + case TEGRA_CC6: + err = tegra_cpuidle_cc6_enter(cpu); + break; + default: + err = -EINVAL; + break; + } + + cpu_pm_exit(); + tegra_pm_clear_cpu_in_lp2(); + local_fiq_enable(); + + return err; +} + +static int tegra_cpuidle_adjust_state_index(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index, unsigned int cpu) +{ + /* + * On Tegra30 CPU0 can't be power-gated while secondary CPUs + * are active because it gates the whole CPU cluster. + */ + if (cpu != 0 || index != TEGRA_C7 || tegra_get_chip_id() != TEGRA30) + return index; + + if (!IS_ENABLED(CONFIG_PM_SLEEP) || num_online_cpus() > 1) + index = TEGRA_C1; + else + index = TEGRA_CC6; + + if (drv->states[index].disabled || dev->states_usage[index].disable) + index = -1; + + return index; +} + +static int tegra_cpuidle_enter(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + unsigned int cpu = cpu_logical_map(dev->cpu); + int err; + + index = tegra_cpuidle_adjust_state_index(dev, drv, index, cpu); + if (index < 0) + return index; + + if (index == TEGRA_C1) + err = arm_cpuidle_simple_enter(dev, drv, index); + else + err = tegra_cpuidle_state_enter(dev, index, cpu); + + if (err && (err != -EINTR || index != TEGRA_CC6)) + pr_err_once("failed to enter state %d err: %d\n", index, err); + + return err ? -1 : index; +} + +static void tegra114_enter_s2idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + tegra_cpuidle_enter(dev, drv, index); +} + +static struct cpuidle_driver tegra_idle_driver = { + .name = "tegra_idle", + .states = { + [TEGRA_C1] = ARM_CPUIDLE_WFI_STATE_PWR(600), + [TEGRA_C7] = { + .enter = tegra_cpuidle_enter, + .exit_latency = 2000, + .target_residency = 2200, + .power_usage = 100, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .name = "C7", + .desc = "CPU core powered off", + }, + [TEGRA_CC6] = { + .enter = tegra_cpuidle_enter, + .exit_latency = 5000, + .target_residency = 10000, + .power_usage = 0, + .flags = CPUIDLE_FLAG_TIMER_STOP | + CPUIDLE_FLAG_COUPLED, + .name = "CC6", + .desc = "CPU cluster powered off", + }, + }, + .state_count = 3, + .safe_state_index = TEGRA_C1, +}; + +/* + * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether + * they are legacy IRQs or MSI, are lost when CC6 is enabled. To work around + * this, simply disable CC6 if the PCI driver and DT node are both enabled. + */ +void tegra_cpuidle_pcie_irqs_in_use(void) +{ + if (tegra_idle_driver.states[TEGRA_CC6].disabled || + tegra_get_chip_id() != TEGRA20) + return; + + pr_info("disabling CC6 state, since PCIe IRQs are in use\n"); + tegra_idle_driver.states[TEGRA_CC6].disabled = true; +} + +static void tegra_cpuidle_setup_tegra114_c7_state(void) +{ + struct cpuidle_state *s = &tegra_idle_driver.states[TEGRA_C7]; + + s->enter_s2idle = tegra114_enter_s2idle; + s->target_residency = 1000; + s->exit_latency = 500; +} + +static int tegra_cpuidle_probe(struct platform_device *pdev) +{ + /* + * Required suspend-resume functionality, which is provided by the + * Tegra-arch core and PMC driver, is unavailable if PM-sleep option + * is disabled. + */ + if (!IS_ENABLED(CONFIG_PM_SLEEP)) { + if (!tegra_cpuidle_using_firmware()) + tegra_idle_driver.states[TEGRA_C7].disabled = true; + + tegra_idle_driver.states[TEGRA_CC6].disabled = true; + } + + /* + * Generic WFI state (also known as C1 or LP3) and the coupled CPU + * cluster power-off (CC6 or LP2) states are common for all Tegra SoCs. + */ + switch (tegra_get_chip_id()) { + case TEGRA20: + /* Tegra20 isn't capable to power-off individual CPU cores */ + tegra_idle_driver.states[TEGRA_C7].disabled = true; + break; + case TEGRA30: + tegra_idle_driver.states[TEGRA_CC6].disabled = true; + break; + case TEGRA114: + case TEGRA124: + tegra_cpuidle_setup_tegra114_c7_state(); + + /* coupled CC6 (LP2) state isn't implemented yet */ + tegra_idle_driver.states[TEGRA_CC6].disabled = true; + break; + default: + return -EINVAL; + } + + return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); +} + +static struct platform_driver tegra_cpuidle_driver = { + .probe = tegra_cpuidle_probe, + .driver = { + .name = "tegra-cpuidle", + }, +}; +builtin_platform_driver(tegra_cpuidle_driver); diff --git a/include/soc/tegra/cpuidle.h b/include/soc/tegra/cpuidle.h index f758808342b6..5665975015d8 100644 --- a/include/soc/tegra/cpuidle.h +++ b/include/soc/tegra/cpuidle.h @@ -6,8 +6,12 @@ #ifndef __SOC_TEGRA_CPUIDLE_H__ #define __SOC_TEGRA_CPUIDLE_H__ +#ifdef CONFIG_ARM_TEGRA_CPUIDLE +void tegra_cpuidle_pcie_irqs_in_use(void); +#else static inline void tegra_cpuidle_pcie_irqs_in_use(void) { } +#endif #endif /* __SOC_TEGRA_CPUIDLE_H__ */ From patchwork Mon Jul 15 17:26:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132133 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HhW3v/ci"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVt34CL7z9sMr for ; Tue, 16 Jul 2019 03:30:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731876AbfGOR36 (ORCPT ); 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[79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:54 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 10/13] cpuidle: tegra: Support CPU cluster power-down state on Tegra30 Date: Mon, 15 Jul 2019 20:26:26 +0300 Message-Id: <20190715172629.4437-11-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The new CPU Idle driver has all necessary features in order to allow the deepest idling state on Tegra30 SoC where the whole CPU cluster is power-gated using the coupled idle state. Note that outer_disable() now need to be invoked directly since it produces erroneous warning message about secondary CPUs being online because it doesn't know that secondaries are turned off at that point by the cpuidle driver. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 4 ++-- drivers/cpuidle/cpuidle-tegra.c | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 7d9ef26e52a7..1845b87a7cf3 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -146,8 +146,8 @@ static int tegra_sleep_cpu(unsigned long v2p) * if any of secondary CPU's is online and this is the LP2-idle * code-path only for Tegra20/30. */ - if (trusted_foundations_registered()) - outer_disable(); + if (trusted_foundations_registered() && outer_cache.disable) + outer_cache.disable(); /* * Note that besides of setting up CPU reset vector this firmware diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c index 2ab293343069..ea084a0aa448 100644 --- a/drivers/cpuidle/cpuidle-tegra.c +++ b/drivers/cpuidle/cpuidle-tegra.c @@ -324,7 +324,6 @@ static int tegra_cpuidle_probe(struct platform_device *pdev) tegra_idle_driver.states[TEGRA_C7].disabled = true; break; case TEGRA30: - tegra_idle_driver.states[TEGRA_CC6].disabled = true; break; case TEGRA114: case TEGRA124: From patchwork Mon Jul 15 17:26:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132132 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="GHWqqrP8"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVt20sY5z9sMQ for ; Tue, 16 Jul 2019 03:30:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731893AbfGOR36 (ORCPT ); Mon, 15 Jul 2019 13:29:58 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:44303 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731859AbfGOR36 (ORCPT ); Mon, 15 Jul 2019 13:29:58 -0400 Received: by mail-lj1-f193.google.com with SMTP id k18so17091333ljc.11; Mon, 15 Jul 2019 10:29:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ez/DtEbZm91hvKH3/uYPobJLTWojYBqiK7N01oWP7xA=; b=GHWqqrP8MGo5usVZkesx/S/t3wUr6lK7Nh0zI9P8FCe6cwHfY1ofjS8rd2gkTNi1AB Xm6F8B6VWn52y6oG1ygaM2YdtR3QGK2RXJfjHVrjwHu/sFWreOak530bov65iaoUMLJu KBGIvqd4yq9Q5zRRzj7+uQc4gyLN471CLYZMIsExyTXS92hIwYhZqNYelURn1kTt7bVE MWZG8K6dRRASsmhu+fBv5+eUBn8gSjvRsHDTF73myDkOcRkmgwKFkDwXxYCnqrRmCt8c 3v587cKJL0VM2o8h8pgRbifzPatUeq4IVvF/9NClJtjb+38k1SWH+v85RQj2zvDGAry6 167Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ez/DtEbZm91hvKH3/uYPobJLTWojYBqiK7N01oWP7xA=; b=d/v6XSQoCkGGgVDL7UdJy/4IG6DWXWXWZUaONWJpWlsk9EIo3o3rFixHtTG8Sy8fiS hMJk4PMtdTUCAuQS4SROukelY3HAEPabM1s7oDSYPb1xv4vAsRDsvlPUuHFlct8t0p1f HNlpjKhY44WPkPknKtsXFjI+TKl4iJX3YSiFDSYro08N5922iZioXcNZ5jdUixwGcxqI RO3Ci3/7jXgYG9DCNPBCOfs24eNQ/i0lfSvcwsohSIZxpKeAcfJ6ydwv3cJ3PaDLm8U4 TtEIZkxuTMCFpD1XgylpSOemeiBXt42m09ovIdOA6j0/M7uJB7OOHHeHvelOTt/Fl+27 XRTg== X-Gm-Message-State: APjAAAVo78/2zJPNSAqeyYWW4tVjPOdnPiAeUeDTFu8+i4v/bE2i6oZr UEOUxD2/YjLdyEJd2RaAQuI= X-Google-Smtp-Source: APXvYqyDNuo3sjvpZZ1PrzvsKvNjDFwHsZyeZMQ0175G+DbtEMIV/KWgUicezlDGR98tOBvk4oyIHg== X-Received: by 2002:a2e:9ec9:: with SMTP id h9mr14042084ljk.90.1563211795641; Mon, 15 Jul 2019 10:29:55 -0700 (PDT) Received: from localhost.localdomain (ppp79-139-233-208.pppoe.spdop.ru. [79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:55 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 11/13] ARM: tegra: Create simple platform device for cpuidle driver Date: Mon, 15 Jul 2019 20:26:27 +0300 Message-Id: <20190715172629.4437-12-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The new CPUIDLE driver now is a proper platform driver, hence it needs a platform device in order to be functional. Register the platform device, like we do that for the CPUFreq driver. Note that on some Tegra114(124) devices PSCI may be used for the CPU hotplugging and CPUIDLE driver doesn't support that case, thus CPUIDLE device won't be registered if PCSI presents. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index d9237769a37c..f1ce2857a251 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include "board.h" @@ -92,6 +93,9 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("nvidia,tegra20")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available()) + platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { From patchwork Mon Jul 15 17:26:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132128 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sWQFfx6y"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVsP0bnFz9sNH for ; Tue, 16 Jul 2019 03:30:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731903AbfGOR37 (ORCPT ); Mon, 15 Jul 2019 13:29:59 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:43458 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731863AbfGOR37 (ORCPT ); Mon, 15 Jul 2019 13:29:59 -0400 Received: by mail-lj1-f194.google.com with SMTP id 16so17082588ljv.10; Mon, 15 Jul 2019 10:29:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3Bk1blV5oQEyQV3BicG+2hmfkOduACJXlcdjcBUfd1g=; b=sWQFfx6ybwZg4ljFXMWw4o2jX6LNSL0/W1n31kmg0FMtfIyaMU4C1Egzndl25QsslE kC/3dUiDm+ZMFR6g/H8EoL6EipSapfRtvuV8gCk9WIG3RUFvtJEAdlQuaWYXrCy7eomA MSnivkTYb8lXi7p8Z2RVY1MyxzmINqnX0lAo1RyljM9YlbMJgypup9wD3OAipwJpUdq+ TfPBT95d+YBoKB+jM/oQ5S3iG/VXGOoplCHa1RprFlwKQsz7rgNDNRe+WrZTae6Rp/x/ W0ayR8wh5Oliu2WyWRKNDD8PxmF6YsCTjSR8mz5XNRCWP7PmoFkoEhOzLU8Q8dPIINzp 1ZTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3Bk1blV5oQEyQV3BicG+2hmfkOduACJXlcdjcBUfd1g=; b=b4sVJfG8Et9+va5kfFr1ao0RWir8T5xaUWv5VzgNoInofucTmJHc3Km7jbbvzI1FrW UpUeURJRKDxINNoxz2NGmYWQyIr/DDTiGHQJcuvPC8TaxEgdvAXVYJkKx1gThfZaKPK2 +9S/0mSHgf5g4YAT5d/vSJ+B/dWsnxAhZdPiF0MYKq7ODjmZUTSztNe+tufqkYmOia9J xZdbGyI17f7EW8S609Z2vFSqPlg1VsVytfU5yI1DuQTnYj3w9thy69CNNtRegv2VZH+4 J9W0kyD3bfwQhk+SFxmOgdYdX9mKLkgSfPOUuf7Tq0fanRxJbKYikeI6Nvp/x9pF/2uS DGUg== X-Gm-Message-State: APjAAAUiHXUb5D2DONHFE9+rKJRAOH+GBVNWKhc0x1ESg890r6ScYp0K tgByhYGCCmAq9B+o6WO3/r8= X-Google-Smtp-Source: APXvYqzOUT6VQLLbYkitbj/O7ZOWVmn9kFOcBjnh1ThsbpBMAGKLhgxuIvnkzQbjKrIzTSTXw2BksA== X-Received: by 2002:a2e:8e90:: with SMTP id z16mr14783618ljk.4.1563211796650; Mon, 15 Jul 2019 10:29:56 -0700 (PDT) Received: from localhost.localdomain (ppp79-139-233-208.pppoe.spdop.ru. [79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:56 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 12/13] ARM: multi_v7_defconfig: Enable Tegra cpuidle driver Date: Mon, 15 Jul 2019 20:26:28 +0300 Message-Id: <20190715172629.4437-13-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and it is now a proper platform driver. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 6a40bc2ef271..2c0fc7968c42 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -107,6 +107,7 @@ CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_ARM_ZYNQ_CPUIDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y +CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_KERNEL_MODE_NEON=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_TRUSTED_FOUNDATIONS=y From patchwork Mon Jul 15 17:26:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1132131 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cfsQfLg6"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45nVsx2ZXlz9sLt for ; Tue, 16 Jul 2019 03:30:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732032AbfGORa1 (ORCPT ); Mon, 15 Jul 2019 13:30:27 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:38938 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731881AbfGOR37 (ORCPT ); Mon, 15 Jul 2019 13:29:59 -0400 Received: by mail-lf1-f65.google.com with SMTP id v85so11565319lfa.6; Mon, 15 Jul 2019 10:29:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9sbsaF7E0TrDeiv6pReKgq+pMBX4p8SmM9uYJr655g4=; b=cfsQfLg6uXhCsDhKrfTKfo6Sq0gES7tIIKRYeUMeQPc11O2FFfbXTX6aotF8r2KSpj bQGuzhwGyMU7Klx8gsdATDAqcdQjnAAhfH0hkhBOwHt75sD9G+l41xQkUfmBLkrH2o9V 7n+UNcnfa82X9rlHaRJTdDOZvrNPMv0ov6LNFSCRcqWNyYuYq+sDQ35md1Ra551cVtld yNGxmdoZTQFGxBEfRFvXBBN+Egl1SIDZJ1Jub+HSvJ/qRyHcpU8uWAltA2ZvO/k6ZpFV QgVWeT2LsIMU3PRFU1KXgIVrQOI3bnbuZDYTtEl0Km55ppFLwKHsHN+Nv6H/GTFGdxRv jmkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9sbsaF7E0TrDeiv6pReKgq+pMBX4p8SmM9uYJr655g4=; b=ucLLKEDi/icdTPqUXXMdwE+kUc/Ll3XPXhgasOll6fnHUyfvs1QrF8SSaI7NVX4dBc NhJAKca9rUorbK0tves36h2TKhEI5rM+mKaNrJqKSdcEXEmfUI0Sy/NnmMSIlbaTxeIN zhsGIB/nPRfhthn7t8XNhApPNmaxNhtXJW34bv7aqOevcnVera3a8+3rFAU2XkxYIil/ WmKkNumEG6n7RiQAlLVQkoO0mDz6/GMltlMvXuxWeQ2QFq03pu5UmzbinPY7vTK8Ag8L 2NArSZW5X1/yeVg63ZDeu5zwZBlXySrYb89Ghm8cxrp3LUWz7iiOs8cK0KP2YirE3qC2 sG/Q== X-Gm-Message-State: APjAAAVPOZzOfRFO4jTo1IdQDQYOxwCVp7x/Ldo417DX4gJGKJIyNvco 1Hb+gWQfFj+Yu8mQg1UCpXA= X-Google-Smtp-Source: APXvYqzh4mCzsVutjVh3P6kwpNAC6f14uhzoqQsZ8erj79ZbfueASsY+KQ7A1LZug29vsoABB/S3DA== X-Received: by 2002:a19:8c08:: with SMTP id o8mr11940682lfd.57.1563211797598; Mon, 15 Jul 2019 10:29:57 -0700 (PDT) Received: from localhost.localdomain (ppp79-139-233-208.pppoe.spdop.ru. [79.139.233.208]) by smtp.gmail.com with ESMTPSA id b17sm3248765ljf.34.2019.07.15.10.29.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 10:29:57 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 13/13] ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig Date: Mon, 15 Jul 2019 20:26:29 +0300 Message-Id: <20190715172629.4437-14-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190715172629.4437-1-digetx@gmail.com> References: <20190715172629.4437-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and it is now a proper platform driver. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/tegra_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 8f5c6a5b444c..9a2f11a780a8 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -25,6 +25,7 @@ CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y +CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_TRUSTED_FOUNDATIONS=y