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Mon, 15 Jul 2019 12:44:33 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, a.hajda@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba Subject: [PATCH v1 01/50] clk: samsung: add new IDs for Exynos5420 clocks Date: Mon, 15 Jul 2019 14:43:28 +0200 Message-Id: <20190715124417.4787-2-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSfyzUYRzHPfe97w/m6uk0nhDrWq3ICaVnq8SqddXWWv+0aaaT705x6L6I ajlFxYhUokXkGrsoJDu/86POSn5kcUllu7a2/Ap3NZspX1/Vf+/P+/P6vD+fPXsYQmognZnT 0XGsJloZJaPsxHWv5nq8/OK3hGwt2IyHn/SQuDr/KYmHLN9I/KBzscw2jxG4t7eKxm8vj9N4 WOuKa8yDJJ7O/EzigYb7FM7vbRHhys5PNH401C/C/a/3448p5RROa+6kccf4NRIvDFaLAx0U FUUVQDFlSqMVNfp0SvFMl6xom2wSKW7U6oFitsbtKB1styucjTqdwGq8A07aRRQaG+nYLysT p5730lrQLMkAtgyC21DHgI7IAHaMFJYDNPLwNykUFoBy8lMAT0nhLEANJTEZgFmayHmpFuwy gH7MMf/46pwSMc9QUI4M+rM8sxrqAOqcC+MZAn4Qoaav9STfcIAHUcXA2FK+GG5Apu40itcS GIA6Gidp4Tp39LjqBcFrW7gHzeX1UYL/jkb3LNuFe/Yhs9ZTsB3Qd2Pt8qgrenMrUyxoDmmz SoCgLyJzduEysxN1GPtJPoaAm9HTBm/BDkJpqQ20kL4CmSZW8TaxKHPr7hKCLUHXr0oFehOq zewTCdoRlVXkLYcrUJHOSgmPkwuQ7uYVkAPc7/1fVgyAHjix8ZxaxXJ+0ew5OadUc/HRKvmp GHUNWPxPbxaMVgNomQ9rB5ABMntJYLhniJRUJnBJ6naAGEK2WrLbumhJwpVJ51lNTKgmPorl 2oELI5Y5SS7YjJ6QQpUyjo1k2VhW87crYmydtaCVue1LkjbJbmsmg0SqjQWmc5Fk99SOdLh3 yP9QRleph1Xre6Vq2vfw/kujvgb5+zuh1mCzrPiY3J5q/ekWI0/3oVwCVIb5iXLv8MS4emwp mH99BGYNzZTq21xStXln1o8cSjj+a5tTv6MJru2yFBzwj53pg03rWC+jdlclJRNzEUofD0LD Kf8Aiv/+40sDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHIsWRmVeSWpSXmKPExsVy+t/xe7pGpTqxBgsm8FncWneO1WLjjPWs Fte/PGe1mH8EyO1//JrZ4vz5DewWZ5vesFvcapCx2PT4GqvFx557rBaXd81hs5hxfh+Txdoj d9ktll6/yGRx8ZSrxe3GFWwWrXuPsFscftPOavHv2kYWB2GPNfPWMHq8v9HK7rFpVSebx+Yl 9R4H3+1h8ujbsorR4/MmuQD2KD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81grI1Ml fTublNSczLLUIn27BL2Mucd3sxfc5694v/U8ewPjXt4uRg4OCQETiQlHc7sYuTiEBJYySlw9 eY6pi5ETKC4mMWnfdnYIW1jiz7UuNhBbSOATo8STRzIgvWwCehI7VhWChEUEVjBKTD7hDTKH WeA1k8SRo+9YQRLCAp4Say6/ZgSxWQRUJW6caQWbwytgJ3F49zuo+fISqzccYAaxOQXsJX5O uwC1y05i8dGfTBMY+RYwMqxiFEktLc5Nzy021CtOzC0uzUvXS87P3cQIjJttx35u3sF4aWPw IUYBDkYlHl6HFO1YIdbEsuLK3EOMEhzMSiK8tl+BQrwpiZVVqUX58UWlOanFhxhNgY6ayCwl mpwPjOm8knhDU0NzC0tDc2NzYzMLJXHeDoGDMUIC6YklqdmpqQWpRTB9TBycUg2MRWd6Sqdc mHnmf+ZSnrnKm05yVfGk2TEmTJfo5/57c70Xi/vcukrX6e3fJzH4GTjJiYXMSjr4VETVP+h/ xLc7K5Z96N92aXGq0jnznE2azK+zdjlzpu7lWnbTwn1+8OQGaZlE/9+njweIv/dy2Fm7c/dr Drf6yy6/V9TaLPlV95U/R6Z9404lJZbijERDLeai4kQA1OpPBLECAAA= X-CMS-MailID: 20190715124434eucas1p273e2efaad8bc3904c6f76cc1671aeb6c X-Msg-Generator: CA X-RootMTR: 20190715124434eucas1p273e2efaad8bc3904c6f76cc1671aeb6c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190715124434eucas1p273e2efaad8bc3904c6f76cc1671aeb6c References: <20190715124417.4787-1-l.luba@partner.samsung.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There is a need of new IDs which will be used for modeling proper hierarchy in the Exynos54xx SoCs. Previous implementation rely on bootloader settings, which are not configuring properly some clocks. These IDs provide interface to set proper parents. Signed-off-by: Lukasz Luba --- include/dt-bindings/clock/exynos5420.h | 27 +++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 02d5ac469a3d..c37a28eeaf7e 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -230,6 +230,30 @@ #define CLK_MOUT_USER_MAU_EPLL 659 #define CLK_MOUT_SCLK_SPLL 660 #define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 +#define CLK_MOUT_ACLK400_WCORE 662 +#define CLK_MOUT_SCLK_DPLL 663 +#define CLK_MOUT_ACLK100_NOC 664 +#define CLK_MOUT_ACLK200_FSYS2 665 +#define CLK_MOUT_PCLK200_FSYS 666 +#define CLK_MOUT_ACLK200_FSYS 667 +#define CLK_MOUT_ACLK400_ISP 668 +#define CLK_MOUT_ACLK400_MSCL 669 +#define CLK_MOUT_SCLK_MPLL 700 +#define CLK_MOUT_ACLK266 701 +#define CLK_MOUT_UART0 702 +#define CLK_MOUT_UART1 703 +#define CLK_MOUT_UART2 704 +#define CLK_MOUT_UART3 705 +#define CLK_MOUT_SCLK_CPLL 706 +#define CLK_MOUT_PWM 707 +#define CLK_MOUT_ACLK266_G2D 708 +#define CLK_MOUT_SW_ACLK400_WCORE 709 +#define CLK_MOUT_SW_ACLK400_MSCL 710 +#define CLK_MOUT_SW_ACLK400_ISP 711 +#define CLK_MOUT_SW_ACLK266_ISP 712 +#define CLK_MOUT_USER_ACLK266_ISP 713 +#define CLK_MOUT_ACLK266_ISP 714 +#define CLK_MOUT_MMC0 715 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -264,8 +288,9 @@ #define CLK_FF_DOUT_SPLL2 797 #define CLK_DOUT_PCLK_DREX0 798 #define CLK_DOUT_PCLK_DREX1 799 +#define CLK_DOUT_ACLK266_ISP 800 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 800 +#define CLK_NR_CLKS 801 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */