From patchwork Sun Jul 14 03:53:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 1131678 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=zoho.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="hC4i2tS9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45md9l5bZ4z9sN6 for ; Sun, 14 Jul 2019 17:11:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727832AbfGNHKm (ORCPT ); Sun, 14 Jul 2019 03:10:42 -0400 Received: from sender4-pp-o95.zoho.com ([136.143.188.95]:25548 "EHLO sender4-pp-o95.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728218AbfGNHKl (ORCPT ); Sun, 14 Jul 2019 03:10:41 -0400 X-Greylist: delayed 754 seconds by postgrey-1.27 at vger.kernel.org; Sun, 14 Jul 2019 03:10:41 EDT ARC-Seal: i=1; a=rsa-sha256; t=1563087330; cv=none; d=zoho.com; s=zohoarc; b=gHfazKbY3bxTbzBwtnkG5zaen4Usc5jwgYdOlSbeTMLnZfRYWmYfozIfXmCcSrmYWXP+qEtCAFiD/EIKjyG2Azm+fn6Kxwi+M41qimgWgX7UdaEz3mP83TN9hhSbDDvWyspGUIENx2HNYcoq2RGeZSanf1tuJj1UWa9hhHetdOM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563087330; h=Cc:Date:From:In-Reply-To:Message-ID:References:Subject:To:ARC-Authentication-Results; bh=hfnVfnh/vca8VDGXpOWZyOyDkom6iR+mQuHJWBcZOjY=; b=mJw93LBVvCy8P2JCcQjyhO11ml1/SUuRdBwrz7fEbByu80HGHxGCOxQLZA2NOpOZf7TRKA4+oiJsS1C1yzcm8cFSC/gcDaY9rt3IkgCKzZjFBftPiZsjb0VOAHp8Gbw2nYgWKfqOYfkaCqDIrtJGUPlaTxnp38p9/Sv285irkvQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass header.i=zoho.com; spf=pass smtp.mailfrom=zhouyanjie@zoho.com; dmarc=pass header.from= header.from= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=zapps768; d=zoho.com; h=from:to:cc:subject:date:message-id:in-reply-to:references; b=lvp+l4RPYUJv2MqMaz/yM9GofQyG7YNGo15EHJCAN5BEoG05gnwzn2lZl0yVocIHM53h84b2SzC3 +6VNjJzcvpmjXBTy/VFrMm3JdKVrJlHrzuPqQ+GL5pVWN0jx8pns DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1563087330; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; l=1709; bh=hfnVfnh/vca8VDGXpOWZyOyDkom6iR+mQuHJWBcZOjY=; b=hC4i2tS9Pvopxxl1QUFjQwgEhXRIuxk/bFv4K9+zjtzz4VPFEoc0j7suK6/4bXXB 7+gx1Fi5HpcYX3bd3j4Rx5gsENOpQ3OXACJMlqg5uOT7Xq5QCmnCa6HRMvxIfCQVX83 wWvgtcpGMV6k6MRNyQbsP9RjsUP8wwth21vtOLdc= Received: from zhouyanjie-virtual-machine.localdomain (125.71.5.36 [125.71.5.36]) by mx.zohomail.com with SMTPS id 1563087330429598.9787410686005; Sat, 13 Jul 2019 23:55:30 -0700 (PDT) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, paul.burton@mips.com, linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH 1/6] dt-bindings: pinctrl: Add JZ4760 and JZ4760B bindings. Date: Sun, 14 Jul 2019 11:53:51 +0800 Message-Id: <1563076436-5338-2-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> References: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the pinctrl bindings for the JZ4760 Soc and the JZ4760B Soc from Ingenic. Signed-off-by: Zhou Yanjie --- Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt index af20b0e..a80ff68 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt @@ -11,8 +11,8 @@ naming scheme "PxN" where x is a character identifying the GPIO port with which the pin is associated and N is an integer from 0 to 31 identifying the pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to -PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a -total of 192 pins. +PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 contains 6 +GPIO ports, PA to PF, for a total of 192 pins. Required properties: @@ -21,6 +21,8 @@ Required properties: - compatible: One of: - "ingenic,jz4740-pinctrl" - "ingenic,jz4725b-pinctrl" + - "ingenic,jz4760-pinctrl" + - "ingenic,jz4760b-pinctrl" - "ingenic,jz4770-pinctrl" - "ingenic,jz4780-pinctrl" - reg: Address range of the pinctrl registers. @@ -31,6 +33,7 @@ Required properties for sub-nodes (GPIO chips): - compatible: Must contain one of: - "ingenic,jz4740-gpio" + - "ingenic,jz4760-gpio" - "ingenic,jz4770-gpio" - "ingenic,jz4780-gpio" - reg: The GPIO bank number. From patchwork Sun Jul 14 03:53:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 1131680 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=zoho.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="iCFIjcCC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45mdB82p2dz9sND for ; Sun, 14 Jul 2019 17:11:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728268AbfGNHLQ (ORCPT ); Sun, 14 Jul 2019 03:11:16 -0400 Received: from sender4-pp-o95.zoho.com ([136.143.188.95]:25555 "EHLO sender4-pp-o95.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728257AbfGNHLP (ORCPT ); Sun, 14 Jul 2019 03:11:15 -0400 ARC-Seal: i=1; a=rsa-sha256; t=1563087358; cv=none; d=zoho.com; s=zohoarc; b=PajdWAL9ZE2X23uDLQTFKwssBHlYH9Nne+I5nN7QwVYjUtvNN1hp7eBeyqPt08L3tBVoAJKPKX4ImhD1bYxMojX7LhlUn1/2wM44ng3gxll0ptGjxWHbtsGZGjkA2knQY/62HhZGOecL077T2/qZ48Ri3s8Z2tLD4eOqc2OZFc8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563087358; h=Cc:Date:From:In-Reply-To:Message-ID:References:Subject:To:ARC-Authentication-Results; bh=RJB7rgYbnLJcwb1mEBskcRFwMuNEbU0C07jWNYI1Gj4=; b=Ouf06N9Um4TeM1qT4+yjfIZC+DiNQIA+kJxMz47tgMx7QNHhBPedlC1didc8SFwyux+dXuoW6cYbEwUPnzQxtVI7hsM445kZCPaJD+/oU6beO2RxgLIJfhw3FLcui4XgiHdqcQCXaanmBtFmNfu53Ib8Cf9lU4kMLucbH8frIdI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass header.i=zoho.com; spf=pass smtp.mailfrom=zhouyanjie@zoho.com; dmarc=pass header.from= header.from= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=zapps768; d=zoho.com; h=from:to:cc:subject:date:message-id:in-reply-to:references; b=EkAHSOKf1GKVjDz96NvCI5aDQdXhYUcu7ZHpaMVtHH/X9cZ0pv3FEXIMDPncqPvFW1gi33AM1MWh LQYEFdKjrej0KYzXBRaNfV5e5rwCsX+1yehyRLS0FpxaR18br3Fy DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1563087358; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; l=21508; bh=RJB7rgYbnLJcwb1mEBskcRFwMuNEbU0C07jWNYI1Gj4=; b=iCFIjcCCR0TtvZbwJXC+/99Ydcw4A0H+SSqDvIki5MhpY8OvXovNN5p3EDY4cFuU O6mBjYDiUe9tNlvjuqIY504cqny/Aw41lamgbgM2meoXuL+9aTDMqPWa5GsD5gVWQoj 6W3S54LYJ4bcVRajZ/vaYdoEyiLj6k8kIIk2l5O0= Received: from zhouyanjie-virtual-machine.localdomain (125.71.5.36 [125.71.5.36]) by mx.zohomail.com with SMTPS id 1563087357079200.0927789191004; Sat, 13 Jul 2019 23:55:57 -0700 (PDT) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, paul.burton@mips.com, linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH 2/6] pinctrl: Ingenic: Add pinctrl driver for JZ4760 and JZ4760B. Date: Sun, 14 Jul 2019 11:53:52 +0800 Message-Id: <1563076436-5338-3-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> References: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add support for probing the pinctrl-ingenic driver on the JZ4760 Soc and the JZ4760B Soc from Ingenic. Signed-off-by: Zhou Yanjie --- drivers/pinctrl/pinctrl-ingenic.c | 336 ++++++++++++++++++++++++++++++++++---- 1 file changed, 305 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index c8ef3b9..ec61b083 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -35,11 +35,11 @@ #define JZ4740_GPIO_TRIG 0x70 #define JZ4740_GPIO_FLAG 0x80 -#define JZ4770_GPIO_INT 0x10 -#define JZ4770_GPIO_PAT1 0x30 -#define JZ4770_GPIO_PAT0 0x40 -#define JZ4770_GPIO_FLAG 0x50 -#define JZ4770_GPIO_PEN 0x70 +#define JZ4760_GPIO_INT 0x10 +#define JZ4760_GPIO_PAT1 0x30 +#define JZ4760_GPIO_PAT0 0x40 +#define JZ4760_GPIO_FLAG 0x50 +#define JZ4760_GPIO_PEN 0x70 #define REG_SET(x) ((x) + 0x4) #define REG_CLEAR(x) ((x) + 0x8) @@ -49,6 +49,8 @@ enum jz_version { ID_JZ4740, ID_JZ4725B, + ID_JZ4760, + ID_JZ4760B, ID_JZ4770, ID_JZ4780, }; @@ -338,6 +340,269 @@ static const struct ingenic_chip_info jz4725b_chip_info = { .pull_downs = jz4740_pull_downs, }; +static const u32 jz4760_pull_ups[6] = { + 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, +}; + +static const u32 jz4760_pull_downs[6] = { + 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, +}; + +static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; +static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; +static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; +static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; +static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; +static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; +static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; +static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; +static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; +static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; +static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; +static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; +static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; +static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; +static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; +static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; +static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; +static int jz4760_nemc_8bit_data_pins[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, +}; +static int jz4760_nemc_16bit_data_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, +}; +static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; +static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; +static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; +static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; +static int jz4760_nemc_wait_pins[] = { 0x1b, }; +static int jz4760_nemc_cs1_pins[] = { 0x15, }; +static int jz4760_nemc_cs2_pins[] = { 0x16, }; +static int jz4760_nemc_cs3_pins[] = { 0x17, }; +static int jz4760_nemc_cs4_pins[] = { 0x18, }; +static int jz4760_nemc_cs5_pins[] = { 0x19, }; +static int jz4760_nemc_cs6_pins[] = { 0x1a, }; +static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; +static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; +static int jz4760_cim_pins[] = { + 0x26, 0x27, 0x28, 0x29, + 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, +}; +static int jz4760_lcd_24bit_pins[] = { + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x58, 0x59, 0x5a, 0x5b, +}; +static int jz4760_pwm_pwm0_pins[] = { 0x80, }; +static int jz4760_pwm_pwm1_pins[] = { 0x81, }; +static int jz4760_pwm_pwm2_pins[] = { 0x82, }; +static int jz4760_pwm_pwm3_pins[] = { 0x83, }; +static int jz4760_pwm_pwm4_pins[] = { 0x84, }; +static int jz4760_pwm_pwm5_pins[] = { 0x85, }; +static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; +static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; + +static int jz4760_uart0_data_funcs[] = { 0, 0, }; +static int jz4760_uart0_hwflow_funcs[] = { 0, 0, }; +static int jz4760_uart1_data_funcs[] = { 0, 0, }; +static int jz4760_uart1_hwflow_funcs[] = { 0, 0, }; +static int jz4760_uart2_data_funcs[] = { 0, 0, }; +static int jz4760_uart2_hwflow_funcs[] = { 0, 0, }; +static int jz4760_uart3_data_funcs[] = { 0, 1, }; +static int jz4760_uart3_hwflow_funcs[] = { 0, 0, }; +static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; +static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; +static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; +static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; +static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; +static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; +static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; +static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; +static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; +static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, }; +static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, }; +static int jz4760_nemc_rd_we_funcs[] = { 0, 0, }; +static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, }; +static int jz4760_nemc_wait_funcs[] = { 0, }; +static int jz4760_nemc_cs1_funcs[] = { 0, }; +static int jz4760_nemc_cs2_funcs[] = { 0, }; +static int jz4760_nemc_cs3_funcs[] = { 0, }; +static int jz4760_nemc_cs4_funcs[] = { 0, }; +static int jz4760_nemc_cs5_funcs[] = { 0, }; +static int jz4760_nemc_cs6_funcs[] = { 0, }; +static int jz4760_i2c0_funcs[] = { 0, 0, }; +static int jz4760_i2c1_funcs[] = { 0, 0, }; +static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; +static int jz4760_lcd_24bit_funcs[] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, +}; +static int jz4760_pwm_pwm0_funcs[] = { 0, }; +static int jz4760_pwm_pwm1_funcs[] = { 0, }; +static int jz4760_pwm_pwm2_funcs[] = { 0, }; +static int jz4760_pwm_pwm3_funcs[] = { 0, }; +static int jz4760_pwm_pwm4_funcs[] = { 0, }; +static int jz4760_pwm_pwm5_funcs[] = { 0, }; +static int jz4760_pwm_pwm6_funcs[] = { 0, }; +static int jz4760_pwm_pwm7_funcs[] = { 0, }; + +static const struct group_desc jz4760_groups[] = { + INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data), + INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow), + INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data), + INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow), + INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data), + INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow), + INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data), + INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow), + INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a), + INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a), + INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e), + INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e), + INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e), + INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d), + INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d), + INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e), + INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e), + INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e), + INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b), + INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b), + INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e), + INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e), + INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e), + INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data), + INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data), + INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale), + INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr), + INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we), + INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe), + INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait), + INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1), + INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2), + INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3), + INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4), + INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5), + INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6), + INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0), + INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1), + INGENIC_PIN_GROUP("cim-data", jz4760_cim), + INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit), + { "lcd-no-pins", }, + INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0), + INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1), + INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2), + INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3), + INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4), + INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5), + INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6), + INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7), +}; + +static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; +static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; +static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; +static const char *jz4760_mmc0_groups[] = { + "mmc0-1bit-a", "mmc0-4bit-a", + "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", +}; +static const char *jz4760_mmc1_groups[] = { + "mmc1-1bit-d", "mmc1-4bit-d", + "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", +}; +static const char *jz4760_mmc2_groups[] = { + "mmc2-1bit-b", "mmc2-4bit-b", + "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", +}; +static const char *jz4760_nemc_groups[] = { + "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", + "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", +}; +static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; +static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; +static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; +static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; +static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; +static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; +static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; +static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; +static const char *jz4760_cim_groups[] = { "cim-data", }; +static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; +static const char *jz4760_pwm0_groups[] = { "pwm0", }; +static const char *jz4760_pwm1_groups[] = { "pwm1", }; +static const char *jz4760_pwm2_groups[] = { "pwm2", }; +static const char *jz4760_pwm3_groups[] = { "pwm3", }; +static const char *jz4760_pwm4_groups[] = { "pwm4", }; +static const char *jz4760_pwm5_groups[] = { "pwm5", }; +static const char *jz4760_pwm6_groups[] = { "pwm6", }; +static const char *jz4760_pwm7_groups[] = { "pwm7", }; + +static const struct function_desc jz4760_functions[] = { + { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, + { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, + { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, + { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, + { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, + { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, + { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, + { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, + { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, + { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, + { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, + { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, + { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, + { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, + { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, + { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, + { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, + { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, + { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, + { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, + { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, + { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, + { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, + { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, + { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, + { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, +}; + +static const struct ingenic_chip_info jz4760_chip_info = { + .num_chips = 6, + .groups = jz4760_groups, + .num_groups = ARRAY_SIZE(jz4760_groups), + .functions = jz4760_functions, + .num_functions = ARRAY_SIZE(jz4760_functions), + .pull_ups = jz4760_pull_ups, + .pull_downs = jz4760_pull_downs, +}; + +static const struct ingenic_chip_info jz4760b_chip_info = { + .num_chips = 6, + .groups = jz4760_groups, + .num_groups = ARRAY_SIZE(jz4760_groups), + .functions = jz4760_functions, + .num_functions = ARRAY_SIZE(jz4760_functions), + .pull_ups = jz4760_pull_ups, + .pull_downs = jz4760_pull_downs, +}; + static const u32 jz4770_pull_ups[6] = { 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, }; @@ -775,8 +1040,8 @@ static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, u8 offset, int value) { - if (jzgc->jzpc->version >= ID_JZ4770) - ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); + if (jzgc->jzpc->version >= ID_JZ4760) + ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); } @@ -786,9 +1051,9 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, { u8 reg1, reg2; - if (jzgc->jzpc->version >= ID_JZ4770) { - reg1 = JZ4770_GPIO_PAT1; - reg2 = JZ4770_GPIO_PAT0; + if (jzgc->jzpc->version >= ID_JZ4760) { + reg1 = JZ4760_GPIO_PAT1; + reg2 = JZ4760_GPIO_PAT0; } else { reg1 = JZ4740_GPIO_TRIG; reg2 = JZ4740_GPIO_DIR; @@ -837,8 +1102,8 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd) struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); int irq = irqd->hwirq; - if (jzgc->jzpc->version >= ID_JZ4770) - ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); + if (jzgc->jzpc->version >= ID_JZ4760) + ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); @@ -853,8 +1118,8 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd) ingenic_gpio_irq_mask(irqd); - if (jzgc->jzpc->version >= ID_JZ4770) - ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); + if (jzgc->jzpc->version >= ID_JZ4760) + ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); } @@ -878,8 +1143,8 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd) irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING); } - if (jzgc->jzpc->version >= ID_JZ4770) - ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); + if (jzgc->jzpc->version >= ID_JZ4760) + ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); } @@ -935,8 +1200,8 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc) chained_irq_enter(irq_chip, desc); - if (jzgc->jzpc->version >= ID_JZ4770) - flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG); + if (jzgc->jzpc->version >= ID_JZ4760) + flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG); else flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); @@ -1001,8 +1266,8 @@ static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) struct ingenic_pinctrl *jzpc = jzgc->jzpc; unsigned int pin = gc->base + offset; - if (jzpc->version >= ID_JZ4770) - return ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1); + if (jzpc->version >= ID_JZ4760) + return ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1); if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) return true; @@ -1027,11 +1292,11 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 'A' + offt, idx, func); - if (jzpc->version >= ID_JZ4770) { - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); + if (jzpc->version >= ID_JZ4760) { + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); ingenic_config_pin(jzpc, pin, GPIO_MSK, false); - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); } else { ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); @@ -1080,10 +1345,10 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 'A' + offt, idx, input ? "in" : "out"); - if (jzpc->version >= ID_JZ4770) { - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); + if (jzpc->version >= ID_JZ4760) { + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); ingenic_config_pin(jzpc, pin, GPIO_MSK, true); - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); } else { ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); @@ -1110,8 +1375,8 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, unsigned int offt = pin / PINS_PER_GPIO_CHIP; bool pull; - if (jzpc->version >= ID_JZ4770) - pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); + if (jzpc->version >= ID_JZ4760) + pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN); else pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); @@ -1142,8 +1407,8 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, unsigned int pin, bool enabled) { - if (jzpc->version >= ID_JZ4770) - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !enabled); + if (jzpc->version >= ID_JZ4760) + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !enabled); else ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled); } @@ -1263,6 +1528,8 @@ static const struct regmap_config ingenic_pinctrl_regmap_config = { static const struct of_device_id ingenic_pinctrl_of_match[] = { { .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 }, { .compatible = "ingenic,jz4725b-pinctrl", .data = (void *)ID_JZ4725B }, + { .compatible = "ingenic,jz4760-pinctrl", .data = (void *) ID_JZ4760 }, + { .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B }, { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 }, { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 }, {}, @@ -1270,6 +1537,7 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { static const struct of_device_id ingenic_gpio_of_match[] __initconst = { { .compatible = "ingenic,jz4740-gpio", }, + { .compatible = "ingenic,jz4760-gpio", }, { .compatible = "ingenic,jz4770-gpio", }, { .compatible = "ingenic,jz4780-gpio", }, {}, @@ -1391,6 +1659,10 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) chip_info = &jz4780_chip_info; else if (jzpc->version >= ID_JZ4770) chip_info = &jz4770_chip_info; + else if (jzpc->version >= ID_JZ4760B) + chip_info = &jz4760b_chip_info; + else if (jzpc->version >= ID_JZ4760) + chip_info = &jz4760_chip_info; else if (jzpc->version >= ID_JZ4725B) chip_info = &jz4725b_chip_info; else @@ -1467,6 +1739,8 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) static const struct platform_device_id ingenic_pinctrl_ids[] = { { "jz4740-pinctrl", ID_JZ4740 }, { "jz4725b-pinctrl", ID_JZ4725B }, + { "jz4760-pinctrl", ID_JZ4760 }, + { "jz4760b-pinctrl", ID_JZ4760B }, { "jz4770-pinctrl", ID_JZ4770 }, { "jz4780-pinctrl", ID_JZ4780 }, {}, From patchwork Sun Jul 14 03:53:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 1131681 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=zoho.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="Uduj8Tqh"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45mdBX6kwjz9sN6 for ; Sun, 14 Jul 2019 17:11:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726799AbfGNHLq (ORCPT ); Sun, 14 Jul 2019 03:11:46 -0400 Received: from sender4-pp-o95.zoho.com ([136.143.188.95]:25559 "EHLO sender4-pp-o95.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728275AbfGNHLq (ORCPT ); Sun, 14 Jul 2019 03:11:46 -0400 ARC-Seal: i=1; a=rsa-sha256; t=1563087394; cv=none; d=zoho.com; s=zohoarc; b=BCpHCA5wo5z5nzUNp9SGvMTYO48B6vv4zvpjYqyywOgT7hGylaq9jF7hxblQqNhzSQ6BOeIXdUvUTNPeDpsr1QfRdmsMUuUT6kBb+PA2C50bOYavarQazvOqDwnqBTIpcCi7uqM8sEZszscwqdtNEiQygd50q5bVrLM1WiMDgwc= ARC-Message-Signature: i=1; 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b=Uduj8TqhQK6hHx6iaYgEv39PWzWSCadM6MQG/MOb6ul3JTGA0v2XvUoTSj63RQET bbQ+WAnoILwCEWihMSrfNwl8F0JupnfnW0L04Cg/cGIxAq6HvX72Mx+qhgdloSEVD31 EIEunJ478TrecmEeiy9RcGBWzD2nlEuxVlF/bVtQ= Received: from zhouyanjie-virtual-machine.localdomain (125.71.5.36 [125.71.5.36]) by mx.zohomail.com with SMTPS id 1563087394688413.43827450011634; Sat, 13 Jul 2019 23:56:34 -0700 (PDT) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, paul.burton@mips.com, linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH 3/6] dt-bindings: pinctrl: Add X1000 and X1000E bindings. Date: Sun, 14 Jul 2019 11:53:53 +0800 Message-Id: <1563076436-5338-4-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> References: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the pinctrl bindings for the X1000 Soc and the X1000E Soc from Ingenic. Signed-off-by: Zhou Yanjie --- .../devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt index a80ff68..7e2ee46 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt @@ -1,18 +1,18 @@ -Ingenic jz47xx pin controller +Ingenic XBurst pin controller Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". -For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may +For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may be used as GPIOs, multiplexed device functions are configured within the GPIO port configuration registers and it is typical to refer to pins using the naming scheme "PxN" where x is a character identifying the GPIO port with which the pin is associated and N is an integer from 0 to 31 identifying the pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and -PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to -PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 contains 6 -GPIO ports, PA to PF, for a total of 192 pins. +PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO +ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 +contains 6 GPIO ports, PA to PF, for a total of 192 pins. Required properties: @@ -25,6 +25,8 @@ Required properties: - "ingenic,jz4760b-pinctrl" - "ingenic,jz4770-pinctrl" - "ingenic,jz4780-pinctrl" + - "ingenic,x1000-pinctrl" + - "ingenic,x1000e-pinctrl" - reg: Address range of the pinctrl registers. @@ -36,6 +38,7 @@ Required properties for sub-nodes (GPIO chips): - "ingenic,jz4760-gpio" - "ingenic,jz4770-gpio" - "ingenic,jz4780-gpio" + - "ingenic,x1000-gpio" - reg: The GPIO bank number. - interrupt-controller: Marks the device node as an interrupt controller. - interrupts: Interrupt specifier for the controllers interrupt. From patchwork Sun Jul 14 03:53:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 1131683 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=zoho.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="cztYgTEs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45mdDG46zXz9sN6 for ; Sun, 14 Jul 2019 17:13:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728218AbfGNHNR (ORCPT ); Sun, 14 Jul 2019 03:13:17 -0400 Received: from sender4-pp-o95.zoho.com ([136.143.188.95]:25564 "EHLO sender4-pp-o95.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728106AbfGNHNQ (ORCPT ); Sun, 14 Jul 2019 03:13:16 -0400 ARC-Seal: i=1; a=rsa-sha256; t=1563087481; cv=none; d=zoho.com; s=zohoarc; b=nOxFUJDAerAM6KJ3+GgS/GfzNzLAPi88Vij71x+lIXhQhe05S1B6B5iRufPoE5rnISFPvWh+yB8jToQ8NAJBH+Pjxd33b8KYsbQAAH34Yae8ojotCd1idzsSazO8MFMEKmmT+dUJtdWgIcu2GKQhRIdeCXBKTMURPj6drY/71hg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563087481; h=Cc:Date:From:In-Reply-To:Message-ID:References:Subject:To:ARC-Authentication-Results; bh=ysjuo3aAVjPUj4LLv/F92GLnhhr6hh0rIgJybioLgJg=; b=A+/dhqS3ufoauMaXjryJdPJa1lRSuTS2uFiDLsz2VumWX5XVJgeqkternNSqpP4rPBpp/px+5VhfYwB4/RaK6fPjfQUtffw/M5+VcTpdjW3je5BtdF/nEUYEHU1qc8LQ9ebN9FsW/7BR4fLGhvcirb+AYs+bzXbkFxnUUHcmZZA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass header.i=zoho.com; spf=pass smtp.mailfrom=zhouyanjie@zoho.com; dmarc=pass header.from= header.from= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=zapps768; d=zoho.com; h=from:to:cc:subject:date:message-id:in-reply-to:references; b=s1y70j5tKr5wxXHsEijl7lzJMgHA80tjbP10n/lla9MSXWmF7izwvUmJ8PzuP2TgvJA+XiZ9UIa7 3+8Z2vQ0nW1UIhZe1z12qFbXLtHHfDIDRiBDKG2Sadp0HtgcLfQB DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1563087481; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; l=16698; bh=ysjuo3aAVjPUj4LLv/F92GLnhhr6hh0rIgJybioLgJg=; b=cztYgTEsGrDrdVVN2e6Mu5MpZyW8Xf+ZNHlzbHwAoYjW4l5kxtVibhzhxMF2fxEF MJXqsqxE/EGEw9TJxSW3EuaJ/eDOlGl74GuZFfpvKXI/Q4BWay7Le+dCNQgFJE6Pl8O OwNSkQyc3zPWAd/EKlvM+OQuJt8I0tnACH12+JGU= Received: from zhouyanjie-virtual-machine.localdomain (125.71.5.36 [125.71.5.36]) by mx.zohomail.com with SMTPS id 1563087480222262.04018488072404; Sat, 13 Jul 2019 23:58:00 -0700 (PDT) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, paul.burton@mips.com, linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH 4/6] pinctrl: Ingenic: Add pinctrl driver for X1000 and X1000E. Date: Sun, 14 Jul 2019 11:53:54 +0800 Message-Id: <1563076436-5338-5-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> References: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add support for probing the pinctrl-ingenic driver on the X1000 Soc and the X1000E Soc from Ingenic. Signed-off-by: Zhou Yanjie --- drivers/pinctrl/pinctrl-ingenic.c | 307 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 296 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index ec61b083..5bb4ae5 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -41,6 +41,9 @@ #define JZ4760_GPIO_FLAG 0x50 #define JZ4760_GPIO_PEN 0x70 +#define X1000_GPIO_PZ_BASE 0x700 +#define X1000_GPIO_PZ_GID2LD 0x7f0 + #define REG_SET(x) ((x) + 0x4) #define REG_CLEAR(x) ((x) + 0x8) @@ -53,6 +56,8 @@ enum jz_version { ID_JZ4760B, ID_JZ4770, ID_JZ4780, + ID_X1000, + ID_X1000E, }; struct ingenic_chip_info { @@ -1009,6 +1014,210 @@ static const struct ingenic_chip_info jz4780_chip_info = { .pull_downs = jz4770_pull_downs, }; +static const u32 x1000_pull_ups[4] = { + 0xffffffff, 0x8dffffff, 0x7d3fffff, 0xffffffff, +}; + +static const u32 x1000_pull_downs[4] = { + 0x00000000, 0x02000000, 0x02000000, 0x00000000, +}; + +static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; +static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; +static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; +static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; +static int x1000_uart1_hwflow_d_pins[] = { 0x64, 0x65, }; +static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; +static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; +static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; +static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; +static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; +static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; +static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; +static int x1000_nemc_8bit_data_pins[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, +}; +static int x1000_nemc_16bit_data_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, +}; +static int x1000_nemc_addr_pins[] = { + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, +}; +static int x1000_nemc_rd_we_pins[] = { 0x30, 0x31, }; +static int x1000_nemc_wait_pins[] = { 0x34, }; +static int x1000_nemc_cs1_pins[] = { 0x32, }; +static int x1000_nemc_cs2_pins[] = { 0x33, }; +static int x1000_i2c0_pins[] = { 0x38, 0x37, }; +static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; +static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; +static int x1000_i2c2_pins[] = { 0x61, 0x60, }; +static int x1000_cim_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, + 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, +}; +static int x1000_lcd_8bit_pins[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x30, 0x31, 0x32, 0x33, 0x34, +}; +static int x1000_lcd_16bit_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, +}; +static int x1000_pwm_pwm0_pins[] = { 0x59, }; +static int x1000_pwm_pwm1_pins[] = { 0x5a, }; +static int x1000_pwm_pwm2_pins[] = { 0x5b, }; +static int x1000_pwm_pwm3_pins[] = { 0x26, }; +static int x1000_pwm_pwm4_pins[] = { 0x58, }; +static int x1000_mac_pins[] = { + 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, +}; + +static int x1000_uart0_data_funcs[] = { 0, 0, }; +static int x1000_uart0_hwflow_funcs[] = { 0, 0, }; +static int x1000_uart1_data_a_funcs[] = { 2, 2, }; +static int x1000_uart1_data_d_funcs[] = { 1, 1, }; +static int x1000_uart1_hwflow_d_funcs[] = { 1, 1, }; +static int x1000_uart2_data_a_funcs[] = { 2, 2, }; +static int x1000_uart2_data_d_funcs[] = { 0, 0, }; +static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; +static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; +static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; +static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, }; +static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, }; +static int x1000_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int x1000_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int x1000_nemc_addr_funcs[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +}; +static int x1000_nemc_rd_we_funcs[] = { 0, 0, }; +static int x1000_nemc_wait_funcs[] = { 0, }; +static int x1000_nemc_cs1_funcs[] = { 0, }; +static int x1000_nemc_cs2_funcs[] = { 0, }; +static int x1000_i2c0_funcs[] = { 0, 0, }; +static int x1000_i2c1_a_funcs[] = { 2, 2, }; +static int x1000_i2c1_c_funcs[] = { 0, 0, }; +static int x1000_i2c2_funcs[] = { 1, 1, }; +static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; +static int x1000_lcd_8bit_funcs[] = { + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, +}; +static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; +static int x1000_pwm_pwm0_funcs[] = { 0, }; +static int x1000_pwm_pwm1_funcs[] = { 1, }; +static int x1000_pwm_pwm2_funcs[] = { 1, }; +static int x1000_pwm_pwm3_funcs[] = { 2, }; +static int x1000_pwm_pwm4_funcs[] = { 0, }; +static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static const struct group_desc x1000_groups[] = { + INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data), + INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow), + INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a), + INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d), + INGENIC_PIN_GROUP("uart1-hwflow-d", x1000_uart1_hwflow_d), + INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), + INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), + INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), + INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit), + INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), + INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit), + INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit), + INGENIC_PIN_GROUP("nemc-8bit-data", x1000_nemc_8bit_data), + INGENIC_PIN_GROUP("nemc-16bit-data", x1000_nemc_16bit_data), + INGENIC_PIN_GROUP("nemc-addr", x1000_nemc_addr), + INGENIC_PIN_GROUP("nemc-rd-we", x1000_nemc_rd_we), + INGENIC_PIN_GROUP("nemc-wait", x1000_nemc_wait), + INGENIC_PIN_GROUP("nemc-cs1", x1000_nemc_cs1), + INGENIC_PIN_GROUP("nemc-cs2", x1000_nemc_cs2), + INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0), + INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), + INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), + INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2), + INGENIC_PIN_GROUP("cim-data", x1000_cim), + INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit), + INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit), + { "lcd-no-pins", }, + INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0), + INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1), + INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2), + INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3), + INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4), + INGENIC_PIN_GROUP("mac", x1000_mac), +}; + +static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *x1000_uart1_groups[] = { + "uart1-data-a", "uart1-data-d", "uart1-hwflow-d", +}; +static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; +static const char *x1000_mmc0_groups[] = { + "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", +}; +static const char *x1000_mmc1_groups[] = { + "mmc1-1bit-e", "mmc1-4bit-e", +}; +static const char *x1000_nemc_groups[] = { + "nemc-8bit-data", "nemc-16bit-data", + "nemc-addr", "nemc-rd-we", "nemc-wait", +}; +static const char *x1000_cs1_groups[] = { "nemc-cs1", }; +static const char *x1000_cs2_groups[] = { "nemc-cs2", }; +static const char *x1000_i2c0_groups[] = { "i2c0-data", }; +static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; +static const char *x1000_i2c2_groups[] = { "i2c2-data", }; +static const char *x1000_cim_groups[] = { "cim-data", }; +static const char *x1000_lcd_groups[] = { + "lcd-8bit", "lcd-16bit", "lcd-no-pins", +}; +static const char *x1000_pwm0_groups[] = { "pwm0", }; +static const char *x1000_pwm1_groups[] = { "pwm1", }; +static const char *x1000_pwm2_groups[] = { "pwm2", }; +static const char *x1000_pwm3_groups[] = { "pwm3", }; +static const char *x1000_pwm4_groups[] = { "pwm4", }; +static const char *x1000_mac_groups[] = { "mac", }; + +static const struct function_desc x1000_functions[] = { + { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, + { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, + { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, + { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, + { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, + { "nemc", x1000_nemc_groups, ARRAY_SIZE(x1000_nemc_groups), }, + { "nemc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, + { "nemc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, + { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, + { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, + { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, + { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, + { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, + { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, + { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, + { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, + { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, + { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, + { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, +}; + +static const struct ingenic_chip_info x1000_chip_info = { + .num_chips = 4, + .groups = x1000_groups, + .num_groups = ARRAY_SIZE(x1000_groups), + .functions = x1000_functions, + .num_functions = ARRAY_SIZE(x1000_functions), + .pull_ups = x1000_pull_ups, + .pull_downs = x1000_pull_downs, +}; + +static const struct ingenic_chip_info x1000e_chip_info = { + .num_chips = 4, + .groups = x1000_groups, + .num_groups = ARRAY_SIZE(x1000_groups), + .functions = x1000_functions, + .num_functions = ARRAY_SIZE(x1000_functions), + .pull_ups = x1000_pull_ups, + .pull_downs = x1000_pull_downs, +}; + static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) { unsigned int val; @@ -1029,6 +1238,23 @@ static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); } +static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, + u8 reg, u8 offset, bool set) +{ + if (set) + reg = REG_SET(reg); + else + reg = REG_CLEAR(reg); + + regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset)); +} + +static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) +{ + regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_GID2LD, + jzgc->gc.base / PINS_PER_GPIO_CHIP); +} + static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, u8 offset) { @@ -1061,21 +1287,45 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, switch (type) { case IRQ_TYPE_EDGE_RISING: - ingenic_gpio_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_set_bit(jzgc, reg1, offset, true); + if (jzgc->jzpc->version >= ID_X1000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); + ingenic_gpio_shadow_set_bit_load(jzgc); + } else { + ingenic_gpio_set_bit(jzgc, reg2, offset, true); + ingenic_gpio_set_bit(jzgc, reg1, offset, true); + } break; case IRQ_TYPE_EDGE_FALLING: - ingenic_gpio_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_set_bit(jzgc, reg1, offset, true); + if (jzgc->jzpc->version >= ID_X1000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); + ingenic_gpio_shadow_set_bit_load(jzgc); + } else { + ingenic_gpio_set_bit(jzgc, reg2, offset, false); + ingenic_gpio_set_bit(jzgc, reg1, offset, true); + } break; case IRQ_TYPE_LEVEL_HIGH: - ingenic_gpio_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_set_bit(jzgc, reg1, offset, false); + if (jzgc->jzpc->version >= ID_X1000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); + ingenic_gpio_shadow_set_bit_load(jzgc); + } else { + ingenic_gpio_set_bit(jzgc, reg2, offset, true); + ingenic_gpio_set_bit(jzgc, reg1, offset, false); + } break; case IRQ_TYPE_LEVEL_LOW: default: - ingenic_gpio_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_set_bit(jzgc, reg1, offset, false); + if (jzgc->jzpc->version >= ID_X1000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); + ingenic_gpio_shadow_set_bit_load(jzgc); + } else { + ingenic_gpio_set_bit(jzgc, reg2, offset, false); + ingenic_gpio_set_bit(jzgc, reg1, offset, false); + } break; } } @@ -1248,6 +1498,21 @@ static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); } +static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, + unsigned int pin, u8 reg, bool set) +{ + unsigned int idx = pin % PINS_PER_GPIO_CHIP; + + regmap_write(jzpc->map, X1000_GPIO_PZ_BASE + + (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); +} + +static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, + unsigned int pin) +{ + regmap_write(jzpc->map, X1000_GPIO_PZ_GID2LD, pin / PINS_PER_GPIO_CHIP); +} + static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, unsigned int pin, u8 reg) { @@ -1292,7 +1557,13 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 'A' + offt, idx, func); - if (jzpc->version >= ID_JZ4760) { + if (jzpc->version >= ID_X1000) { + ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); + ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); + ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); + ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); + ingenic_shadow_config_pin_load(jzpc, pin); + } else if (jzpc->version >= ID_JZ4760) { ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); ingenic_config_pin(jzpc, pin, GPIO_MSK, false); ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); @@ -1345,7 +1616,12 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 'A' + offt, idx, input ? "in" : "out"); - if (jzpc->version >= ID_JZ4760) { + if (jzpc->version >= ID_X1000) { + ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); + ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); + ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); + ingenic_shadow_config_pin_load(jzpc, pin); + } else if (jzpc->version >= ID_JZ4760) { ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); ingenic_config_pin(jzpc, pin, GPIO_MSK, true); ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); @@ -1532,6 +1808,8 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { { .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B }, { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 }, { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 }, + { .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 }, + { .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E }, {}, }; @@ -1540,6 +1818,7 @@ static const struct of_device_id ingenic_gpio_of_match[] __initconst = { { .compatible = "ingenic,jz4760-gpio", }, { .compatible = "ingenic,jz4770-gpio", }, { .compatible = "ingenic,jz4780-gpio", }, + { .compatible = "ingenic,x1000-gpio", }, {}, }; @@ -1655,7 +1934,11 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) else jzpc->version = (enum jz_version)id->driver_data; - if (jzpc->version >= ID_JZ4780) + if (jzpc->version >= ID_X1000E) + chip_info = &x1000e_chip_info; + else if (jzpc->version >= ID_X1000) + chip_info = &x1000_chip_info; + else if (jzpc->version >= ID_JZ4780) chip_info = &jz4780_chip_info; else if (jzpc->version >= ID_JZ4770) chip_info = &jz4770_chip_info; @@ -1743,6 +2026,8 @@ static const struct platform_device_id ingenic_pinctrl_ids[] = { { "jz4760b-pinctrl", ID_JZ4760B }, { "jz4770-pinctrl", ID_JZ4770 }, { "jz4780-pinctrl", ID_JZ4780 }, + { "x1000-pinctrl", ID_X1000 }, + { "x1000e-pinctrl", ID_X1000E }, {}, }; From patchwork Sun Jul 14 03:53:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 1131684 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=zoho.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="gYBDppZ3"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45mdDr2NlJz9sND for ; Sun, 14 Jul 2019 17:13:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728257AbfGNHNq (ORCPT ); Sun, 14 Jul 2019 03:13:46 -0400 Received: from sender-pp-o92.zoho.com ([135.84.80.237]:25454 "EHLO sender-pp-o92.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728221AbfGNHNq (ORCPT ); Sun, 14 Jul 2019 03:13:46 -0400 ARC-Seal: i=1; a=rsa-sha256; t=1563087513; cv=none; d=zoho.com; s=zohoarc; b=kguB6JxfqtlnhUmhR1Nb6MDJjeMxV1Dw1jwJxW5BbIt3EvxcTnZTnXa9/q0bC2/+KqWiKQzvn/Z6yCsbN1jpx/FzL6IEZ4hIGWqWsI92NPhiZ930NSmgAwRiDrs6dyZOAJpndf1UlOHIbrkCt7b2Cvc5CoXX5kVG+2CaW4VPX7k= ARC-Message-Signature: i=1; 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b=gYBDppZ3+ygLODyqht3EzZD5JoeSd8UFNjKd+vqXw25NLZBY90L/ih1h7hCv88L+ EIcXV+LpaSP6oKmPrRZ1J0UR1/jJ5w531b6GP4NsNcON6bHVp7p0U/LcCwHJCbFt6R3 b5jVDg19ADLf8IISgJCdwxDOcR/4CUyzB1AMHqPQ= Received: from zhouyanjie-virtual-machine.localdomain (125.71.5.36 [125.71.5.36]) by mx.zohomail.com with SMTPS id 1563087512516142.16015020040902; Sat, 13 Jul 2019 23:58:32 -0700 (PDT) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, paul.burton@mips.com, linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH 5/6] dt-bindings: pinctrl: Add X1500 bindings. Date: Sun, 14 Jul 2019 11:53:55 +0800 Message-Id: <1563076436-5338-6-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> References: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the pinctrl bindings for the X1500 Soc from Ingenic. Signed-off-by: Zhou Yanjie --- Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt index 7e2ee46..0014d98 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt @@ -27,6 +27,7 @@ Required properties: - "ingenic,jz4780-pinctrl" - "ingenic,x1000-pinctrl" - "ingenic,x1000e-pinctrl" + - "ingenic,x1500-pinctrl" - reg: Address range of the pinctrl registers. From patchwork Sun Jul 14 03:53:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 1131686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=zoho.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="gJdFpe52"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45mdFj4ww3z9sND for ; Sun, 14 Jul 2019 17:14:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728292AbfGNHOc (ORCPT ); Sun, 14 Jul 2019 03:14:32 -0400 Received: from sender-pp-o92.zoho.com ([135.84.80.237]:25443 "EHLO sender-pp-o92.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728270AbfGNHOb (ORCPT ); Sun, 14 Jul 2019 03:14:31 -0400 ARC-Seal: i=1; a=rsa-sha256; t=1563087559; cv=none; d=zoho.com; s=zohoarc; b=L4Z/fBDUVft6JdVEF8oEsDur7LnICzpsTtIIOjT67oja0IaZm86Sqw2YXtlmWcDfv7BHzklvNpbKLvgq92/+z/jHovg1uLLdZYjRNhk6QKvo06dwwZiSsr8ZRT81rRdgsw1EkEUCzArZQLZQ/v+o8p4b8ZQkO3PR4zpFpVLg8wY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563087559; h=Cc:Date:From:In-Reply-To:Message-ID:References:Subject:To:ARC-Authentication-Results; bh=c5cG3HXWY3IylMLOLUOUc1HqbW9QEvHahf5tChUYxzs=; b=eUhLTZT9l6S5JG3tSwsfrRF2orXq9AFlkwCdSCE8vtuytNEGDvJN660Uf3dYHyN3jVOt4hsZ1ti/IOJQsKvemilkpg3wEmTBBFrZ4HxzOQwjm9qAMSieFJRoIwkDES+sA9ovUhww0RCpsF8qL5OGj8ETdnVoWRJ8IbSTEdYFrGw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass header.i=zoho.com; spf=pass smtp.mailfrom=zhouyanjie@zoho.com; dmarc=pass header.from= header.from= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=zapps768; d=zoho.com; h=from:to:cc:subject:date:message-id:in-reply-to:references; b=HEe2jCuWq06EtjV3EnfsG0TUWQOReMut8EnjBRrexIq+uihm57SQWkh9mzdetRGQMHP194Ce/Kri /mqJjNn2SLN5ig1a168A9pyFdNecFwYRg/FOjC6B/yDeMdY3yX4P DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1563087559; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; l=7433; bh=c5cG3HXWY3IylMLOLUOUc1HqbW9QEvHahf5tChUYxzs=; b=gJdFpe52wHcW+FA7n9eoJHZYUSqH6mVJmlu5zLFyv1b0kLWhw+wNFWBJ/+J4DJu9 8/eid/UZa6EPMUKzZxJae+6EHbD5mvK+0yBU1ZCHn0Iyh2pwtwS/DXJofOPlDQrfqGF o+1ULTEKjXmkcWkqMsFX5bARRN2aUOgv1mpzLmpM= Received: from zhouyanjie-virtual-machine.localdomain (125.71.5.36 [125.71.5.36]) by mx.zohomail.com with SMTPS id 1563087558238275.29348659637753; Sat, 13 Jul 2019 23:59:18 -0700 (PDT) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, paul.burton@mips.com, linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH 6/6] pinctrl: Ingenic: Add pinctrl driver for X1500. Date: Sun, 14 Jul 2019 11:53:56 +0800 Message-Id: <1563076436-5338-7-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> References: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add support for probing the pinctrl-ingenic driver on the X1500 Soc from Ingenic. Signed-off-by: Zhou Yanjie --- drivers/pinctrl/pinctrl-ingenic.c | 118 +++++++++++++++++++++++++++++++++++++- 1 file changed, 117 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 5bb4ae5..6e26830 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -3,6 +3,7 @@ * Ingenic SoCs pinctrl driver * * Copyright (c) 2017 Paul Cercueil + * Copyright (c) 2019 Zhou Yanjie */ #include @@ -58,6 +59,7 @@ enum jz_version { ID_JZ4780, ID_X1000, ID_X1000E, + ID_X1500, }; struct ingenic_chip_info { @@ -1218,6 +1220,116 @@ static const struct ingenic_chip_info x1000e_chip_info = { .pull_downs = x1000_pull_downs, }; +static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; +static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; +static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; +static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; +static int x1500_uart1_hwflow_d_pins[] = { 0x64, 0x65, }; +static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; +static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; +static int x1500_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; +static int x1500_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; +static int x1500_i2c0_pins[] = { 0x38, 0x37, }; +static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; +static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; +static int x1500_i2c2_pins[] = { 0x61, 0x60, }; +static int x1500_cim_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, + 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, +}; +static int x1500_pwm_pwm0_pins[] = { 0x59, }; +static int x1500_pwm_pwm1_pins[] = { 0x5a, }; +static int x1500_pwm_pwm2_pins[] = { 0x5b, }; +static int x1500_pwm_pwm3_pins[] = { 0x26, }; +static int x1500_pwm_pwm4_pins[] = { 0x58, }; + +static int x1500_uart0_data_funcs[] = { 0, 0, }; +static int x1500_uart0_hwflow_funcs[] = { 0, 0, }; +static int x1500_uart1_data_a_funcs[] = { 2, 2, }; +static int x1500_uart1_data_d_funcs[] = { 1, 1, }; +static int x1500_uart1_hwflow_d_funcs[] = { 1, 1, }; +static int x1500_uart2_data_a_funcs[] = { 2, 2, }; +static int x1500_uart2_data_d_funcs[] = { 0, 0, }; +static int x1500_mmc0_1bit_funcs[] = { 1, 1, 1, }; +static int x1500_mmc0_4bit_funcs[] = { 1, 1, 1, }; +static int x1500_i2c0_funcs[] = { 0, 0, }; +static int x1500_i2c1_a_funcs[] = { 2, 2, }; +static int x1500_i2c1_c_funcs[] = { 0, 0, }; +static int x1500_i2c2_funcs[] = { 1, 1, }; +static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; +static int x1500_pwm_pwm0_funcs[] = { 0, }; +static int x1500_pwm_pwm1_funcs[] = { 1, }; +static int x1500_pwm_pwm2_funcs[] = { 1, }; +static int x1500_pwm_pwm3_funcs[] = { 2, }; +static int x1500_pwm_pwm4_funcs[] = { 0, }; + +static const struct group_desc x1500_groups[] = { + INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data), + INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow), + INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a), + INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d), + INGENIC_PIN_GROUP("uart1-hwflow-d", x1500_uart1_hwflow_d), + INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), + INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), + INGENIC_PIN_GROUP("mmc0-1bit", x1500_mmc0_1bit), + INGENIC_PIN_GROUP("mmc0-4bit", x1500_mmc0_4bit), + INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), + INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), + INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), + INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2), + INGENIC_PIN_GROUP("cim-data", x1500_cim), + { "lcd-no-pins", }, + INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0), + INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1), + INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2), + INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3), + INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4), +}; + +static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *x1500_uart1_groups[] = { + "uart1-data-a", "uart1-data-d", "uart1-hwflow-d", +}; +static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; +static const char *x1500_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; +static const char *x1500_i2c0_groups[] = { "i2c0-data", }; +static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; +static const char *x1500_i2c2_groups[] = { "i2c2-data", }; +static const char *x1500_cim_groups[] = { "cim-data", }; +static const char *x1500_lcd_groups[] = { "lcd-no-pins", }; +static const char *x1500_pwm0_groups[] = { "pwm0", }; +static const char *x1500_pwm1_groups[] = { "pwm1", }; +static const char *x1500_pwm2_groups[] = { "pwm2", }; +static const char *x1500_pwm3_groups[] = { "pwm3", }; +static const char *x1500_pwm4_groups[] = { "pwm4", }; + +static const struct function_desc x1500_functions[] = { + { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, + { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, + { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, + { "mmc0", x1500_mmc0_groups, ARRAY_SIZE(x1500_mmc0_groups), }, + { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, + { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, + { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, + { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, + { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), }, + { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, + { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, + { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, + { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, + { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, +}; + +static const struct ingenic_chip_info x1500_chip_info = { + .num_chips = 4, + .groups = x1500_groups, + .num_groups = ARRAY_SIZE(x1500_groups), + .functions = x1500_functions, + .num_functions = ARRAY_SIZE(x1500_functions), + .pull_ups = x1000_pull_ups, + .pull_downs = x1000_pull_downs, +}; + static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) { unsigned int val; @@ -1810,6 +1922,7 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 }, { .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 }, { .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E }, + { .compatible = "ingenic,x1500-pinctrl", .data = (void *) ID_X1500 }, {}, }; @@ -1934,7 +2047,9 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) else jzpc->version = (enum jz_version)id->driver_data; - if (jzpc->version >= ID_X1000E) + if (jzpc->version >= ID_X1500) + chip_info = &x1500_chip_info; + else if (jzpc->version >= ID_X1000E) chip_info = &x1000e_chip_info; else if (jzpc->version >= ID_X1000) chip_info = &x1000_chip_info; @@ -2028,6 +2143,7 @@ static const struct platform_device_id ingenic_pinctrl_ids[] = { { "jz4780-pinctrl", ID_JZ4780 }, { "x1000-pinctrl", ID_X1000 }, { "x1000e-pinctrl", ID_X1000E }, + { "x1500-pinctrl", ID_X1500 }, {}, };