From patchwork Mon Jul 8 11:04:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Chen X-Patchwork-Id: 1129049 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45j2fd56MKz9sMr for ; Mon, 8 Jul 2019 21:05:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728274AbfGHLFM (ORCPT ); Mon, 8 Jul 2019 07:05:12 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:33875 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727625AbfGHLFM (ORCPT ); Mon, 8 Jul 2019 07:05:12 -0400 X-UUID: 616d08799c88431ab5b31eb9710c1fb7-20190708 X-UUID: 616d08799c88431ab5b31eb9710c1fb7-20190708 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2007830324; Mon, 08 Jul 2019 19:05:08 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 8 Jul 2019 19:05:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 8 Jul 2019 19:05:06 +0800 From: To: , , , , CC: , , , , , , , , , , , , , , , , , Subject: [RFC PATCH V2 1/6] dt-bindings: mt8183: Added DIP dt-bindings Date: Mon, 8 Jul 2019 19:04:55 +0800 Message-ID: <20190708110500.7242-2-frederic.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190708110500.7242-1-frederic.chen@mediatek.com> References: <20190708110500.7242-1-frederic.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Frederic Chen This patch adds DT binding documentation for the Digital Image Processing (DIP) unit of camera ISP system on Mediatek's SoCs. It depends on the SCP and MDP 3 patch as following: 1. dt-bindings: Add a binding for Mediatek SCP https://patchwork.kernel.org/patch/11027247/ 2. dt-binding: mt8183: Add Mediatek MDP3 dt-bindings https://patchwork.kernel.org/patch/10945603/ Signed-off-by: Frederic Chen Reviewed-by: Rob Herring --- .../bindings/media/mediatek,mt8183-dip.txt | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt b/Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt new file mode 100644 index 000000000000..3a0435513089 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt @@ -0,0 +1,40 @@ +* Mediatek Digital Image Processor (DIP) + +Digital Image Processor (DIP) unit in Mediatek ISP system is responsible for +image content adjustment according to the tuning parameters. DIP can process +the image form memory buffer and output the processed image to multiple output +buffers. Furthermore, it can support demosaicing and noise reduction on the +images. + +Required properties: +- compatible: "mediatek,mt8183-dip" +- reg: Physical base address and length of the function block register space +- interrupts: interrupt number to the cpu +- iommus: should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt + for details. +- mediatek,mdp3: should point to the respective mdp block. DIP hardware + connects to MDP and we can get the processed image with both effect of the + two blocks. +- mediatek,larb: must contain the local arbiters in the current SoCs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details. +- mediatek,scp: should point to the scp node since the we use SCP + coprocessor to control DIP hardware +- clocks: must contain the local arbiters 5 (LARB5) and DIP clock +- clock-names: must contain "larb5" and "dip" + +Example: + dip: dip@15022000 { + compatible = "mediatek,mt8183-dip"; + mediatek,larb = <&larb5>; + mediatek,mdp3 = <&mdp_rdma0>; + mediatek,scp = <&scp>; + iommus = <&iommu M4U_PORT_CAM_IMGI>; + reg = <0 0x15022000 0 0x6000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_LARB5>, + <&imgsys CLK_IMG_DIP>; + clock-names = "larb5", + "dip"; + };