From patchwork Wed Jul 3 03:33:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 1126594 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-504237-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ahHSaoLX"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="K4MC61gi"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45dmtp5kGtz9s4V for ; Wed, 3 Jul 2019 13:34:26 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=aa+ diLq1WP2P8I1ZrxQpiHl1iwNW47zVzmqJPuxLE3TsTEIuinyoRnV5K5xWhuyEncZ NccD1sIbf5SyKArdApXjySV6s0BrQwGsyaYpx+euUypcSrUIg7x5anuVg3DzgGtr xAsYKiVsgSngSgF6aEb+CBbomAyU9ew87wuynW6Y= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=e9cJSolYi 61+55xF6vbAvfnlhVs=; b=ahHSaoLXWB3Jb47XRuLtV5gU68UMcNyMAi0oFwj50 feWWU4dfk94QS1sFj7Zvi7xauEh+hSKQhfIEhsFJlm+34BNSOdAA4uCVQJfoXceM HCLJJlud14XgqorjzBaPPx6plCcig0Maa2JqcQAmmJPc7qq9ADCC2iqkKQn/jSHy wI= Received: (qmail 38341 invoked by alias); 3 Jul 2019 03:34:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 38267 invoked by uid 89); 3 Jul 2019 03:34:10 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=5.3.0, borrowed X-HELO: mail-pl1-f176.google.com Received: from mail-pl1-f176.google.com (HELO mail-pl1-f176.google.com) (209.85.214.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 03 Jul 2019 03:34:07 +0000 Received: by mail-pl1-f176.google.com with SMTP id 9so415229ple.5 for ; Tue, 02 Jul 2019 20:34:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l2i6w6zvTuJiDQUvgJSAzrj7k+pLRsy0FIOccOj7CXY=; b=K4MC61gi/d3Aa3NMntAkWy0NT1x1aEeQUkGEiKXMSHm55PNMDR0Zyntpm3wYjHDIh/ dUsL/YCG7/3tIy0DABtk8YuSrjqZE/HStk5ORgdYjbr8J2s1fMdrA6GNK0L/PYKwQH7U 0Xkzo2wkz6jiMn151CWrT7KI4OChPga41h/SYKisHlrIKLB6tIGZoydUprflIzMuX5Ss Ql1xVO6mHzfDuhLZD1OO5S0ZezrHY8in8nO/tpBUU19Zb16n238AMLMJseUxnazYYCD+ LaJz+xQTlA11vX5g1spEPhP4fdVR8VsKJEQbbz3dF/EI1qNQPDVCtfaqJLQR6GBumxBi 6IdA== Received: from localhost (g223.61-115-60.ppp.wakwak.ne.jp. [61.115.60.223]) by smtp.gmail.com with ESMTPSA id w22sm527972pfi.175.2019.07.02.20.34.04 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 02 Jul 2019 20:34:05 -0700 (PDT) From: Stafford Horne To: GCC patches Cc: Openrisc , Bernhard Reutner-Fischer , Jeff Law , Stafford Horne Subject: [PATCH v2 1/5] or1k: Fix code quality for volatile memory loads Date: Wed, 3 Jul 2019 12:33:47 +0900 Message-Id: <20190703033351.11924-2-shorne@gmail.com> In-Reply-To: <20190703033351.11924-1-shorne@gmail.com> References: <20190703033351.11924-1-shorne@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Volatile memory does not match the memory_operand predicate. This causes extra extend/mask instructions instructions when reading from volatile memory. On OpenRISC loading volatile memory can be treated the same as regular memory loads which supports combined sign/zero extends. Fixing this eliminates the need for extra extend/mask instructions. This also adds a test provided by Richard Selvaggi which uncovered the issue while we were looking into another issue. gcc/ChangeLog: PR target/90363 * config/or1k/or1k.md (zero_extendsi2): Update predicate. (extendsi2): Update predicate. * gcc/config/or1k/predicates.md (volatile_mem_operand): New. (reg_or_mem_operand): New. gcc/testsuite/ChangeLog: PR target/90363 * gcc.target/or1k/swap-1.c: New test. * gcc.target/or1k/swap-2.c: New test. --- Since v1: - Fixed typos with volatile gcc/config/or1k/or1k.md | 6 +-- gcc/config/or1k/predicates.md | 18 +++++++ gcc/testsuite/gcc.target/or1k/swap-1.c | 70 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/or1k/swap-2.c | 47 +++++++++++++++++ 4 files changed, 138 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/or1k/swap-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/swap-2.c diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md index 2dad51cd46b..757d899c442 100644 --- a/gcc/config/or1k/or1k.md +++ b/gcc/config/or1k/or1k.md @@ -328,11 +328,11 @@ ;; Sign Extending ;; ------------------------------------------------------------------------- -;; Zero extension can always be done with AND and an extending load. +;; Zero extension can always be done with AND or an extending load. (define_insn "zero_extendsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))] + (zero_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))] "" "@ l.andi\t%0, %1, @@ -344,7 +344,7 @@ (define_insn "extendsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (sign_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))] + (sign_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))] "TARGET_SEXT" "@ l.exts\t%0, %1 diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md index 879236bca49..b895f1b4228 100644 --- a/gcc/config/or1k/predicates.md +++ b/gcc/config/or1k/predicates.md @@ -82,3 +82,21 @@ (define_predicate "equality_comparison_operator" (match_code "ne,eq")) + +;; Borrowed from rs6000 +; Return true if the operand is in volatile memory. Note that during the +;; RTL generation phase, memory_operand does not return TRUE for volatile +;; memory references. So this function allows us to recognize volatile +;; references where it's safe. +(define_predicate "volatile_mem_operand" + (and (match_code "mem") + (match_test "MEM_VOLATILE_P (op)") + (if_then_else (match_test "reload_completed") + (match_operand 0 "memory_operand") + (match_test "memory_address_p (mode, XEXP (op, 0))")))) + +;; Return true if the operand is a register or memory; including volatile +;; memory. +(define_predicate "reg_or_mem_operand" + (ior (match_operand 0 "nonimmediate_operand") + (match_operand 0 "volatile_mem_operand"))) diff --git a/gcc/testsuite/gcc.target/or1k/swap-1.c b/gcc/testsuite/gcc.target/or1k/swap-1.c new file mode 100644 index 00000000000..4c179d1e430 --- /dev/null +++ b/gcc/testsuite/gcc.target/or1k/swap-1.c @@ -0,0 +1,70 @@ +/* { dg-do run } */ +/* { dg-options "-Os -mhard-mul -msoft-div -msoft-float" } */ + +/* Notes: + + This test failed on or1k GCC 7.2.0, and passes on or1k GCC 5.3.0 + as well as the or1k port released in GCC 9.1. + + The main program is organized as a loop structure so gcc does not + optimize-away the calls to swap_1(). Compiling with -O2 is still smart + enough to optimize-away the calls, but using -Os does not. + The bad code is only generated when compiled with -Os. + + When the bad code is generated all code is okay except for the very last + instruction (a 'l.addc' in the l.jr delay slot). + Up to that point in execution, r11 and r12 contain the correct (expected) + values, but the execution of the final "l.addc" corrupts r11. + + This test is added to ensure this does not come back. */ + +#include + +volatile static uint8_t g_doswap = 1; + +uint64_t swap_1 (uint64_t u64) { + uint32_t u64_lo, u64_hi, u64_tmp; + + u64_lo = u64 & 0xFFFFFFFF; + u64_hi = u64 >> 32; + + if (g_doswap) + { + u64_tmp = u64_lo; + u64_lo = u64_hi; + u64_hi = u64_tmp; + } + + u64 = u64_lo; + u64 += ((uint64_t) u64_hi << 32); + + return u64; +} + +int main () { + int ret; + int iter; + uint64_t aa[2]; // inputs to swap function + uint64_t ee[2]; // expected outputs of swap function + uint64_t rr[2]; // actual results of swap function + + g_doswap = 1; + + // populate inputs, and expected outputs: + aa[0] = 0x123456789abcdef0; + aa[1] = 0x0123456789abcdef; + + ee[0] = 0x9ABCDEF012345678; + ee[1] = 0x89ABCDEF01234567; + + ret = 0; + for (iter = 0; iter < 2; iter++) + { + rr[iter] = swap_1(aa[iter]); + // early-out if there's a mis-match: + if (ee[iter] != rr[iter]) + ret = 1; + } + + return ret; +} diff --git a/gcc/testsuite/gcc.target/or1k/swap-2.c b/gcc/testsuite/gcc.target/or1k/swap-2.c new file mode 100644 index 00000000000..3730b4ee2e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/or1k/swap-2.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mhard-mul -msoft-div -msoft-float" } */ + +/* Notes: + + This test failed on or1k GCC 7.2.0, and passes on or1k GCC 5.3.0 + as well as the or1k port released in GCC 9.1. + + The main program is organized as a loop structure so gcc does not + optimize-away the calls to swap_1(). Compiling with -O2 is still smart + enough to optimize-away the calls, but using -Os does not. + The bad code is only generated when compiled with -Os. + + When the bad code is generated all code is okay except for the very last + instruction (a 'l.addc' in the l.jr delay slot). + Up to that point in execution, r11 and r12 contain the correct (expected) + values, but the execution of the final "l.addc" corrupts r11. + + This test ensures an l.addc is not in the output. Also, while confirming + this test we uncovered PR/90363, we use it to check for that as well. */ + +#include + +volatile static uint8_t g_doswap = 1; + +uint64_t swap_1 (uint64_t u64) { + uint32_t u64_lo, u64_hi, u64_tmp; + + u64_lo = u64 & 0xFFFFFFFF; + u64_hi = u64 >> 32; + + if (g_doswap) + { + u64_tmp = u64_lo; + u64_lo = u64_hi; + u64_hi = u64_tmp; + } + + u64 = u64_lo; + u64 += ((uint64_t) u64_hi << 32); + + return u64; +} + +/* Check to ensure the volatile load does not get zero extended. */ +/* { dg-final { scan-assembler-not "0xff" } } */ +/* { dg-final { scan-assembler-not "l.addc" } } */ From patchwork Wed Jul 3 03:33:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 1126595 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-504238-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="knsq7qdu"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WSRFQgv7"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45dmv23b9hz9s3Z for ; Wed, 3 Jul 2019 13:34:38 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=OJ1 QOUScGVBkuvrQkwU79kKZcpdGXoL+qGR+Kpu2nZUSe9pv5KouQo68Q4y5oG2Uqg+ uPn9wz1VSYnkn6YaqbCR4MT9O+u86WhHvcHvI2OA0seNoS4ZvTUuCUOwIeTUZVm7 IuMV7wpJzVRdoCymszkIaDvodrcFR4r3dT9X25i0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=fH2R+NyKX rbDTm9pP1R9Ret1Lp4=; b=knsq7qduz3YrHATqYT5jhsfczOI56XYFqYdIibW0c XBFuEDZO1TniB7RkkpOZY6iTMg64DZA1buRF5UgFt9M2sgQrsXZ6UOVArFZboZLB iNhHCuIAUys+JSAVkif6QKqwm/mbs0Zyajy/XY5egcCX0wfFooFvuoVdmAq2pn8A Ps= Received: (qmail 39119 invoked by alias); 3 Jul 2019 03:34:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 38465 invoked by uid 89); 3 Jul 2019 03:34:11 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=quotient, HX-Received:2a27, H*RU:209.85.214.193, HX-Spam-Relays-External:209.85.214.193 X-HELO: mail-pl1-f193.google.com Received: from mail-pl1-f193.google.com (HELO mail-pl1-f193.google.com) (209.85.214.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 03 Jul 2019 03:34:09 +0000 Received: by mail-pl1-f193.google.com with SMTP id e5so397164pls.13 for ; Tue, 02 Jul 2019 20:34:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M0AuKl6/tFOClcQ8E2AI6hBsJ2g1XLtBDY8c9fpA1c4=; b=WSRFQgv7FLbJh6MC27Ge+uYvLztvQLP7l2uwFLlYQHydbOL3lB+U3TPjspjMOHjeUi /vZIG0hkITu3X/pBCo9Jy2XGif0Kj+96OoCFnDQW/+hv42JNpUa2NZPibVEFKVYQSt7e /K0dOqZKK7+6bwQoNJvMcmf5lKQ5w4YYdjhKD37vosJLBMV9wizOZWGfdA0v/n1LEin1 VWvOJyn1LPaohazdti07lRYdMa39+77hhdWtmMuh0xhZKsL+HmTZq6ZqC0We99ddR7VL BR/rKl+l+LoeGKSu4dCvOCbkvdLIIw2KaM4s58Bd3MjMwRC58DFWUro0peHuYdHNK6QV teMA== Received: from localhost (g223.61-115-60.ppp.wakwak.ne.jp. [61.115.60.223]) by smtp.gmail.com with ESMTPSA id 191sm525522pfu.177.2019.07.02.20.34.07 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 02 Jul 2019 20:34:07 -0700 (PDT) From: Stafford Horne To: GCC patches Cc: Openrisc , Bernhard Reutner-Fischer , Jeff Law , Stafford Horne Subject: [PATCH v2 2/5] or1k: Fix issues with msoft-div Date: Wed, 3 Jul 2019 12:33:48 +0900 Message-Id: <20190703033351.11924-3-shorne@gmail.com> In-Reply-To: <20190703033351.11924-1-shorne@gmail.com> References: <20190703033351.11924-1-shorne@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Fixes bad assembly logic with software divide as reported by Richard Selvaggi. Also, add a basic test to verify the soft math works when enabled. gcc/testsuite/ChangeLog: PR target/90362 * gcc.target/or1k/div-mul-3.c: New test. libgcc/ChangeLog: PR target/90362 * config/or1k/lib1funcs.S (__udivsi3): Change l.sfeqi to l.sfeq and l.sfltsi to l.sflts equivalents as the immediate instructions are not available on every processor. Change a l.bnf to l.bf to fix logic issue. --- Changes since v1: - none gcc/testsuite/gcc.target/or1k/div-mul-3.c | 31 +++++++++++++++++++++++ libgcc/config/or1k/lib1funcs.S | 6 ++--- 2 files changed, 34 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-3.c diff --git a/gcc/testsuite/gcc.target/or1k/div-mul-3.c b/gcc/testsuite/gcc.target/or1k/div-mul-3.c new file mode 100644 index 00000000000..2c4f91b7e98 --- /dev/null +++ b/gcc/testsuite/gcc.target/or1k/div-mul-3.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msoft-div -msoft-mul" } */ + +struct testcase { + int a; + int b; + int c; + int expected; +}; + +struct testcase tests[] = { + {2, 200, 3, 133}, + {3, 300, 3, 300}, + {2, 500, 3, 333}, + {4, 250, 3, 333}, + {0, 0, 0, 0} +}; + +int calc (int a, int b, int c) { + return a * b / c; +} + +int main () { + int fail = 0; + struct testcase *tc; + + for (int i = 0; (tc = &tests[i], tc->c); i++) + fail |= (calc (tc->a, tc->b, tc->c) != tc->expected); + + return fail; +} diff --git a/libgcc/config/or1k/lib1funcs.S b/libgcc/config/or1k/lib1funcs.S index d2103923486..6d058977229 100644 --- a/libgcc/config/or1k/lib1funcs.S +++ b/libgcc/config/or1k/lib1funcs.S @@ -68,18 +68,18 @@ __udivmodsi3_internal: is not clobbered by this routine, and use that as to save a return address without creating a stack frame. */ - l.sfeqi r4, 0 /* division by zero; return 0. */ + l.sfeq r4, r0 /* division by zero; return 0. */ l.ori r11, r0, 0 /* initial quotient */ l.bf 9f l.ori r12, r3, 0 /* initial remainder */ /* Given X/Y, shift Y left until Y >= X. */ l.ori r6, r0, 1 /* mask = 1 */ -1: l.sfltsi r4, 0 /* y has msb set */ +1: l.sflts r4, r0 /* y has msb set */ l.bf 2f l.sfltu r4, r12 /* y < x */ l.add r4, r4, r4 /* y <<= 1 */ - l.bnf 1b + l.bf 1b l.add r6, r6, r6 /* mask <<= 1 */ /* Shift Y back to the right again, subtracting from X. */ From patchwork Wed Jul 3 03:33:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 1126596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[61.115.60.223]) by smtp.gmail.com with ESMTPSA id v23sm518684pff.185.2019.07.02.20.34.09 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 02 Jul 2019 20:34:10 -0700 (PDT) From: Stafford Horne To: GCC patches Cc: Openrisc , Bernhard Reutner-Fischer , Jeff Law , Stafford Horne Subject: [PATCH v2 3/5] or1k: Add mrori option, fix option docs Date: Wed, 3 Jul 2019 12:33:49 +0900 Message-Id: <20190703033351.11924-4-shorne@gmail.com> In-Reply-To: <20190703033351.11924-1-shorne@gmail.com> References: <20190703033351.11924-1-shorne@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes gcc/ChangeLog: * config.gcc (or1k*-*-*): Add mrori and mror to validation. * doc/invoke.texi (OpenRISC Options): Add mrori option, rewrite all documenation to be more clear. * config/or1k/elf.opt (mboard=, mnewlib): Rewrite documentation to be more clear. * config/or1k/or1k.opt (mrori): New option. (mhard-div, msoft-div, mhard-mul, msoft-mul, mcmov, mror, msext, msfimm, mshftimm): Rewrite documentation to be more clear. * config/or1k/or1k.md (insn_support): Add ror and rori. (enabled): Add conditions for ror and rori. (rotrsi3): Replace condition for shftimm with ror and rori. gcc/testsuite/ChangeLog: * gcc.target/or1k/ror-4.c: New file. * gcc.target/or1k/shftimm-1.c: Update test from rotate to shift as the shftimm option no longer controls rotate. --- Changes since v1: - new patch gcc/config.gcc | 1 + gcc/config/or1k/elf.opt | 6 +-- gcc/config/or1k/or1k.md | 12 +++-- gcc/config/or1k/or1k.opt | 56 +++++++++++++---------- gcc/doc/invoke.texi | 56 +++++++++++++---------- gcc/testsuite/gcc.target/or1k/ror-4.c | 8 ++++ gcc/testsuite/gcc.target/or1k/shftimm-1.c | 8 ++-- 7 files changed, 87 insertions(+), 60 deletions(-) create mode 100644 gcc/testsuite/gcc.target/or1k/ror-4.c diff --git a/gcc/config.gcc b/gcc/config.gcc index c281c418b28..aeab8b4544e 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2578,6 +2578,7 @@ or1k*-*-*) for or1k_multilib in ${or1k_multilibs}; do case ${or1k_multilib} in mcmov | msext | msfimm | \ + mror | mrori | \ mhard-div | mhard-mul | \ msoft-div | msoft-mul ) TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${or1k_multilib}" diff --git a/gcc/config/or1k/elf.opt b/gcc/config/or1k/elf.opt index 641b6ddd4be..2d4d1875d02 100644 --- a/gcc/config/or1k/elf.opt +++ b/gcc/config/or1k/elf.opt @@ -25,9 +25,9 @@ mboard= Target RejectNegative Joined -Configure board specific runtime. +Configure the newlib board specific runtime. The default is or1ksim. mnewlib Target RejectNegative -For compatibility, it's always newlib for elf now. - +This option is ignored; it is provided for compatibility purposes only. This +used to select linker and preprocessor options for use with newlib. diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md index 757d899c442..bbad593db40 100644 --- a/gcc/config/or1k/or1k.md +++ b/gcc/config/or1k/or1k.md @@ -63,7 +63,7 @@ "alu,st,ld,control,multi" (const_string "alu")) -(define_attr "insn_support" "class1,sext,sfimm,shftimm" (const_string "class1")) +(define_attr "insn_support" "class1,sext,sfimm,shftimm,ror,rori" (const_string "class1")) (define_attr "enabled" "" (cond [(eq_attr "insn_support" "class1") (const_int 1) @@ -72,7 +72,11 @@ (and (eq_attr "insn_support" "sfimm") (ne (symbol_ref "TARGET_SFIMM") (const_int 0))) (const_int 1) (and (eq_attr "insn_support" "shftimm") - (ne (symbol_ref "TARGET_SHFTIMM") (const_int 0))) (const_int 1)] + (ne (symbol_ref "TARGET_SHFTIMM") (const_int 0))) (const_int 1) + (and (eq_attr "insn_support" "ror") + (ne (symbol_ref "TARGET_ROR") (const_int 0))) (const_int 1) + (and (eq_attr "insn_support" "rori") + (ne (symbol_ref "TARGET_RORI") (const_int 0))) (const_int 1)] (const_int 0))) ;; Describe a user's asm statement. @@ -179,11 +183,11 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (rotatert:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "reg_or_u6_operand" "r,n")))] - "TARGET_ROR" + "TARGET_ROR || TARGET_RORI" "@ l.ror\t%0, %1, %2 l.rori\t%0, %1, %2" - [(set_attr "insn_support" "*,shftimm")]) + [(set_attr "insn_support" "ror,rori")]) (define_insn "andsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt index 7bdbd842dd4..c2f64c5dd45 100644 --- a/gcc/config/or1k/or1k.opt +++ b/gcc/config/or1k/or1k.opt @@ -21,47 +21,55 @@ ; See the GCC internals manual (options.texi) for a description of ; this file's format. -; Please try to keep this file in ASCII collating order. - mhard-div Target RejectNegative InverseMask(SOFT_DIV) -Use hardware divide instructions, use -msoft-div for emulation. +Enable generation of hardware divide (l.div, l.divu) instructions. This is the +default; use -msoft-div to override. + +msoft-div +Target RejectNegative Mask(SOFT_DIV) +Enable generation of binaries which use functions from libgcc to perform divide +operations. The default is -mhard-div. mhard-mul Target RejectNegative InverseMask(SOFT_MUL). -Use hardware multiply instructions, use -msoft-mul for emulation. +Enable generation of hardware multiply instructions (l.mul, l.muli) instructions. +This is the default; use -msoft-mul to override. + +msoft-mul +Target RejectNegative Mask(SOFT_MUL). +Enable generation of binaries which use functions from libgcc to perform +multiply operations. The default is -mhard-mul. mcmov Target RejectNegative Mask(CMOV) -Allows generation of binaries which use the l.cmov instruction. If your target -does not support this the compiler will generate the equivalent using set and -branch. +Enable generation of conditional move (l.cmov) instructions. By default the +equivalent will be generated using using set and branch. mror Target RejectNegative Mask(ROR) -Allows generation of binaries which use the l.rori instructions. +Enable generation of rotate right (l.ror) instructions. By default functions +from libgcc are used to perform rotate right operations. + +mrori +Target RejectNegative Mask(RORI) +Enable generation of rotate right with immediate (l.rori) instructions. By +default functions from libgcc are used to perform rotate right with immediate +operations. msext Target RejectNegative Mask(SEXT) -Allows generation of binaries which use sign-extension instructions. If your -target does not support this the compiler will use memory loads to perform sign -extension. +Enable generation of sign extension (l.ext*) instructions. By default memory +loads are used to perform sign extension. msfimm Target RejectNegative Mask(SFIMM) -Allows generation of binaries which use l.sf*i instructions. If your target -does not support this the compiler will generate instructions to store the -immediate to a register first. +Enable generation of compare and set flag with immediate (l.sf*i) instructions. +By default extra instructions will be generated to store the immediate to a +register first. mshftimm Target RejectNegative Mask(SHFTIMM) -Allows generation of binaries which support shifts and rotate instructions -supporting immediate arguments, for example l.rori. - -msoft-div -Target RejectNegative Mask(SOFT_DIV) -Use divide emulation. - -msoft-mul -Target RejectNegative Mask(SOFT_MUL). -Use multiply emulation. +Enable generation of shift with immediate (l.srai, l.srli, l.slli) instructions. +By default extra instructions will be generated to store the immediate to a +register first. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 6382a840281..1f1f73672bd 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1033,7 +1033,7 @@ Objective-C and Objective-C++ Dialects}. @emph{OpenRISC Options} @gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div @gol -msoft-mul -msoft-div @gol --mcmov -mror -msext -msfimm -mshftimm} +-mcmov -mror -mrori -msext -msfimm -mshftimm} @emph{PDP-11 Options} @gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol @@ -23632,50 +23632,56 @@ newlib board library linking. The default is @code{or1ksim}. @item -mnewlib @opindex mnewlib -For compatibility, it's always newlib for elf now. +This option is ignored; it is for compatibility purposes only. This used to +select linker and preprocessor options for use with newlib. -@item -mhard-div +@item -msoft-div +@itemx -mhard-div +@opindex msoft-div @opindex mhard-div -Generate code for hardware which supports divide instructions. This is the -default. +Select software or hardware divide (@code{l.div}, @code{l.divu}) instructions. +This default is hardware divide. -@item -mhard-mul +@item -msoft-mul +@itemx -mhard-mul +@opindex msoft-mul @opindex mhard-mul -Generate code for hardware which supports multiply instructions. This is the -default. +Select software or hardware multiply (@code{l.mul}, @code{l.muli}) instructions. +This default is hardware multiply. @item -mcmov @opindex mcmov -Generate code for hardware which supports the conditional move (@code{l.cmov}) -instruction. +Enable generation of conditional move (@code{l.cmov}) instructions. By +default the equivalent will be generated using using set and branch. @item -mror @opindex mror -Generate code for hardware which supports rotate right instructions. +Enable generation of rotate right (@code{l.ror}) instructions. By default +functions from @file{libgcc} are used to perform rotate right operations. + +@item -mrori +@opindex mrori +Enable generation of rotate right with immediate (@code{l.rori}) instructions. +By default functions from @file{libgcc} are used to perform rotate right with +immediate operations. @item -msext @opindex msext -Generate code for hardware which supports sign-extension instructions. +Enable generation of sign extension (@code{l.ext*}) instructions. By default +memory loads are used to perform sign extension. @item -msfimm @opindex msfimm -Generate code for hardware which supports set flag immediate (@code{l.sf*i}) -instructions. +Enable generation of compare and set flag with immediate (@code{l.sf*i}) +instructions. By default extra instructions will be generated to store the +immediate to a register first. @item -mshftimm @opindex mshftimm -Generate code for hardware which supports shift immediate related instructions -(i.e. @code{l.srai}, @code{l.srli}, @code{l.slli}, @code{1.rori}). Note, to -enable generation of the @code{l.rori} instruction the @option{-mror} flag must -also be specified. +Enable generation of shift with immediate (@code{l.srai}, @code{l.srli}, +@code{l.slli}) instructions. By default extra instructions will be generated +to store the immediate to a register first. -@item -msoft-div -@opindex msoft-div -Generate code for hardware which requires divide instruction emulation. - -@item -msoft-mul -@opindex msoft-mul -Generate code for hardware which requires multiply instruction emulation. @end table diff --git a/gcc/testsuite/gcc.target/or1k/ror-4.c b/gcc/testsuite/gcc.target/or1k/ror-4.c new file mode 100644 index 00000000000..7489ce5b6a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/or1k/ror-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mrori -O2" } */ + +unsigned int rotate6 (unsigned int a) { + return ( a >> 6 ) | ( a << ( 32 - 6 ) ); +} + +/* { dg-final { scan-assembler "l.rori" } } */ diff --git a/gcc/testsuite/gcc.target/or1k/shftimm-1.c b/gcc/testsuite/gcc.target/or1k/shftimm-1.c index be8d9e8b895..3a8dc06df79 100644 --- a/gcc/testsuite/gcc.target/or1k/shftimm-1.c +++ b/gcc/testsuite/gcc.target/or1k/shftimm-1.c @@ -1,8 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-mror -mshftimm -O2" } */ +/* { dg-options "-mshftimm -O2" } */ -unsigned int rotate6 (unsigned int a) { - return ( a >> 6 ) | ( a << ( 32 - 6 ) ); +unsigned int shift6 (unsigned int a) { + return a << 6; } -/* { dg-final { scan-assembler "l.rori" } } */ +/* { dg-final { scan-assembler "l.slli" } } */ From patchwork Wed Jul 3 03:33:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 1126597 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-504240-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="MI+qfeTA"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Itgz/rhK"; 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[61.115.60.223]) by smtp.gmail.com with ESMTPSA id s193sm509109pgc.32.2019.07.02.20.34.12 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 02 Jul 2019 20:34:12 -0700 (PDT) From: Stafford Horne To: GCC patches Cc: Openrisc , Bernhard Reutner-Fischer , Jeff Law , Stafford Horne Subject: [PATCH v2 4/5] or1k: Initial support for FPU Date: Wed, 3 Jul 2019 12:33:50 +0900 Message-Id: <20190703033351.11924-5-shorne@gmail.com> In-Reply-To: <20190703033351.11924-1-shorne@gmail.com> References: <20190703033351.11924-1-shorne@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes This adds support for OpenRISC hardware floating point instructions. This is enabled with the -mhard-float option. Double-prevision floating point operations work using register pairing as specified in: https://openrisc.io/proposals/orfpx64a32. This has just been added in the OpenRISC architecture specification 1.3. This is enabled with the -mdouble-float option. Not all architectures support unordered comparisons so an option, -munordered-float is added. Currently OpenRISC does not support sf/df or df/sf conversions, but this has also just been added in architecture specification 1.3. gcc/ChangeLog: * config.gcc (or1k*-*-*): Add mhard-float, mdouble-float, msoft-float and munordered-float validations. * config/or1k/constraints.md (d): New register constraint. * config/or1k/predicates.md (fp_comparison_operator): New. * config/or1k/or1k.c (or1k_print_operand): Add support for printing 'd' operands. (or1k_expand_compare): Normalize unordered comparisons. * config/or1k/or1k.h (reg_class): Define DOUBLE_REGS. (REG_CLASS_NAMES): Add "DOUBLE_REGS". (REG_CLASS_CONTENTS): Add contents for DOUBLE_REGS. * config/or1k/or1k.md (type): Add fpu. (fpu): New instruction reservation. (F, f, fr, fi, FI, FOP, fop): New. (3): New ALU instruction definition. (float2): New conversion instruction definition. (fix_trunc2): New conversion instruction definition. (fpcmpcc): New code iterator. (*sf_fp_insn): New instruction definition. (cstore4): New expand definition. (cbranch4): New expand definition. * config/or1k/or1k.opt (msoft-float, mhard-float, mdouble-float, munordered-float): New options. * doc/invoke.texi: Document msoft-float, mhard-float, mdouble-float and munordered-float. --- Changes since v1: - User register pairs for 64-bit ops. See or1k_print_operand gcc/config.gcc | 1 + gcc/config/or1k/constraints.md | 4 ++ gcc/config/or1k/or1k.c | 36 ++++++++++- gcc/config/or1k/or1k.h | 3 + gcc/config/or1k/or1k.md | 111 ++++++++++++++++++++++++++++++++- gcc/config/or1k/or1k.opt | 22 +++++++ gcc/config/or1k/predicates.md | 5 ++ gcc/doc/invoke.texi | 21 +++++++ 8 files changed, 199 insertions(+), 4 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index aeab8b4544e..1678109131f 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2579,6 +2579,7 @@ or1k*-*-*) case ${or1k_multilib} in mcmov | msext | msfimm | \ mror | mrori | \ + mhard-float | mdouble-float | munordered-float | msoft-float | \ mhard-div | mhard-mul | \ msoft-div | msoft-mul ) TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${or1k_multilib}" diff --git a/gcc/config/or1k/constraints.md b/gcc/config/or1k/constraints.md index 93da8c058c6..8cac7eb5329 100644 --- a/gcc/config/or1k/constraints.md +++ b/gcc/config/or1k/constraints.md @@ -24,6 +24,7 @@ ; We use: ; c - sibcall registers +; d - double pair base registers (excludes r0, r30 and r31 which overflow) ; I - constant signed 16-bit ; K - constant unsigned 16-bit ; M - constant signed 16-bit shifted left 16-bits (l.movhi) @@ -32,6 +33,9 @@ (define_register_constraint "c" "SIBCALL_REGS" "Registers which can hold a sibling call address") +(define_register_constraint "d" "DOUBLE_REGS" + "Registers which can be used for double reg pairs.") + ;; Immediates (define_constraint "I" "A signed 16-bit immediate in the range -32768 to 32767." diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c index 54c9e804ea5..d90826b75ca 100644 --- a/gcc/config/or1k/or1k.c +++ b/gcc/config/or1k/or1k.c @@ -1226,6 +1226,17 @@ or1k_print_operand (FILE *file, rtx x, int code) output_operand_lossage ("invalid %%H value"); break; + case 'd': + if (REG_P (x)) + if (GET_MODE (x) == DFmode || GET_MODE (x) == DImode) + fprintf (file, "%s,%s", reg_names[REGNO (operand)], + reg_names[REGNO (operand) + 1]); + else + fprintf (file, "%s", reg_names[REGNO (operand)]); + else + output_operand_lossage ("invalid %%d value"); + break; + case 'h': print_reloc (file, x, 0, RKIND_HI); break; @@ -1435,21 +1446,42 @@ void or1k_expand_compare (rtx *operands) { rtx sr_f = gen_rtx_REG (BImode, SR_F_REGNUM); + rtx_code cmp_code = GET_CODE (operands[0]); + bool flag_check_ne = true; /* The RTL may receive an immediate in argument 1 of the compare, this is not supported unless we have l.sf*i instructions, force them into registers. */ if (!TARGET_SFIMM) XEXP (operands[0], 1) = force_reg (SImode, XEXP (operands[0], 1)); + /* Normalize comparison operators to ones OpenRISC support. */ + switch (cmp_code) + { + case LTGT: + cmp_code = UNEQ; + flag_check_ne = false; + break; + + case ORDERED: + cmp_code = UNORDERED; + flag_check_ne = false; + break; + + default: + break; + } + /* Emit the given comparison into the Flag bit. */ PUT_MODE (operands[0], BImode); + PUT_CODE (operands[0], cmp_code); emit_insn (gen_rtx_SET (sr_f, operands[0])); /* Adjust the operands for use in the caller. */ - operands[0] = gen_rtx_NE (VOIDmode, sr_f, const0_rtx); + operands[0] = flag_check_ne ? gen_rtx_NE (VOIDmode, sr_f, const0_rtx) + : gen_rtx_EQ (VOIDmode, sr_f, const0_rtx); operands[1] = sr_f; operands[2] = const0_rtx; -} + } /* Expand the patterns "call", "sibcall", "call_value" and "sibcall_value". Expands a function call where argument RETVAL is an optional RTX providing diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h index 6dda230f217..7588c187e5f 100644 --- a/gcc/config/or1k/or1k.h +++ b/gcc/config/or1k/or1k.h @@ -189,6 +189,7 @@ enum reg_class { NO_REGS, SIBCALL_REGS, + DOUBLE_REGS, GENERAL_REGS, FLAG_REGS, ALL_REGS, @@ -200,6 +201,7 @@ enum reg_class #define REG_CLASS_NAMES { \ "NO_REGS", \ "SIBCALL_REGS", \ + "DOUBLE_REGS", \ "GENERAL_REGS", \ "FLAG_REGS", \ "ALL_REGS" } @@ -212,6 +214,7 @@ enum reg_class #define REG_CLASS_CONTENTS \ { { 0x00000000, 0x00000000 }, \ { SIBCALL_REGS_MASK, 0 }, \ + { 0x7ffffefe, 0x00000000 }, \ { 0xffffffff, 0x00000003 }, \ { 0x00000000, 0x00000004 }, \ { 0xffffffff, 0x00000007 } \ diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md index bbad593db40..728ef96b99c 100644 --- a/gcc/config/or1k/or1k.md +++ b/gcc/config/or1k/or1k.md @@ -60,7 +60,7 @@ (define_attr "length" "" (const_int 4)) (define_attr "type" - "alu,st,ld,control,multi" + "alu,st,ld,control,multi,fpu" (const_string "alu")) (define_attr "insn_support" "class1,sext,sfimm,shftimm,ror,rori" (const_string "class1")) @@ -97,6 +97,10 @@ (define_insn_reservation "control" 1 (eq_attr "type" "control") "cpu") +(define_insn_reservation "fpu" 2 + (eq_attr "type" "fpu") + "cpu") + ; Define delay slots for any branch (define_delay (eq_attr "type" "control") @@ -159,6 +163,47 @@ "" "l.sub\t%0, %r1, %2") +;; ------------------------------------------------------------------------- +;; Floating Point Arithmetic instructions +;; ------------------------------------------------------------------------- + +;; Mode iterator for single/double float +(define_mode_iterator F [(SF "TARGET_HARD_FLOAT") + (DF "TARGET_DOUBLE_FLOAT")]) +(define_mode_attr f [(SF "s") (DF "d")]) +(define_mode_attr fr [(SF "r") (DF "d")]) +(define_mode_attr fi [(SF "si") (DF "di")]) +(define_mode_attr FI [(SF "SI") (DF "DI")]) + +;; Basic arithmetic instructions +(define_code_iterator FOP [plus minus mult div]) +(define_code_attr fop [(plus "add") (minus "sub") (mult "mul") (div "div")]) + +(define_insn "3" + [(set (match_operand:F 0 "register_operand" "=") + (FOP:F (match_operand:F 1 "register_operand" "") + (match_operand:F 2 "register_operand" "")))] + "TARGET_HARD_FLOAT" + "lf..\t%d0, %d1, %d2" + [(set_attr "type" "fpu")]) + +;; Basic float<->int conversion +(define_insn "float2" + [(set (match_operand:F 0 "register_operand" "=") + (float:F + (match_operand: 1 "register_operand" "")))] + "TARGET_HARD_FLOAT" + "lf.itof.\t%d0, %d1" + [(set_attr "type" "fpu")]) + +(define_insn "fix_trunc2" + [(set (match_operand: 0 "register_operand" "=") + (fix: + (match_operand:F 1 "register_operand" "")))] + "TARGET_HARD_FLOAT" + "lf.ftoi.\t%d0, %d1" + [(set_attr "type" "fpu")]) + ;; ------------------------------------------------------------------------- ;; Logical operators ;; ------------------------------------------------------------------------- @@ -380,7 +425,7 @@ (define_code_iterator intcmpcc [ne eq lt ltu gt gtu ge le geu leu]) (define_code_attr insn [(ne "ne") (eq "eq") (lt "lts") (ltu "ltu") (gt "gts") (gtu "gtu") (ge "ges") (le "les") - (geu "geu") (leu "leu") ]) + (geu "geu") (leu "leu")]) (define_insn "*sf_insn" [(set (reg:BI SR_F_REGNUM) @@ -392,6 +437,36 @@ l.sfi\t%r0, %1" [(set_attr "insn_support" "*,sfimm")]) +;; Support FP comparisons too + +;; The OpenRISC FPU supports these comparisons: +;; +;; lf.sfeq.{d,s} - equality, r r, double or single precision +;; lf.sfge.{d,s} - greater than or equal, r r, double or single precision +;; lf.sfgt.{d,s} - greater than, r r, double or single precision +;; lf.sfle.{d,s} - less than or equal, r r, double or single precision +;; lf.sflt.{d,s} - less than, r r, double or single precision +;; lf.sfne.{d,s} - not equal, r r, double or single precision +;; +;; Double precision is only supported on some hardware. Only register/register +;; comparisons are supported. All comparisons are signed. + +(define_code_iterator fpcmpcc [ne eq lt gt ge le uneq unle unlt ungt unge + unordered]) +(define_code_attr fpcmpinsn [(ne "ne") (eq "eq") (lt "lt") (gt "gt") (ge "ge") + (le "le") (uneq "ueq") (unle "ule") (unlt "ult") + (ungt "ugt") (unge "uge") (unordered "un")]) + + +(define_insn "*sf_fp_insn" + [(set (reg:BI SR_F_REGNUM) + (fpcmpcc:BI (match_operand:F 0 "register_operand" "") + (match_operand:F 1 "register_operand" "")))] + "TARGET_HARD_FLOAT" + "lf.sf.\t%d0, %d1" + [(set_attr "type" "fpu")]) + + ;; ------------------------------------------------------------------------- ;; Conditional Store instructions ;; ------------------------------------------------------------------------- @@ -412,6 +487,23 @@ DONE; }) +;; Support FP cstores too +(define_expand "cstore4" + [(set (match_operand:SI 0 "register_operand" "") + (if_then_else:F + (match_operator 1 "fp_comparison_operator" + [(match_operand:F 2 "register_operand" "") + (match_operand:F 3 "register_operand" "")]) + (match_dup 0) + (const_int 0)))] + "TARGET_HARD_FLOAT" +{ + or1k_expand_compare (operands + 1); + PUT_MODE (operands[1], SImode); + emit_insn (gen_rtx_SET (operands[0], operands[1])); + DONE; +}) + ;; Being able to "copy" SR_F to a general register is helpful for ;; the atomic insns, wherein the usual usage is to test the success ;; of the compare-and-swap. Representing the operation in this way, @@ -505,6 +597,21 @@ or1k_expand_compare (operands); }) +;; Support FP branching + +(define_expand "cbranch4" + [(set (pc) + (if_then_else + (match_operator 0 "fp_comparison_operator" + [(match_operand:F 1 "register_operand" "") + (match_operand:F 2 "register_operand" "")]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "TARGET_HARD_FLOAT" +{ + or1k_expand_compare (operands); +}) + (define_insn "*cbranch" [(set (pc) (if_then_else diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt index c2f64c5dd45..15085fafa3f 100644 --- a/gcc/config/or1k/or1k.opt +++ b/gcc/config/or1k/or1k.opt @@ -41,6 +41,28 @@ Target RejectNegative Mask(SOFT_MUL). Enable generation of binaries which use functions from libgcc to perform multiply operations. The default is -mhard-mul. +msoft-float +Target RejectNegative InverseMask(HARD_FLOAT) +Enable generation of binaries which use functions from libgcc to perform +floating point operations. This is the default; use -mhard-float to override. + +mhard-float +Target RejectNegative Mask(HARD_FLOAT) +Enable generation of hardware floating point instructions. The default is +-msoft-float. + +mdouble-float +Target Mask(DOUBLE_FLOAT) +When -mhard-float is selected, enables generation of double-precision floating +point instructions. By default functions from libgcc are used to perform +double-precision floating point operations. + +munordered-float +Target RejectNegative Mask(FP_UNORDERED) +When -mhard-float is selected, enables generation of unordered floating point +compare and set flag (lf.sfun*) instructions. By default functions from libgcc +are used to perform unordered floating point compare and set flag operations. + mcmov Target RejectNegative Mask(CMOV) Enable generation of conditional move (l.cmov) instructions. By default the diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md index b895f1b4228..a1231dbad33 100644 --- a/gcc/config/or1k/predicates.md +++ b/gcc/config/or1k/predicates.md @@ -83,6 +83,11 @@ (define_predicate "equality_comparison_operator" (match_code "ne,eq")) +(define_predicate "fp_comparison_operator" + (if_then_else (match_test "TARGET_FP_UNORDERED") + (match_operand 0 "comparison_operator") + (match_operand 0 "ordered_comparison_operator"))) + ;; Borrowed from rs6000 ; Return true if the operand is in volatile memory. Note that during the ;; RTL generation phase, memory_operand does not return TRUE for volatile diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 1f1f73672bd..379e4a9b731 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1033,6 +1033,7 @@ Objective-C and Objective-C++ Dialects}. @emph{OpenRISC Options} @gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div @gol -msoft-mul -msoft-div @gol +-msoft-float -mhard-float -mdouble-float -munordered-float @gol -mcmov -mror -mrori -msext -msfimm -mshftimm} @emph{PDP-11 Options} @@ -23649,6 +23650,26 @@ This default is hardware divide. Select software or hardware multiply (@code{l.mul}, @code{l.muli}) instructions. This default is hardware multiply. +@item -msoft-float +@itemx -mhard-float +@opindex msoft-float +@opindex mhard-float +Select software or hardware for floating point operations. +The default is software. + +@item -mdouble-float +@opindex mdouble-float +When @option{-mhard-float} is selected, enables generation of double-precision +floating point instructions. By default functions from @file{libgcc} are used +to perform double-precision floating point operations. + +@item -munordered-float +@opindex munordered-float +When @option{-mhard-float} is selected, enables generation of unordered +floating point compare and set flag (@code{lf.sfun*}) instructions. By default +functions from @file{libgcc} are used to perform unordered floating point +compare and set flag operations. + @item -mcmov @opindex mcmov Enable generation of conditional move (@code{l.cmov}) instructions. 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[61.115.60.223]) by smtp.gmail.com with ESMTPSA id v27sm531659pgn.76.2019.07.02.20.34.15 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 02 Jul 2019 20:34:15 -0700 (PDT) From: Stafford Horne To: GCC patches Cc: Openrisc , Bernhard Reutner-Fischer , Jeff Law , Stafford Horne Subject: [PATCH v2 5/5] or1k: only force reg for immediates Date: Wed, 3 Jul 2019 12:33:51 +0900 Message-Id: <20190703033351.11924-6-shorne@gmail.com> In-Reply-To: <20190703033351.11924-1-shorne@gmail.com> References: <20190703033351.11924-1-shorne@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes The force_reg in or1k_expand_compare is hard coded for SImode, which is fine as this used to only be used on SI expands. However, with FP support this will cause issues. In general we should only force the right hand operand to a register if its an immediate. This patch adds an condition to check for that. gcc/ChangeLog: * config/or1k/or1k.c (or1k_expand_compare): Check for int before force_reg. --- Changes since v1: - none gcc/config/or1k/or1k.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c index d90826b75ca..e4aff83cec7 100644 --- a/gcc/config/or1k/or1k.c +++ b/gcc/config/or1k/or1k.c @@ -1446,13 +1446,15 @@ void or1k_expand_compare (rtx *operands) { rtx sr_f = gen_rtx_REG (BImode, SR_F_REGNUM); + rtx righthand_op = XEXP (operands[0], 1); rtx_code cmp_code = GET_CODE (operands[0]); bool flag_check_ne = true; - /* The RTL may receive an immediate in argument 1 of the compare, this is not - supported unless we have l.sf*i instructions, force them into registers. */ - if (!TARGET_SFIMM) - XEXP (operands[0], 1) = force_reg (SImode, XEXP (operands[0], 1)); + /* Integer RTL may receive an immediate in argument 1 of the compare, this is + not supported unless we have l.sf*i instructions, force them into + registers. */ + if (!TARGET_SFIMM && CONST_INT_P (righthand_op)) + XEXP (operands[0], 1) = force_reg (SImode, righthand_op); /* Normalize comparison operators to ones OpenRISC support. */ switch (cmp_code)