From patchwork Fri Nov 3 10:10:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 833751 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pOBy/AmM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ySyVP3MkBz9s8J for ; Fri, 3 Nov 2017 21:14:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1EC8BC21DDF; Fri, 3 Nov 2017 10:13:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AC55CC21E0C; Fri, 3 Nov 2017 10:11:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B72A6C21C59; Fri, 3 Nov 2017 10:11:03 +0000 (UTC) Received: from mail-wr0-f195.google.com (mail-wr0-f195.google.com [209.85.128.195]) by lists.denx.de (Postfix) with ESMTPS id 47A93C21C45 for ; Fri, 3 Nov 2017 10:11:03 +0000 (UTC) Received: by mail-wr0-f195.google.com with SMTP id o44so2013781wrf.11 for ; Fri, 03 Nov 2017 03:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=F/MzGKyoQwVaBYqzafNR62tGiRsMsWfAud+pEbIymUw=; b=pOBy/AmMW4JHTp/+VuHWTB6gPuYbuBM7XPyt0iB3ltsdxOrY1OZm7lPeZCDWeGbmgt GENpVuvait+7FXqyrAAiWVMZOd67zCybkcxdgjWQmLEnKkCUerFiBY/BLv5Zg6o/CzsE dSaujcegTMgphHw1tfcSugQ8cRfSuKXpDa4qtmo8yGQ2pxl+wDfvntAFRw6h+1PQ6VIm 0mcbOujL2Cao2PSxYSstiqHbD1serCTs/N/sWfZ23/j9KcqYpc26gcsmP1KSOq5WWlUH KulJ5TsYYknT9bgdirKUilMA+C7nSWZ52EmN1tXLqKWpZzk1faZK69Ij/KKQQkx6tWkC 2rmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=F/MzGKyoQwVaBYqzafNR62tGiRsMsWfAud+pEbIymUw=; b=pbLQHN8M/pmKGAYe+Xh3z9L+YN+i+d3BmOk+DnvlKJVgZgkCalewK0mTWsWWXjZNMZ GqBbe84om2x6Q0tm6nZIUcyJDx3TchSHPJ1i3gl7EEPTJawwa0XuA/qh6neJOM9e2sX+ vctxrcXIr3iU77o6Pa2nuJ87FQF5atWd7zX3C+rLoTy6Ys2mSm7eZYXNrMlVxTz3tJR2 sk9H58gf2SMd6BiRsEH0/3aydjvtwoy6a7X2pWOrFBLAhq2ocSlN/yY8yUsW9E5+kuU5 tvwX3M6+rv3nvUeeKp1liGHRpUBYonJUG3YGkuY8rFXVaxLI6SktQp8dOfls3PCsZz4p 0Slg== X-Gm-Message-State: AMCzsaVqiDLlV26nqLl15Sa9DW4sSv6ANTrKvM355uO6DjP7i6p9I3au SaF/IcGEgqeUl4x8xgauQYvCbA== X-Google-Smtp-Source: ABhQp+QP/G6mOxpc9legPchV2c11zVWwX/U6Zec0asZWJVJ3Xj5FipliG3GIx0aCsisrGcp588NYaw== X-Received: by 10.223.151.51 with SMTP id r48mr5452037wrb.164.1509703862718; Fri, 03 Nov 2017 03:11:02 -0700 (PDT) Received: from hades (host86-156-77-147.range86-156.btcentralplus.com. [86.156.77.147]) by smtp.gmail.com with ESMTPSA id 128sm2399338wmi.28.2017.11.03.03.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 03:10:59 -0700 (PDT) From: Martyn Welch X-Google-Original-From: Martyn Welch Received: from martyn by hades with local (Exim 4.84_2) (envelope-from ) id 1eAYwD-0002bI-QV; Fri, 03 Nov 2017 10:10:57 +0000 To: u-boot@lists.denx.de Date: Fri, 3 Nov 2017 10:10:48 +0000 Message-Id: <1509703855-9948-2-git-send-email-martyn.welch@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> References: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> Cc: Nandor Han Subject: [U-Boot] [PATCH v4 1/8] imx: mxc_i2c: tweak the i2c transfer method X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Nandor Han Tweak the i2c transfer to work for devices that want to read data without addressing a register. Signed-off-by: Nandor Han Signed-off-by: Martyn Welch Acked-by: Heiko Schocher Cc: Heiko Schocher Cc: Stefano Babic --- Changes for v2: - Replacing '!= -1' with '>= 0'. drivers/i2c/mxc_i2c.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index abf1da2..205274e 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -317,16 +317,19 @@ static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip, temp |= I2CR_MTX | I2CR_TX_NO_AK; writeb(temp, base + (I2CR << reg_shift)); - /* write slave address */ - ret = tx_byte(i2c_bus, chip << 1); - if (ret < 0) - return ret; - - while (alen--) { - ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff); + if (alen >= 0) { + /* write slave address */ + ret = tx_byte(i2c_bus, chip << 1); if (ret < 0) return ret; + + while (alen--) { + ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff); + if (ret < 0) + return ret; + } } + return 0; } @@ -537,9 +540,11 @@ static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, if (ret < 0) return ret; - temp = readb(base + (I2CR << reg_shift)); - temp |= I2CR_RSTA; - writeb(temp, base + (I2CR << reg_shift)); + if (alen >= 0) { + temp = readb(base + (I2CR << reg_shift)); + temp |= I2CR_RSTA; + writeb(temp, base + (I2CR << reg_shift)); + } ret = tx_byte(i2c_bus, (chip << 1) | 1); if (ret < 0) { From patchwork Fri Nov 3 10:10:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 833750 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZrVX2kD2"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ySySy3m3mz9sBW for ; Fri, 3 Nov 2017 21:13:06 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3B20CC21D99; Fri, 3 Nov 2017 10:12:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9FBA3C21DEB; Fri, 3 Nov 2017 10:11:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4D73FC21CEC; Fri, 3 Nov 2017 10:11:03 +0000 (UTC) Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by lists.denx.de (Postfix) with ESMTPS id 0078DC21CB3 for ; Fri, 3 Nov 2017 10:11:02 +0000 (UTC) Received: by mail-wm0-f68.google.com with SMTP id t139so418895wmt.1 for ; Fri, 03 Nov 2017 03:11:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=8cgorcsu+QS8CAb+9wcosJXR2Pi7yswJL+/ThK5Lei4=; b=ZrVX2kD2HV7uOh1oeNpbeGzh3SXzd/Un/3ff0rx1TwHsahEui+E26AG5dnJ5QsiAkP ZOKCny2Ryngh3Dj1W2DAsV7eGMYvysxagoU48od5mNM6TI/91y7uBdffp1kf4OAbtpbh 9JRvYFVlx2OMQYZRf9IOZ29Qu59fvNN730/OBg0fvEG02Y0vPn9AT2K3G7K8Oy0/0rYT /vI5ElvkqmT3ISNws6GJuq4CO0zmE4O6myxpuC+C7Qv/cZORB3/qJ5aK9e9REjpYfHqA CmVi+FmdlpSiq8jGoE2XGAO6PSUDJhBGFfy5r/i7XVD7/HXqsp7Wf0QWIh/vBYoa5mmG rpOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=8cgorcsu+QS8CAb+9wcosJXR2Pi7yswJL+/ThK5Lei4=; b=YeV9/pR+iHIhNW1lVCBnVd0ddOr1PwBR60sB+zdZk24TuKUV3QHbUtbs4vVwAYtw2K cshpgT1dloHCMZe6aDI4+QTX+8gKx+fwLE9zTo1TTldUp0O/e701cPy5OtqpZ+rvTGH6 +QNWdniXBVd8ceWlBiZTP8aOTPFF3vOgdHDZdUH3KL2EUMRWfgwpNlAFdfWLgqrTbX95 clAXP1YxIYoShmB+X47dIBbSLvs7U9o1q2rOi4iUEyC6OvrI0SEez7LtO6XAYn2Gl+pR iP4jFIuvNLkqQAiJJd2a5dvTrIVwqQmsjNQEoAHKyQ8lpEeBvveed268rusYD36Aj988 uVtw== X-Gm-Message-State: AMCzsaXhcTYaKyirgYNszI704XsxSHhmeqEkuvDB2bIPCsKmhFB+62RJ hDXZgXqc1Xy7XLD7XC8I42FINg== X-Google-Smtp-Source: ABhQp+QD6/FatTpJcmpYNtnQ5WFpO6JQKe64KXYpLNh0zhRBOD0p/4Xl45GzXx8N1ljfStNpmt1gPg== X-Received: by 10.28.21.10 with SMTP id 10mr3684598wmv.41.1509703861380; Fri, 03 Nov 2017 03:11:01 -0700 (PDT) Received: from hades (host86-156-77-147.range86-156.btcentralplus.com. [86.156.77.147]) by smtp.gmail.com with ESMTPSA id q124sm3050059wmg.18.2017.11.03.03.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 03:10:59 -0700 (PDT) From: Martyn Welch X-Google-Original-From: Martyn Welch Received: from martyn by hades with local (Exim 4.84_2) (envelope-from ) id 1eAYwD-0002bL-Qr; Fri, 03 Nov 2017 10:10:57 +0000 To: u-boot@lists.denx.de Date: Fri, 3 Nov 2017 10:10:49 +0000 Message-Id: <1509703855-9948-3-git-send-email-martyn.welch@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> References: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> Cc: Ian Ray Subject: [U-Boot] [PATCH v4 2/8] ext4: recover from filesystem corruption when reading X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ian Ray Some fixes when reading EXT files and directory entries were identified after using e2fuzz to corrupt an EXT3 filesystem: - Stop reading directory entries if the offset becomes badly aligned. - Avoid overwriting memory by clamping the length used to zero the buffer in ext4fs_read_file. Also sanity check blocksize. Signed-off-by: Ian Ray Signed-off-by: Martyn Welch --- fs/ext4/ext4_common.c | 10 ++++++++++ fs/ext4/ext4fs.c | 10 +++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 31952f4..dac9545 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -660,6 +660,11 @@ static int search_dir(struct ext2_inode *parent_inode, char *dirname) offset = 0; do { + if (offset & 3) { + printf("Badly aligned ext2_dirent\n"); + break; + } + dir = (struct ext2_dirent *)(block_buffer + offset); direntname = (char*)(dir) + sizeof(struct ext2_dirent); @@ -880,6 +885,11 @@ static int unlink_filename(char *filename, unsigned int blknr) offset = 0; do { + if (offset & 3) { + printf("Badly aligned ext2_dirent\n"); + break; + } + previous_dir = dir; dir = (struct ext2_dirent *)(block_buffer + offset); direntname = (char *)(dir) + sizeof(struct ext2_dirent); diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index b0c7303..9ee2caf 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -64,6 +64,9 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, char *delayed_buf = NULL; short status; + if (blocksize <= 0) + return -1; + /* Adjust len so it we can't read past the end of the file. */ if (len + pos > filesize) len = (filesize - pos); @@ -127,6 +130,7 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, (blockend >> log2blksz); } } else { + int n; if (previous_block_number != -1) { /* spill */ status = ext4fs_devread(delayed_start, @@ -137,7 +141,11 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, return -1; previous_block_number = -1; } - memset(buf, 0, blocksize - skipfirst); + /* Zero no more than `len' bytes. */ + n = blocksize - skipfirst; + if (n > len) + n = len; + memset(buf, 0, n); } buf += blocksize - skipfirst; } From patchwork Fri Nov 3 10:10:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 833747 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[86.156.77.147]) by smtp.gmail.com with ESMTPSA id c37sm12187914wra.73.2017.11.03.03.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 03:10:59 -0700 (PDT) From: Martyn Welch X-Google-Original-From: Martyn Welch Received: from martyn by hades with local (Exim 4.84_2) (envelope-from ) id 1eAYwD-0002bP-R8; Fri, 03 Nov 2017 10:10:57 +0000 To: u-boot@lists.denx.de Date: Fri, 3 Nov 2017 10:10:50 +0000 Message-Id: <1509703855-9948-4-git-send-email-martyn.welch@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> References: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> Subject: [U-Boot] [PATCH v4 3/8] pwm: imx: Enable PWM support on i.MX53 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add missing parts for i.MX53 PWM support Acked-by: Nandor Han Signed-off-by: Martyn Welch --- Changes for v4: - Removed ifdef. arch/arm/include/asm/arch-mx5/imx-regs.h | 17 +++++++++++++++++ drivers/pwm/pwm-imx-util.c | 2 ++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 3e79fa3..2b0dc1e 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -508,6 +508,23 @@ struct fuse_bank4_regs { }; #endif +#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) +#define PWMCR_DOZEEN (1 << 24) +#define PWMCR_WAITEN (1 << 23) +#define PWMCR_DBGEN (1 << 22) +#define PWMCR_CLKSRC_IPG_HIGH (2 << 16) +#define PWMCR_CLKSRC_IPG (1 << 16) +#define PWMCR_EN (1 << 0) + +struct pwm_regs { + u32 cr; + u32 sr; + u32 ir; + u32 sar; + u32 pr; + u32 cnr; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c index 534dd8e..97ac0c8 100644 --- a/drivers/pwm/pwm-imx-util.c +++ b/drivers/pwm/pwm-imx-util.c @@ -23,10 +23,12 @@ struct pwm_regs *pwm_id_to_reg(int pwm_id) return (struct pwm_regs *)PWM1_BASE_ADDR; case 1: return (struct pwm_regs *)PWM2_BASE_ADDR; +#ifdef CONFIG_MX6 case 2: return (struct pwm_regs *)PWM3_BASE_ADDR; case 3: return (struct pwm_regs *)PWM4_BASE_ADDR; +#endif #ifdef CONFIG_MX6SX case 4: return (struct pwm_regs *)PWM5_BASE_ADDR; From patchwork Fri Nov 3 10:10:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 833753 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[86.156.77.147]) by smtp.gmail.com with ESMTPSA id p49sm11303058wrc.61.2017.11.03.03.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 03:10:59 -0700 (PDT) From: Martyn Welch X-Google-Original-From: Martyn Welch Received: from martyn by hades with local (Exim 4.84_2) (envelope-from ) id 1eAYwD-0002bT-RM; Fri, 03 Nov 2017 10:10:57 +0000 To: u-boot@lists.denx.de Date: Fri, 3 Nov 2017 10:10:51 +0000 Message-Id: <1509703855-9948-5-git-send-email-martyn.welch@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> References: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> Cc: Nandor Han Subject: [U-Boot] [PATCH v4 4/8] arm: mx5: Add more register definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add register definitions require for video configuration. Signed-off-by: Nandor Han Signed-off-by: Martyn Welch Reviewed-by: Stefano Babic Cc: Stefano Babic --- arch/arm/include/asm/arch-mx5/crm_regs.h | 9 +++++++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index b61c7b9..c0af832 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -210,6 +210,15 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET 26 +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK (0x7 << 26) +#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v) (((v) & 0x7) << 26) +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7) + +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5 + + /* Define the bits in register CSCDR2 */ #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 2b0dc1e..bc1288e 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -416,6 +416,34 @@ struct iomuxc { }; #endif + +#define IOMUXC_GPR2_BITMAP_SPWG 0 +#define IOMUXC_GPR2_BITMAP_JEIDA 1 + +#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 +#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1< X-Patchwork-Id: 833749 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="jr8CxrY+"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ySySd6sWkz9s8J for ; Fri, 3 Nov 2017 21:12:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4DC0BC21E35; Fri, 3 Nov 2017 10:12:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BA17AC21C45; Fri, 3 Nov 2017 10:11:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 63DD4C21C59; Fri, 3 Nov 2017 10:11:03 +0000 (UTC) Received: from mail-wr0-f195.google.com (mail-wr0-f195.google.com [209.85.128.195]) by lists.denx.de (Postfix) with ESMTPS id ECA3EC21C59 for ; Fri, 3 Nov 2017 10:11:00 +0000 (UTC) Received: by mail-wr0-f195.google.com with SMTP id u40so2014534wrf.10 for ; Fri, 03 Nov 2017 03:11:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=srycvGSGgVw6pz+xaYzwXIwFX0RU4jOMBfT1h2PgtL0=; b=jr8CxrY+HluG5SkBFaM9cwVnn3Jtpt0Vq3LLicwkiaXVvsaYW+WwosKIwvNpBT8mv+ JKnUfYzy6itEK+aE1PfP4l44ZwCnnZC4Ogi7HrpdqqUqJWLJkxaqUXwwNnKtzKb5qYHP ZMU0kp/ub+LiigdhUYXFxsS3/Vsh6wEm0GoOPyJoA1W3vW2r6JanDQjjdzDdCHBllorb lXU3cG6jpwngd2hyQmdnYNK3AGP46ZVfcw7AsNz03Wsi35sdsbyYBLzMRkoBzEqot7xN HGnHtXShYQ0S9GkOH6aEF7NxV5F19GsGaJtf9blc9S7bCMQ9a9SneUgRt/NoSBOcxwTU wckA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=srycvGSGgVw6pz+xaYzwXIwFX0RU4jOMBfT1h2PgtL0=; b=gUWon7baCfy9snEEUHOCbkrWuPtCFZ7vPzY7GD61H4ke9Alm4LOX/1ccOx3/RTQiJL imZqX16Y3sPQb9NgiNiQu/QSijYUSXHCZ3uULm/PAuL95KiMy5wGWDASCaOlP5A2u75z ViLRz2Ie2B27WnahG/0qJ7FEQUn/uR6ktTKy+hEuKW/1jpBQ2cxLbP98p9tFW4MRCtk3 iKzNzfuqdLTBZUKTOEYfT1c0k/m8aWQbvY8poPE3WqvbWrzzKiitgGhhOwcqn106hUzP r416sddjwp8Aw96zFEuDIY5pLgdzk3l42SASt6yiHzMjjLAe+MQVUogQgQEE0aZvBcbc KGFA== X-Gm-Message-State: AMCzsaXyXlqi+jQX0YECMRo0+wwgpy1NNbp0ABoh206V5z2Zi6g7Z1P9 caQmP9IOG8GrocDIcn+MdxBdAQ== X-Google-Smtp-Source: ABhQp+SrVPN7rRHwIWSrGzuSkJH8WZEYeWBQ3DwMYekMmdtvUGSp0+fhrF9pNeQ7myoL32g9j/DV+A== X-Received: by 10.223.193.70 with SMTP id w6mr5732266wre.158.1509703860263; Fri, 03 Nov 2017 03:11:00 -0700 (PDT) Received: from hades (host86-156-77-147.range86-156.btcentralplus.com. [86.156.77.147]) by smtp.gmail.com with ESMTPSA id u4sm3451942wre.1.2017.11.03.03.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 03:10:59 -0700 (PDT) From: Martyn Welch X-Google-Original-From: Martyn Welch Received: from martyn by hades with local (Exim 4.84_2) (envelope-from ) id 1eAYwD-0002bX-Ra; Fri, 03 Nov 2017 10:10:57 +0000 To: u-boot@lists.denx.de Date: Fri, 3 Nov 2017 10:10:52 +0000 Message-Id: <1509703855-9948-6-git-send-email-martyn.welch@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> References: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> Cc: Ian Ray Subject: [U-Boot] [PATCH v4 5/8] bootcount: add support for bootcounter on EXT filesystem X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ian Ray Add support for bootcounter on an EXT filesystem. Sync configuration whitelist. Signed-off-by: Ian Ray Signed-off-by: Martyn Welch --- Changes for v2: - Adding Kconfig for EXT bootcount. Changes for v3: - Add over-arching BOOTCOUNT Kconfig entry. README | 7 +++++ drivers/Kconfig | 2 ++ drivers/bootcount/Kconfig | 57 +++++++++++++++++++++++++++++++++++++ drivers/bootcount/Makefile | 1 + drivers/bootcount/bootcount_ext.c | 59 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 126 insertions(+) create mode 100644 drivers/bootcount/Kconfig create mode 100644 drivers/bootcount/bootcount_ext.c diff --git a/README b/README index f288176..6336c5c 100644 --- a/README +++ b/README @@ -2362,6 +2362,13 @@ The following options need to be configured: CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for the bootcounter. CONFIG_BOOTCOUNT_ALEN = address len + CONFIG_BOOTCOUNT_EXT + enable support for the bootcounter in EXT filesystem + CONFIG_SYS_BOOTCOUNT_ADDR = RAM address used for read + and write. + CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE = interface + CONFIG_SYS_BOOTCOUNT_EXT_DEVPART = device and part + CONFIG_SYS_BOOTCOUNT_EXT_NAME = filename - Show boot progress: CONFIG_SHOW_BOOT_PROGRESS diff --git a/drivers/Kconfig b/drivers/Kconfig index 613e602..c2e813f 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -10,6 +10,8 @@ source "drivers/ata/Kconfig" source "drivers/block/Kconfig" +source "drivers/bootcount/Kconfig" + source "drivers/clk/Kconfig" source "drivers/cpu/Kconfig" diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig new file mode 100644 index 0000000..acffbcf --- /dev/null +++ b/drivers/bootcount/Kconfig @@ -0,0 +1,57 @@ +# +# Boot count configuration +# + +menu "Boot count support" + +config BOOTCOUNT + bool "Enable Boot count support" + help + Enable boot count support, which provides the ability to store the + number of times the board has booted on a number of different + persistent storage mediums. + +if BOOTCOUNT + +config BOOTCOUNT_EXT + bool "Boot counter on EXT filesystem" + help + Add support for bootcounter on an EXT filesystem. + +if BOOTCOUNT_EXT + +config SYS_BOOTCOUNT_EXT_INTERFACE + string "Interface on which to find boot counter EXT filesystem" + default "mmc" + depends on BOOTCOUNT_EXT + help + Set the interface to use when locating the filesystem to use for the + boot counter. + +config SYS_BOOTCOUNT_EXT_DEVPART + string "Partition of the boot counter EXT filesystem" + default "0:1" + depends on BOOTCOUNT_EXT + help + Set the partition to use when locating the filesystem to use for the + boot counter. + +config SYS_BOOTCOUNT_EXT_NAME + string "Path and filename of the EXT filesystem based boot counter" + default "/boot/failures" + depends on BOOTCOUNT_EXT + help + Set the filename and path of the file used to store the boot counter. + +config SYS_BOOTCOUNT_ADDR + hex "RAM address used for reading and writing the boot counter" + default 0x7000A000 + depends on BOOTCOUNT_EXT + help + Set the address used for reading and writing the boot counter. + +endif + +endif + +endmenu diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index ed9659a..45445d2 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o +obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o diff --git a/drivers/bootcount/bootcount_ext.c b/drivers/bootcount/bootcount_ext.c new file mode 100644 index 0000000..d36bb0e --- /dev/null +++ b/drivers/bootcount/bootcount_ext.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2017 General Electric Company. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define BC_MAGIC 0xbc + +void bootcount_store(ulong a) +{ + uint8_t *buf; + loff_t len; + int ret; + + if (fs_set_blk_dev(CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE, CONFIG_SYS_BOOTCOUNT_EXT_DEVPART, FS_TYPE_EXT)) { + puts("Error selecting device\n"); + return; + } + + buf = map_sysmem(CONFIG_SYS_BOOTCOUNT_ADDR, 2); + buf[0] = BC_MAGIC; + buf[1] = (a & 0xff); + unmap_sysmem(buf); + + ret = fs_write(CONFIG_SYS_BOOTCOUNT_EXT_NAME, CONFIG_SYS_BOOTCOUNT_ADDR, 0, 2, &len); + if (ret != 0) { + puts("Error storing bootcount\n"); + } +} + +ulong bootcount_load(void) +{ + uint8_t *buf; + loff_t len_read; + int ret; + + if (fs_set_blk_dev(CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE, CONFIG_SYS_BOOTCOUNT_EXT_DEVPART, FS_TYPE_EXT)) { + puts("Error selecting device\n"); + return 0; + } + + ret = fs_read(CONFIG_SYS_BOOTCOUNT_EXT_NAME, CONFIG_SYS_BOOTCOUNT_ADDR, 0, 2, &len_read); + if (ret != 0 || len_read != 2) { + puts("Error loading bootcount\n"); + return 0; + } + + buf = map_sysmem(CONFIG_SYS_BOOTCOUNT_ADDR, 2); + if (buf[0] == BC_MAGIC) { + ret = buf[1]; + } + unmap_sysmem(buf); + + return ret; +} From patchwork Fri Nov 3 10:10:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 833756 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kqNz1tLV"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ySyZF72Tpz9s8J for ; Fri, 3 Nov 2017 21:17:41 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B1DAFC21E0C; Fri, 3 Nov 2017 10:15:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 975FEC21E4C; Fri, 3 Nov 2017 10:11:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F1ADEC21DA1; Fri, 3 Nov 2017 10:11:07 +0000 (UTC) Received: from mail-wr0-f195.google.com (mail-wr0-f195.google.com [209.85.128.195]) by lists.denx.de (Postfix) with ESMTPS id 0FBC0C21C45 for ; Fri, 3 Nov 2017 10:11:04 +0000 (UTC) Received: by mail-wr0-f195.google.com with SMTP id y9so2038224wrb.2 for ; Fri, 03 Nov 2017 03:11:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Noi3IFUJsM438F67dXRYNIdbLnNokUNNMUSAaqT15W8=; b=kqNz1tLVogD9ah6Cg4fq6XZaWZQpmBfivcw2yxpxX9ztWbUHWVvzAxaGkbdT6iyA2d dK1SsEcjBy2381A4H/PQIM24ZF2QIXuiZNm6G+fbROGDE+dp/bGV52A+rI70Kt5VblrT kNhqENntR4TZzuUuuqSaZjVxD6cnkQ0+QNnR2v/0O6hDJKsaetH3zpSMIzpaiDP2uCYP lgBLTihul8ye3hzwd2063LfTjU9d+nfGsKDl0hFPLd5H8xDqqNE5qVnwNXxBinumFlgF iNuZbfWA8I9LqM9jHSTak8chxr+Zix0uSdt6DuTYJ9g1cZhSqlGzBrg+lpslbEmZ4YNk 0k4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Noi3IFUJsM438F67dXRYNIdbLnNokUNNMUSAaqT15W8=; b=UxbUfIPm+beWSOz64T1WImCcwZyuGnIkh9eIvp1Hzv18g3cj95vpBuGfH/GP4GbNgD pLhwmngrbwpiU7MscJfBI7yioFLzfCVDkxlVfdWTGMc8fw/cWCYTzcwaP9QJg2ugPJgG k3nLfRdjkpyvUwAHoNo6to3TGYPyUZUgzFSmkMYGpgOrNlCCXXborPZipeMaQ6UFsbol A/duVUTzV5JGmFMpD5OsDcFkL4tvKjb2Tdi1T+z6/YMppUwSWgunwRh2c3QKSx0AdR6u XdcJfToCuNkLucU07ppE3KnEX8eVORVEL0eckZjzP0RK5AhVtvwOK4DWmDuXLOduqLrE dCwA== X-Gm-Message-State: AMCzsaWhYkvtNS4d6/oOAc5RfAoofjV2bP8/55i+LbEbjenUidRELZEi oRqFfxJvnsdUxVk8rn+nmxWzEA== X-Google-Smtp-Source: ABhQp+TMI5/OsmCHk9TrB7djNwpKmsqZOh27AARxIs2uklg7bAOEwU83VLcxC1HoyW87NOz/CpYKpA== X-Received: by 10.223.163.143 with SMTP id l15mr5259568wrb.65.1509703863184; Fri, 03 Nov 2017 03:11:03 -0700 (PDT) Received: from hades (host86-156-77-147.range86-156.btcentralplus.com. [86.156.77.147]) by smtp.gmail.com with ESMTPSA id 25sm3692805wrv.8.2017.11.03.03.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 03:10:59 -0700 (PDT) From: Martyn Welch X-Google-Original-From: Martyn Welch Received: from martyn by hades with local (Exim 4.84_2) (envelope-from ) id 1eAYwD-0002bb-Rt; Fri, 03 Nov 2017 10:10:57 +0000 To: u-boot@lists.denx.de Date: Fri, 3 Nov 2017 10:10:53 +0000 Message-Id: <1509703855-9948-7-git-send-email-martyn.welch@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> References: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> Cc: Nandor Han Subject: [U-Boot] [PATCH v4 6/8] rtc: add support for s35392a X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Nandor Han Add support for S35392A RTC. The driver supports both U-Boot driver models. Signed-off-by: Nandor Han Signed-off-by: Martyn Welch Cc: Heiko Schocher --- drivers/rtc/Kconfig | 6 + drivers/rtc/Makefile | 1 + drivers/rtc/s35392a.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/Kconfig | 3 + 4 files changed, 370 insertions(+) create mode 100644 drivers/rtc/s35392a.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index d06130c7..2964bb2 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -30,4 +30,10 @@ config RTC_DS1307 Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and compatible Real Time Clock devices. +config RTC_S35392A + bool "Enable S35392A driver" + select BITREVERSE + help + Enable s35392a driver which provides rtc get and set function. + endmenu diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 003e31a..7a8f97a 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -49,5 +49,6 @@ obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o obj-$(CONFIG_RTC_RV3029) += rv3029.o obj-$(CONFIG_RTC_RX8025) += rx8025.o obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o +obj-$(CONFIG_RTC_S35392A) += s35392a.o obj-$(CONFIG_SANDBOX) += sandbox_rtc.o obj-$(CONFIG_RTC_X1205) += x1205.o diff --git a/drivers/rtc/s35392a.c b/drivers/rtc/s35392a.c new file mode 100644 index 0000000..0aa7865 --- /dev/null +++ b/drivers/rtc/s35392a.c @@ -0,0 +1,360 @@ +/* + * SII Semiconductor Corporation S35392A RTC driver. + * + * Copyright (c) 2017, General Electric Company + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * SPDX-License-Identifier: GPL-2.0 + */ + + +#include +#include +#include +#include +#include +#include + +#define S35390A_CMD_STATUS1 0x30 +#define S35390A_CMD_STATUS2 0x31 +#define S35390A_CMD_TIME1 0x32 +#define S35390A_CMD_TIME2 0x33 +#define S35390A_CMD_INT2_REG1 0x35 + +#define S35390A_BYTE_YEAR 0 +#define S35390A_BYTE_MONTH 1 +#define S35390A_BYTE_DAY 2 +#define S35390A_BYTE_WDAY 3 +#define S35390A_BYTE_HOURS 4 +#define S35390A_BYTE_MINS 5 +#define S35390A_BYTE_SECS 6 + +/* flags for STATUS1 */ +#define S35390A_FLAG_POC 0x01 +#define S35390A_FLAG_BLD 0x02 +#define S35390A_FLAG_INT2 0x04 +#define S35390A_FLAG_24H 0x40 +#define S35390A_FLAG_RESET 0x80 + +/* If either BLD or POC is set, then the chip has lost power long enough for + * the time value to become invalid. */ +#define S35390A_LOW_VOLTAGE (S35390A_FLAG_POC | S35390A_FLAG_BLD) + +/*---------------------------------------------------------------------*/ +#undef DEBUG_RTC + +#ifdef DEBUG_RTC +#define DEBUGR(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGR(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +#ifdef CONFIG_DM_RTC +#define DEV_TYPE struct udevice + +#else +/* Local udevice */ +struct ludevice { + u8 chip; +}; +#define DEV_TYPE struct ludevice +struct ludevice dev; + +#endif + +#define msleep(a) udelay(a * 1000) + +int lowvoltage = 0; + +static int s35392a_rtc_reset(DEV_TYPE *dev); + +static int s35392a_rtc_read(DEV_TYPE *dev, u8 reg, u8* buf, int len) +{ + int ret; + +#ifdef CONFIG_DM_RTC + /* TODO: we need to tweak the chip address to reg */ + ret = dm_i2c_read(dev, 0, buf, len); +#else + (void)dev; + ret = i2c_read(reg, 0, -1, buf, len); +#endif + + return ret; +} + +static int s35392a_rtc_write(DEV_TYPE *dev, u8 reg, u8* buf, int len) +{ + int ret; + +#ifdef CONFIG_DM_RTC + /* TODO: we need to tweak the chip address to reg */ + ret = dm_i2c_write(dev, 0, buf, 1); +#else + (void)dev; + ret = i2c_write(reg, 0, 0, buf, len); +#endif + + return ret; +} + +static int s35392a_rtc_read8(DEV_TYPE *dev, unsigned int reg) +{ + u8 val; + int ret; + + ret = s35392a_rtc_read(dev, reg, &val, sizeof(val)); + return ret < 0 ? ret : val; +} + +static int s35392a_rtc_write8(DEV_TYPE *dev, unsigned int reg, int val) +{ + int ret; + u8 lval = val; + + ret = s35392a_rtc_write(dev, reg, &lval, sizeof(lval)); + return ret < 0 ? ret : 0; +} + +static int validate_time(const struct rtc_time *tm) +{ + if ((tm->tm_year < 2000) || (tm->tm_year > 2099)) + return -EINVAL; + + if ((tm->tm_mon < 1) || (tm->tm_mon > 12)) + return -EINVAL; + + if ((tm->tm_mday < 1) || (tm->tm_mday > 31)) + return -EINVAL; + + if ((tm->tm_wday < 0) || (tm->tm_wday > 6)) + return -EINVAL; + + if ((tm->tm_hour < 0) || (tm->tm_hour > 23)) + return -EINVAL; + + if ((tm->tm_min < 0) || (tm->tm_min > 59)) + return -EINVAL; + + if ((tm->tm_sec < 0) || (tm->tm_sec > 59)) + return -EINVAL; + + return 0; +} + +void s35392a_rtc_init(DEV_TYPE *dev) +{ + int status = s35392a_rtc_read8(dev, S35390A_CMD_STATUS1); + if (status < 0) + goto error; + + DEBUGR("init: S35390A_CMD_STATUS1: 0x%x\n", status); + + lowvoltage = status & S35390A_LOW_VOLTAGE ? 1 : 0; + + if (status & S35390A_FLAG_POC) + /* + * Do not communicate for 0.5 seconds since the power-on + * detection circuit is in operation. + */ + msleep(500); + + else if (!lowvoltage) + /* + * If both POC and BLD are unset everything is fine. + */ + return; + + if(lowvoltage) + printf("RTC low voltage detected\n"); + + if (!s35392a_rtc_reset(dev)) + return; + +error: + printf("Error RTC init. \n"); +} + +/* Get the current time from the RTC */ +static int s35392a_rtc_get(DEV_TYPE *dev, struct rtc_time *tm) +{ + u8 date[7]; + int ret, i; + + if (lowvoltage) { + DEBUGR("RTC low voltage detected\n"); + return -EINVAL; + } + + ret = s35392a_rtc_read(dev, S35390A_CMD_TIME1, date, sizeof(date)); + if (ret < 0) { + DEBUGR("Error reading date from RTC\n"); + return -EIO; + } + + /* This chip returns the bits of each byte in reverse order */ + for (i = 0; i < 7; ++i) + date[i] = bitrev8(date[i]); + + tm->tm_sec = bcd2bin(date[S35390A_BYTE_SECS]); + tm->tm_min = bcd2bin(date[S35390A_BYTE_MINS]); + tm->tm_hour = bcd2bin(date[S35390A_BYTE_HOURS] & ~S35390A_FLAG_24H); + tm->tm_wday = bcd2bin(date[S35390A_BYTE_WDAY]); + tm->tm_mday = bcd2bin(date[S35390A_BYTE_DAY]); + tm->tm_mon = bcd2bin(date[S35390A_BYTE_MONTH]); + tm->tm_year = bcd2bin(date[S35390A_BYTE_YEAR]) + 2000; + + DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + return 0; +} + +/* Set the RTC */ +static int s35392a_rtc_set(DEV_TYPE *dev, const struct rtc_time *tm) +{ + int i, ret; + int status; + u8 date[7]; + + DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + ret = validate_time(tm); + if (ret < 0) + return -EINVAL; + + /* We support only 24h mode */ + ret = s35392a_rtc_read8(dev, S35390A_CMD_STATUS1); + if (ret < 0) + return -EIO; + status = ret; + + ret = s35392a_rtc_write8(dev, S35390A_CMD_STATUS1, status | S35390A_FLAG_24H); + if (ret < 0) + return -EIO; + + date[S35390A_BYTE_YEAR] = bin2bcd(tm->tm_year - 2000); + date[S35390A_BYTE_MONTH] = bin2bcd(tm->tm_mon ); + date[S35390A_BYTE_DAY] = bin2bcd(tm->tm_mday); + date[S35390A_BYTE_WDAY] = bin2bcd(tm->tm_wday); + date[S35390A_BYTE_HOURS] = bin2bcd(tm->tm_hour); + date[S35390A_BYTE_MINS] = bin2bcd(tm->tm_min); + date[S35390A_BYTE_SECS] = bin2bcd(tm->tm_sec); + + /* This chip expects the bits of each byte to be in reverse order */ + for (i = 0; i < 7; ++i) + date[i] = bitrev8(date[i]); + + ret = s35392a_rtc_write(dev, S35390A_CMD_TIME1, date, sizeof(date)); + if (ret < 0) { + DEBUGR("Error writing date to RTC\n"); + return -EIO; + } + + /* Now we have time. Reset the low voltage status */ + lowvoltage = 0; + + return 0; +} + +/* Reset the RTC. */ +static int s35392a_rtc_reset(DEV_TYPE *dev) +{ + int buf; + int ret; + unsigned initcount = 0; + + buf = S35390A_FLAG_RESET; + +initialize: + ret = s35392a_rtc_write8(dev, S35390A_CMD_STATUS1, buf); + if (ret < 0) + return -EIO; + + ret = s35392a_rtc_read8(dev, S35390A_CMD_STATUS1); + if (ret < 0) + return -EIO; + buf = ret; + + if (!lowvoltage) + lowvoltage = buf & S35390A_LOW_VOLTAGE ? 1 : 0; + + if (buf & S35390A_LOW_VOLTAGE) { + /* Try up to five times to reset the chip */ + if (initcount < 5) { + ++initcount; + goto initialize; + } else + return -EIO; + } + + return 0; +} + +#ifndef CONFIG_DM_RTC + +int rtc_get(struct rtc_time * tm) +{ + return s35392a_rtc_get(&dev, tm); +} + +int rtc_set(struct rtc_time * tm) +{ + return s35392a_rtc_set(&dev, tm); +} + +void rtc_reset(void) +{ + s35392a_rtc_reset(&dev); +} + +void rtc_init(void) +{ + s35392a_rtc_init(&dev); +} + +#else + +static int s35392a_probe(struct udevice *dev) +{ + s35392a_rtc_init(dev); + return 0; +} + +static const struct rtc_ops s35392a_rtc_ops = { + .get = s35392a_rtc_get, + .set = s35392a_rtc_set, + .read8 = s35392a_rtc_read8, + .write8 = s35392a_rtc_write8, + .reset = s35392a_rtc_reset, +}; + +static const struct udevice_id s35392a_rtc_ids[] = { + { .compatible = "sii,s35392a-rtc" }, + { } +}; + +U_BOOT_DRIVER(s35392a_rtc) = { + .name = "s35392a_rtc", + .id = UCLASS_RTC, + .probe = s35392a_probe, + .of_match = s35392a_rtc_ids, + .ops = &s35392a_rtc_ops, +}; + +#endif diff --git a/lib/Kconfig b/lib/Kconfig index 18663ba..f447c53 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -80,6 +80,9 @@ config TPL_TINY_MEMSET config RBTREE bool +config BITREVERSE + bool "Bit reverse library from Linux" + source lib/dhry/Kconfig menu "Security support" From patchwork Fri Nov 3 10:10:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 833748 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[86.156.77.147]) by smtp.gmail.com with ESMTPSA id r44sm7159343wrb.37.2017.11.03.03.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 03:10:59 -0700 (PDT) From: Martyn Welch X-Google-Original-From: Martyn Welch Received: from martyn by hades with local (Exim 4.84_2) (envelope-from ) id 1eAYwD-0002bf-SA; Fri, 03 Nov 2017 10:10:57 +0000 To: u-boot@lists.denx.de Date: Fri, 3 Nov 2017 10:10:54 +0000 Message-Id: <1509703855-9948-8-git-send-email-martyn.welch@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> References: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> Subject: [U-Boot] [PATCH v4 7/8] board: ge: make VPD code common X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The VPD data is used on a number of GE products. Move the parsing code to a common location so that we can share this code. Signed-off-by: Martyn Welch --- Changes in v4: - New patch. board/ge/bx50v3/Makefile | 2 +- board/ge/bx50v3/bx50v3.c | 2 +- board/ge/common/Makefile | 7 +++++++ board/ge/{bx50v3 => common}/vpd_reader.c | 0 board/ge/{bx50v3 => common}/vpd_reader.h | 0 5 files changed, 9 insertions(+), 2 deletions(-) create mode 100644 board/ge/common/Makefile rename board/ge/{bx50v3 => common}/vpd_reader.c (100%) rename board/ge/{bx50v3 => common}/vpd_reader.h (100%) diff --git a/board/ge/bx50v3/Makefile b/board/ge/bx50v3/Makefile index 2fff27b..bcd149f 100644 --- a/board/ge/bx50v3/Makefile +++ b/board/ge/bx50v3/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := bx50v3.o vpd_reader.o +obj-y := bx50v3.o diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 2e8f394..37de990 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -28,7 +28,7 @@ #include #include #include -#include "vpd_reader.h" +#include "../common/vpd_reader.h" DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_I2C_EEPROM_ADDR diff --git a/board/ge/common/Makefile b/board/ge/common/Makefile new file mode 100644 index 0000000..93e6c01 --- /dev/null +++ b/board/ge/common/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2017 General Electric Company +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := vpd_reader.o diff --git a/board/ge/bx50v3/vpd_reader.c b/board/ge/common/vpd_reader.c similarity index 100% rename from board/ge/bx50v3/vpd_reader.c rename to board/ge/common/vpd_reader.c diff --git a/board/ge/bx50v3/vpd_reader.h b/board/ge/common/vpd_reader.h similarity index 100% rename from board/ge/bx50v3/vpd_reader.h rename to board/ge/common/vpd_reader.h From patchwork Fri Nov 3 10:10:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 833755 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[86.156.77.147]) by smtp.gmail.com with ESMTPSA id c17sm7153438wrg.26.2017.11.03.03.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 03:10:59 -0700 (PDT) From: Martyn Welch X-Google-Original-From: Martyn Welch Received: from martyn by hades with local (Exim 4.84_2) (envelope-from ) id 1eAYwD-0002bk-ST; Fri, 03 Nov 2017 10:10:57 +0000 To: u-boot@lists.denx.de Date: Fri, 3 Nov 2017 10:10:55 +0000 Message-Id: <1509703855-9948-9-git-send-email-martyn.welch@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> References: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> MIME-Version: 1.0 Cc: Ian Ray , Peter Senna Tschudin , Nandor Han Subject: [U-Boot] [PATCH v4 8/8] mx53: Add Board support for GE PPD X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Peter Senna Tschudin Create board support for GE PPD, based on mx53loco. Use mx53ppd_defconfig make target to configure for this board. Signed-off-by: Peter Senna Tschudin Signed-off-by: Ian Ray Signed-off-by: Nandor Han Signed-off-by: Martyn Welch Cc: Stefano Babic --- Changes in v4: - Remove mach-type.h entry. - Move to ge board directory (to be able to use ge common code). - Remove now common VPD code. - Move do_lcd_enable() to mx53ppd_video.c. arch/arm/mach-imx/mx5/Kconfig | 5 + board/ge/mx53ppd/Kconfig | 17 ++ board/ge/mx53ppd/MAINTAINERS | 7 + board/ge/mx53ppd/Makefile | 12 + board/ge/mx53ppd/imximage.cfg | 87 +++++++ board/ge/mx53ppd/mx53ppd.c | 474 +++++++++++++++++++++++++++++++++++++++ board/ge/mx53ppd/mx53ppd_video.c | 135 +++++++++++ board/ge/mx53ppd/ppd_gpio.h | 96 ++++++++ configs/mx53ppd_defconfig | 39 ++++ include/configs/mx53ppd.h | 244 ++++++++++++++++++++ 10 files changed, 1116 insertions(+) create mode 100644 board/ge/mx53ppd/Kconfig create mode 100644 board/ge/mx53ppd/MAINTAINERS create mode 100644 board/ge/mx53ppd/Makefile create mode 100644 board/ge/mx53ppd/imximage.cfg create mode 100644 board/ge/mx53ppd/mx53ppd.c create mode 100644 board/ge/mx53ppd/mx53ppd_video.c create mode 100644 board/ge/mx53ppd/ppd_gpio.h create mode 100644 configs/mx53ppd_defconfig create mode 100644 include/configs/mx53ppd.h diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig index ef37c35..21f825d 100644 --- a/arch/arm/mach-imx/mx5/Kconfig +++ b/arch/arm/mach-imx/mx5/Kconfig @@ -45,6 +45,10 @@ config TARGET_MX53LOCO select BOARD_LATE_INIT select MX53 +config TARGET_MX53PPD + bool "Support mx53ppd" + select MX53 + config TARGET_MX53SMD bool "Support mx53smd" select MX53 @@ -70,6 +74,7 @@ source "board/freescale/mx53ard/Kconfig" source "board/freescale/mx53evk/Kconfig" source "board/freescale/mx53loco/Kconfig" source "board/freescale/mx53smd/Kconfig" +source "board/ge/mx53ppd/Kconfig" source "board/inversepath/usbarmory/Kconfig" source "board/technologic/ts4800/Kconfig" diff --git a/board/ge/mx53ppd/Kconfig b/board/ge/mx53ppd/Kconfig new file mode 100644 index 0000000..781c1cf --- /dev/null +++ b/board/ge/mx53ppd/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ + +if TARGET_MX53PPD + +config SYS_BOARD + default "mx53ppd" + +config SYS_VENDOR + default "ge" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "mx53ppd" + +endif diff --git a/board/ge/mx53ppd/MAINTAINERS b/board/ge/mx53ppd/MAINTAINERS new file mode 100644 index 0000000..9b64b5d --- /dev/null +++ b/board/ge/mx53ppd/MAINTAINERS @@ -0,0 +1,7 @@ +MX53PPD BOARD +M: Antti Mäentausta +M: Martyn Welch +S: Maintained +F: board/freescale/mx53ppd/ +F: include/configs/mx53ppd.h +F: configs/mx53ppd_defconfig diff --git a/board/ge/mx53ppd/Makefile b/board/ge/mx53ppd/Makefile new file mode 100644 index 0000000..928edfb --- /dev/null +++ b/board/ge/mx53ppd/Makefile @@ -0,0 +1,12 @@ +# Copyright 2017 General Electric Company +# +# Based on board/freescale/mx53loco/Makefile: +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# Jason Liu +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += mx53ppd.o +obj-$(CONFIG_VIDEO) += mx53ppd_video.o diff --git a/board/ge/mx53ppd/imximage.cfg b/board/ge/mx53ppd/imximage.cfg new file mode 100644 index 0000000..83ff4b8 --- /dev/null +++ b/board/ge/mx53ppd/imximage.cfg @@ -0,0 +1,87 @@ +/* + * Copyright 2017 General Electric Company + * + * Based on board/freescale/mx53loco/imximage.cfg: + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x53fa8004 0x00194005 +DATA 4 0x53fa8554 0x00300000 +DATA 4 0x53fa8558 0x00300040 +DATA 4 0x53fa8560 0x00300000 +DATA 4 0x53fa8564 0x00300040 +DATA 4 0x53fa8568 0x00300040 +DATA 4 0x53fa8570 0x00300000 +DATA 4 0x53fa8574 0x00300000 +DATA 4 0x53fa8578 0x00300000 +DATA 4 0x53fa857c 0x00300040 +DATA 4 0x53fa8580 0x00300040 +DATA 4 0x53fa8584 0x00300000 +DATA 4 0x53fa8588 0x00300000 +DATA 4 0x53fa8590 0x00300040 +DATA 4 0x53fa8594 0x00300000 +DATA 4 0x53fa86f0 0x00300000 +DATA 4 0x53fa86f4 0x00000000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8718 0x00300000 +DATA 4 0x53fa871c 0x00300000 +DATA 4 0x53fa8720 0x00300000 +DATA 4 0x53fa8728 0x00300000 +DATA 4 0x53fa872c 0x00300000 +DATA 4 0x63fd9088 0x35343535 +DATA 4 0x63fd9090 0x4d444c44 +DATA 4 0x63fd907c 0x01370138 +DATA 4 0x63fd9080 0x013b013c +DATA 4 0x63fd9018 0x00111740 +DATA 4 0x63fd9000 0x85190000 +DATA 4 0x63fd900c 0x8b8f52e3 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x008f0e21 +DATA 4 0x63fd9008 0x09333030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00468031 +DATA 4 0x63fd901c 0x052080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x05208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00005800 +DATA 4 0x63fd9040 0x05380003 +DATA 4 0x63fd9058 0x00011110 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c new file mode 100644 index 0000000..7b8756b --- /dev/null +++ b/board/ge/mx53ppd/mx53ppd.c @@ -0,0 +1,474 @@ +/* + * Copyright 2017 General Electric Company + * + * Based on board/freescale/mx53loco/mx53loco.c: + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ppd_gpio.h" +#include +#include "../../ge/common/vpd_reader.h" +#include + +#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24) + +DECLARE_GLOBAL_DATA_PTR; + +/* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */ +#define VPD_EEPROM_BUS 2 + +/* Address of 24C08 EEPROM. */ +#define VPD_EEPROM_ADDR 0x50 +#define VPD_EEPROM_ADDR_LEN 1 + +static uint32_t mx53_dram_size[2]; + +phys_size_t get_effective_memsize(void) +{ + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return mx53_dram_size[0]; +} + +int dram_init(void) +{ + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); + + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; + + return 0; +} + +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + int rev = readl(&fuse->gp[6]); + + rev = 0; + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + +#ifdef CONFIG_USB_EHCI_MX5 +int board_ehci_hcd_init(int port) +{ + /* request VBUS power enable pin, GPIO7_8 */ + imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8); + gpio_direction_output(IMX_GPIO_NR(7, 8), 1); + return 0; +} +#endif + +static void setup_iomux_fec(void) +{ + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), + NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, + PAD_CTL_HYS | PAD_CTL_PKE), + NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + PAD_CTL_HYS | PAD_CTL_PKE), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC3_BASE_ADDR}, + {MMC_SDHC1_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_DSE_HIGH) + +int board_mmc_init(bd_t *bis) +{ + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, + SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), + MX53_PAD_EIM_DA11__GPIO3_11, + }; + + static const iomux_v3_cfg_t sd2_pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), + MX53_PAD_EIM_DA13__GPIO3_13, + }; + + u32 index; + int ret; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads(sd1_pads, + ARRAY_SIZE(sd1_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(sd2_pads, + ARRAY_SIZE(sd2_pads)); + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return -EINVAL; + } + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; +} +#endif + +#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + +static void setup_iomux_i2c(void) +{ + static const iomux_v3_cfg_t i2c1_pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); +} + +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD, + .gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD, + .gp = IMX_GPIO_NR(3, 28) + }, + .sda = { + .i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD, + .gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD, + .gp = IMX_GPIO_NR(3, 21) + } +}; + +static void clock_1GHz(void) +{ + int ret; + u32 ref_clk = MXC_HCLK; + /* + * After increasing voltage to 1.25V, we can switch + * CPU clock to 1GHz and DDR to 400MHz safely + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to 400MHz failed\n"); +} + +void ppd_gpio_init(void) +{ + int i; + imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads)); + for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i) { + gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value); + } +} + +int board_early_init_f(void) +{ + setup_iomux_fec(); + setup_iomux_lcd(); + ppd_gpio_init(); + + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#define VPD_TYPE_INVALID 0x00 +#define VPD_BLOCK_NETWORK 0x20 +#define VPD_BLOCK_HWID 0x44 +#define VPD_PRODUCT_PPD 4 +#define VPD_HAS_MAC1 0x1 +#define VPD_MAC_ADDRESS_LENGTH 6 + +struct vpd_cache { + uint8_t product_id; + uint8_t has; + unsigned char mac1[VPD_MAC_ADDRESS_LENGTH]; +}; + +/* + * Extracts MAC and product information from the VPD. + */ +static int vpd_callback( + void *userdata, + uint8_t id, + uint8_t version, + uint8_t type, + size_t size, + uint8_t const *data) +{ + struct vpd_cache *vpd = (struct vpd_cache *)userdata; + + if ( id == VPD_BLOCK_HWID + && version == 1 + && type != VPD_TYPE_INVALID + && size >= 1) { + vpd->product_id = data[0]; + + } else if ( id == VPD_BLOCK_NETWORK + && version == 1 + && type != VPD_TYPE_INVALID) { + if (size >= 6) { + vpd->has |= VPD_HAS_MAC1; + memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH); + } + } + + return 0; +} + +static void process_vpd(struct vpd_cache *vpd) +{ + int fec_index = -1; + + switch (vpd->product_id) + { + case VPD_PRODUCT_PPD: + fec_index = 0; + break; + } + + if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1)) { + eth_env_set_enetaddr("ethaddr", vpd->mac1); + } +} + +static int read_vpd(uint eeprom_bus) +{ + struct vpd_cache vpd; + int res; + int size = 1024; + uint8_t *data; + unsigned int current_i2c_bus = i2c_get_bus_num(); + + res = i2c_set_bus_num(eeprom_bus); + if (res < 0) + return res; + + data = (uint8_t *)malloc(size); + if (!data) + return -ENOMEM; + + res = i2c_read(VPD_EEPROM_ADDR, 0, + VPD_EEPROM_ADDR_LEN, data, size); + + if (res == 0) { + memset(&vpd, 0, sizeof(vpd)); + vpd_reader(size, data, &vpd, vpd_callback); + process_vpd(&vpd); + } + + free(data); + + i2c_set_bus_num(current_i2c_bus); + return res; +} + +void check_time(void) +{ + int ret, i; + struct rtc_time tm; + u8 retry = 3; + + unsigned int current_i2c_bus = i2c_get_bus_num(); + + ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM); + if (ret < 0) + return; + + rtc_init(); + + for (i = 0; i < retry; i++) { + ret = rtc_get(&tm); + if(!ret || ret == -EINVAL) { + break; + } + } + + if (ret < 0) { + env_set("rtc_status", "RTC_ERROR"); + } + + if (tm.tm_year > 2037) { + tm.tm_sec = 0; + tm.tm_min = 0; + tm.tm_hour = 0; + tm.tm_mday = 1; + tm.tm_wday = 2; + tm.tm_mon = 1; + tm.tm_year = 2036; + + for (i = 0; i < retry; i++) { + ret = rtc_set(&tm); + if(!ret) { + break; + } + } + + if (ret < 0) + env_set("rtc_status", "RTC_ERROR"); + } + + i2c_set_bus_num(current_i2c_bus); +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + mxc_set_sata_internal_clock(); + setup_iomux_i2c(); + + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + return 0; +} + +int misc_init_r(void) +{ + const char *cause; + + /* We care about WDOG only, treating everything else as + * a power-on-reset. + */ + if (get_imx_reset_cause() & 0x0010) { + cause = "WDOG"; + } else { + cause = "POR"; + } + + env_set("bootcause", cause); + + return 0; +} + +int board_late_init(void) +{ + read_vpd(VPD_EEPROM_BUS); + + clock_1GHz(); + print_cpuinfo(); + hw_watchdog_init(); + + check_time(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: GE PPD\n"); + + return 0; +} diff --git a/board/ge/mx53ppd/mx53ppd_video.c b/board/ge/mx53ppd/mx53ppd_video.c new file mode 100644 index 0000000..08daa1c --- /dev/null +++ b/board/ge/mx53ppd/mx53ppd_video.c @@ -0,0 +1,135 @@ +/* + * Copyright 2017 General Electric Company + * + * Based on board/freescale/mx53loco/mx53loco_video.c: + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Fabio Estevam + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ppd_gpio.h" + +#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24) + +static struct fb_videomode const nv_spwg = { + .name = "NV-SPWGRGB888", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 15384, + .left_margin = 16, + .right_margin = 210, + .upper_margin = 10, + .lower_margin = 22, + .hsync_len = 30, + .vsync_len = 13, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +}; + + +void setup_iomux_lcd(void) +{ + static const iomux_v3_cfg_t lcd_pads[] = { + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, + }; + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); +} + +void lcd_enable(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* Set LDB_DI0 as clock source for IPU_DI0 */ + clrsetbits_le32(&mxc_ccm->cscmr2, + MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK, + MXC_CCM_CSCMR2_DI0_CLK_SEL(MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK)); + + /* Turn on IPU LDB DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3)); + + /* Turn on IPU DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3)); + + /* Configure LDB */ + writel(IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + /* Enable backlights */ + pwm_init(1, 0, 0); + + /* duty cycle 5000000ns, period: 5000000ns */ + pwm_config(1, 5000000, 5000000); + + /* Backlight Power */ + gpio_direction_output(BACKLIGHT_ENABLE, 1); + + pwm_enable(1); +} + +static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + lcd_enable(); + return 0; +} + +U_BOOT_CMD( + ppd_lcd_enable, 1, 1, do_lcd_enable, + "enable PPD LCD", + "no parameters" +); + +int board_video_skip(void) +{ + int ret; + + ret = ipuv3_fb_init(&nv_spwg, 0, IPU_PIX_FMT_RGB24); + if (ret) + printf("Display cannot be configured: %d\n", ret); + + return ret; +} diff --git a/board/ge/mx53ppd/ppd_gpio.h b/board/ge/mx53ppd/ppd_gpio.h new file mode 100644 index 0000000..a722435 --- /dev/null +++ b/board/ge/mx53ppd/ppd_gpio.h @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2015 General Electric Company + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PPD_GPIO_H_ +#define __PPD_GPIO_H_ + +#include +#include + +#define PPD_UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) + +static const iomux_v3_cfg_t ppd_pads[] = { + /* FEC */ + MX53_PAD_EIM_A22__GPIO2_16, + /* UART */ + NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, PPD_UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, PPD_UART_PAD_CTRL), + /* Video */ + MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */ + MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */ + MX53_PAD_CSI0_DAT10__GPIO5_28, /* DATA_WIDTH_CTRL */ + MX53_PAD_CSI0_PIXCLK__GPIO5_18, /* HOST_CONTROLLED_RESET_TO_LCD_N */ + MX53_PAD_EIM_DA2__GPIO3_2, /* LVDS1_MUX_CTRL */ + MX53_PAD_EIM_DA3__GPIO3_3, /* LVDS0_MUX_CTRL */ + MX53_PAD_EIM_A21__GPIO2_17, /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ + MX53_PAD_CSI0_DAT11__GPIO5_29, /* BACKLIGHT_ENABLE */ + MX53_PAD_DISP0_DAT9__PWM2_PWMO, /* IMX535_PWM2_TO_LCD_CONNECTOR */ + /* I2C */ + MX53_PAD_EIM_A20__GPIO2_18, /* RESET_I2C1_BUS_SEGMENT_MUX_N */ + + /* SPI */ + MX53_PAD_DISP0_DAT23__GPIO5_17, + MX53_PAD_KEY_COL2__GPIO4_10, + MX53_PAD_KEY_ROW2__GPIO4_11, + MX53_PAD_KEY_COL3__GPIO4_12, +}; + +struct gpio_cfg { + unsigned gpio; + int value; +}; + +#define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16) +#define UD_SCAN_CTRL IMX_GPIO_NR(5, 21) +#define LR_SCAN_CTRL IMX_GPIO_NR(5, 20) +#define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3) +#define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2) +#define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18) +#define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28) +#define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28) +#define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29) +#define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22) +#define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27) +#define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17) +#define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29) +#define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18) +#define ECSPI1_CS0 IMX_GPIO_NR(5, 17) +#define ECSPI1_CS1 IMX_GPIO_NR(4, 10) +#define ECSPI1_CS2 IMX_GPIO_NR(4, 11) +#define ECSPI1_CS3 IMX_GPIO_NR(4, 12) + +static const struct gpio_cfg ppd_gpios[] = { + /* FEC */ + /* Drive Low as GPIO output for 25ms per Eth Phy IX spec */ + /* Then Drive High as GPIO output to bring Eth Phy IC out of reset */ + { RESET_IMX535_ETHERNET_PHY_N, 0 }, + { RESET_IMX535_ETHERNET_PHY_N, 1 }, + /* Video */ + { UD_SCAN_CTRL, 0 }, + { LR_SCAN_CTRL, 1 }, +#ifdef PROPRIETARY_CHANGES + { LVDS0_MUX_CTRL, 1 }, +#else + { LVDS0_MUX_CTRL, 0 }, +#endif + { LVDS1_MUX_CTRL, 1 }, + { HOST_CONTROLLED_RESET_TO_LCD_N, 1 }, + { DATA_WIDTH_CTRL, 0 }, + { RESET_DP0_TRANSMITTER_N, 1 }, + { RESET_DP1_TRANSMITTER_N, 1 }, + { POWER_DOWN_LVDS0_DESERIALIZER_N, 1 }, + { POWER_DOWN_LVDS1_DESERIALIZER_N, 1 }, + { ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 }, + { BACKLIGHT_ENABLE, 0 }, + { RESET_I2C1_BUS_SEGMENT_MUX_N, 1 }, + { ECSPI1_CS0, 1 }, + { ECSPI1_CS1, 1 }, + { ECSPI1_CS2, 1 }, + { ECSPI1_CS3, 1 }, +}; + +#endif /* __PPD_GPIO_H_ */ diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig new file mode 100644 index 0000000..0ab19e9 --- /dev/null +++ b/configs/mx53ppd_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX5=y +CONFIG_TARGET_MX53PPD=y +CONFIG_FIT=y +CONFIG_BOOTCOUNT=y +CONFIG_BOOTCOUNT_EXT=y +CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE="mmc" +CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5" +CONFIG_SYS_BOOTCOUNT_EXT_NAME="/boot/failures" +CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000 +CONFIG_NETDEVICES=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg" +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_I2C=y +CONFIG_RTC_S35392A=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +# CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_OF_LIBFDT=y + +CONFIG_MMC=y diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h new file mode 100644 index 0000000..7cc4689 --- /dev/null +++ b/include/configs/mx53ppd.h @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * Configuration settings for Freescale MX53 low cost board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONSOLE_DEV "ttymxc0" + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_FSL_CLK + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000 + +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO +#define CONFIG_REVISION_TAG + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_SUPPORT_RAW_INITRD /* bootz raw initrd support */ + +/* Eth Configs */ +#define CONFIG_MII + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +/* USB Configs */ +#define CONFIG_USB_EHCI_MX5 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +#define CONFIG_SYS_RTC_BUS_NUM 2 +#define CONFIG_SYS_I2C_RTC_ADDR 0x30 + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* PMIC Controller */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_DIALOG_POWER +#define CONFIG_POWER_FSL +#define CONFIG_POWER_FSL_MC13892 +#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#define CONFIG_SUPPORT_RAW_INITRD + + +#define CONFIG_ETHPRIME "FEC0" + +#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ +#define CONFIG_SYS_TEXT_BASE 0x77800000 + +#define PPD_CONFIG_NFS \ + "nfsserver=192.168.252.95\0" \ + "gatewayip=192.168.252.95\0" \ + "netmask=255.255.255.0\0" \ + "ipaddr=192.168.252.99\0" \ + "kernsize=0x2000\0" \ + "use_dhcp=0\0" \ + "nfsroot=/opt/springdale/rd\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs ${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \ + "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; set getcmd dhcp; else set kern_ipconf ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; set getcmd tftp; fi\0" \ + "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} ${nfsserver}:${image}; bootm ${loadaddr}\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + PPD_CONFIG_NFS \ + "bootlimit=10\0" \ + "image=/boot/fitImage\0" \ + "fdt_high=0xffffffff\0" \ + "dev=mmc\0" \ + "devnum=0\0" \ + "rootdev=mmcblk0p\0" \ + "quiet=quiet loglevel=0\0" \ + "console=" CONSOLE_DEV "\0" \ + "lvds=ldb\0" \ + "setargs=setenv bootargs ${lvds} jtag=on mem=2G vt.global_cursor_default=0 " \ + "bootcause=${bootcause} " \ + "${quiet} console=${console} ${rtc_status}" \ + "\0" \ + "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} " \ + "ro rootwait ${bootargs}\0" \ + "doquiet=" \ + "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; then setenv quiet; fi\0" \ + "hasfirstboot=" \ + "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 /boot/bootcause/firstboot\0" \ + "swappartitions=" \ + "setexpr partnum 3 - ${partnum}\0" \ + "failbootcmd=" \ + "ppd_lcd_enable; " \ + "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ + "echo $msg; " \ + "setenv stdout vga; " \ + "echo \"\n\n\n\n \" $msg; " \ + "setenv stdout serial; " \ + "mw.b 0x7000A000 0xbc; " \ + "mw.b 0x7000A001 0x00; " \ + "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ + "altbootcmd=" \ + "run doquiet; " \ + "setenv partnum 1; run hasfirstboot || setenv partnum 2; run hasfirstboot || setenv partnum 0; " \ + "if test ${partnum} != 0; then " \ + "setenv bootcause REVERT; " \ + "run swappartitions loadimage doboot; " \ + "fi; " \ + "run failbootcmd\0" \ + "loadimage=" \ + "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ + "doboot=" \ + "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ + "run setargs; " \ + "run bootargs_emmc; " \ + "bootm ${loadaddr}\0" \ + "tryboot=" \ + "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ + "run loadimage || run swappartitions && run loadimage || setenv partnum 0 && echo MISSING IMAGE;" \ + "run doboot; " \ + "run failbootcmd\0" \ + "video-mode=" \ + "lcd:800x480-24@60,monitor=lcd\0" \ + + +#define CONFIG_MMCBOOTCOMMAND \ + "if mmc dev ${devnum}; then " \ + "run doquiet; " \ + "run tryboot; " \ + "fi; " \ + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_MAXARGS 48 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_CMD_FUSE +#define CONFIG_FSL_IIM + +#define CONFIG_SYS_I2C_SPEED 100000 + +/* I2C1 */ +#define CONFIG_SYS_NUM_I2C_BUSES 9 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ + } + +#define CONFIG_BCH + +#define CONFIG_BOOTCOUNT_LIMIT + +/* Backlight Control */ +#define CONFIG_PWM_IMX +#define CONFIG_IMX6_PWM_PER_CLK 66666000 + +/* Framebuffer and LCD */ +#ifdef CONFIG_VIDEO + #define CONFIG_VIDEO_IPUV3 +#endif + +#endif /* __CONFIG_H */