From patchwork Fri Jun 28 02:12:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123819 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ETTtTjjf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgL81kFdz9s9G for ; Fri, 28 Jun 2019 12:13:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726716AbfF1CNl (ORCPT ); Thu, 27 Jun 2019 22:13:41 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19612 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726694AbfF1CNk (ORCPT ); Thu, 27 Jun 2019 22:13:40 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:31 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:33 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:33 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:33 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:33 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:33 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 01/18] irqchip: tegra: Do not disable COP IRQ during suspend Date: Thu, 27 Jun 2019 19:12:35 -0700 Message-ID: <1561687972-19319-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688011; bh=s1XnuLcDk97/CuRHD9/IW+GAX3pxhADV42EQBIG7j4Y=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ETTtTjjfEu+L/wxeVVmd8cYksQbkCX1BAC6i3+R7aQOT6CazTXhXqr/531Ks2g6KO uREF9fi+9zjcQZAyWJ8JWoRotKLI4tDvnUWh7S8Nzy1NDxZGm/4o72vvkJPRV1d32a wpkjOREkFvio444O0ZKyL3dC8zfLAR47pk52qnE4OrGDllugTIYXun+ziZahauLueM rXnswh8xu0LtGxWfwJk6+gdjw7Oy5jsPS5krxyBdcUgWtUiQDInEewOQRk8Uqfrf91 hTNC7uDbIz66YhPZi/A2KzLIkZqb7afAHwgPm+F8Wu+g/g1AULWN057B2lOCDNGrOj Czlv7qR+FuL3A== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry sequence and sc7 entry firmware is run from COP/BPMP-Lite. So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence for Tegra210. This patch has fix for leaving the COP IRQ enabled for Tegra210 during interrupt controller suspend operation. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/irqchip/irq-tegra.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c index e1f771c72fc4..851f88cef508 100644 --- a/drivers/irqchip/irq-tegra.c +++ b/drivers/irqchip/irq-tegra.c @@ -44,6 +44,7 @@ static unsigned int num_ictlrs; struct tegra_ictlr_soc { unsigned int num_ictlrs; + bool supports_sc7; }; static const struct tegra_ictlr_soc tegra20_ictlr_soc = { @@ -56,6 +57,7 @@ static const struct tegra_ictlr_soc tegra30_ictlr_soc = { static const struct tegra_ictlr_soc tegra210_ictlr_soc = { .num_ictlrs = 6, + .supports_sc7 = true, }; static const struct of_device_id ictlr_matches[] = { @@ -67,6 +69,7 @@ static const struct of_device_id ictlr_matches[] = { struct tegra_ictlr_info { void __iomem *base[TEGRA_MAX_NUM_ICTLRS]; + const struct tegra_ictlr_soc *soc; #ifdef CONFIG_PM_SLEEP u32 cop_ier[TEGRA_MAX_NUM_ICTLRS]; u32 cop_iep[TEGRA_MAX_NUM_ICTLRS]; @@ -147,8 +150,20 @@ static int tegra_ictlr_suspend(void) lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER); lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS); - /* Disable COP interrupts */ - writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); + /* + * AVP/COP/BPMP-Lite is the Tegra boot processor. + * + * Tegra210 system suspend flow uses sc7entry firmware which + * is executed by COP/BPMP and it includes disabling COP IRQ, + * clamping CPU rail, turning off VDD_CPU, and preparing the + * system to go to SC7/LP0. + * + * COP/BPMP wakes up when COP IRQ is triggered and runs + * sc7entry-firmware. So need to keep COP interrupt enabled. + */ + if (!lic->soc->supports_sc7) + /* Disable COP interrupts if SC7 is not supported */ + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); /* Disable CPU interrupts */ writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); @@ -339,6 +354,7 @@ static int __init tegra_ictlr_init(struct device_node *node, goto out_unmap; } + lic->soc = soc; tegra_ictlr_syscore_init(); pr_info("%pOF: %d interrupts forwarded to %pOF\n", From patchwork Fri Jun 28 02:12:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123846 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Um3OwDcV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgMN5y7Cz9sND for ; Fri, 28 Jun 2019 12:14:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726992AbfF1COs (ORCPT ); Thu, 27 Jun 2019 22:14:48 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:17594 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726426AbfF1CNg (ORCPT ); Thu, 27 Jun 2019 22:13:36 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:33 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:34 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:34 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:33 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:33 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:33 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:33 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 02/18] pinctrl: tegra: Add suspend and resume support Date: Thu, 27 Jun 2019 19:12:36 -0700 Message-ID: <1561687972-19319-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688013; bh=6XVtmPiEo6fFZCuCiwnb+UkS0vaYrf4FcEseKnc+izw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Um3OwDcVHDIRK3fw70C6JDSsK7KNL+Be94prmyNCuyuDnCI43A5Rh6oDEcTMG63Kz TsOce2FU6YyUW0HAQ72qXwWXofnsNc98mbliOdeXwxxK2cfJ/cSMRV8bC+dvKt9nyu Y89O0CS7G1QhcNjeQKLmh3NXruppoumz80bfrTZd6hBEvPtot2I1dwL9sHsmXEN3/v 0Wj1dw8+9Tleh12YGFBqelgsBrz6N8DBVtiaEOP29eshytynzSOIC91gvLv5+0Iju+ 73jNbTW8/lVUHkuXG1JiywOxQFAG/cGqBTMnWCPqMtbm97ec9bvWBe1DI7HU/gAgZJ wNhJLBAQhYNTg== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds support for Tegra pinctrl driver suspend and resume. During suspend, context of all pinctrl registers are stored and on resume they are all restored to have all the pinmux and pad configuration for normal operation. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/pinctrl/tegra/pinctrl-tegra.c | 52 ++++++++++++++++++++++++++++++++ drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++ drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 + 3 files changed, 56 insertions(+) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 34596b246578..e7c0a1011cba 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -621,6 +621,43 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) } } +static int tegra_pinctrl_suspend(struct device *dev) +{ + struct tegra_pmx *pmx = dev_get_drvdata(dev); + u32 *backup_regs = pmx->backup_regs; + u32 *regs; + unsigned int i, j; + + for (i = 0; i < pmx->nbanks; i++) { + regs = pmx->regs[i]; + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++) + *backup_regs++ = readl(regs++); + } + + return pinctrl_force_sleep(pmx->pctl); +} + +static int tegra_pinctrl_resume(struct device *dev) +{ + struct tegra_pmx *pmx = dev_get_drvdata(dev); + u32 *backup_regs = pmx->backup_regs; + u32 *regs; + unsigned int i, j; + + for (i = 0; i < pmx->nbanks; i++) { + regs = pmx->regs[i]; + for (j = 0; j < pmx->reg_bank_size[i] / 4; j++) + writel(*backup_regs++, regs++); + } + + return 0; +} + +const struct dev_pm_ops tegra_pinctrl_pm = { + .suspend = &tegra_pinctrl_suspend, + .resume = &tegra_pinctrl_resume +}; + static bool gpio_node_has_range(const char *compatible) { struct device_node *np; @@ -645,6 +682,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, int i; const char **group_pins; int fn, gn, gfn; + unsigned long backup_regs_size = 0; pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); if (!pmx) @@ -697,6 +735,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, res = platform_get_resource(pdev, IORESOURCE_MEM, i); if (!res) break; + backup_regs_size += resource_size(res); } pmx->nbanks = i; @@ -705,11 +744,24 @@ int tegra_pinctrl_probe(struct platform_device *pdev, if (!pmx->regs) return -ENOMEM; + pmx->reg_bank_size = devm_kcalloc(&pdev->dev, pmx->nbanks, + sizeof(*pmx->reg_bank_size), + GFP_KERNEL); + if (!pmx->reg_bank_size) + return -ENOMEM; + + pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, + GFP_KERNEL); + if (!pmx->backup_regs) + return -ENOMEM; + for (i = 0; i < pmx->nbanks; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(pmx->regs[i])) return PTR_ERR(pmx->regs[i]); + + pmx->reg_bank_size[i] = resource_size(res); } pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 287702660783..55456f8d44cf 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -17,6 +17,8 @@ struct tegra_pmx { int nbanks; void __iomem **regs; + size_t *reg_bank_size; + u32 *backup_regs; }; enum tegra_pinconf_param { @@ -193,6 +195,7 @@ struct tegra_pinctrl_soc_data { bool drvtype_in_mux; }; +extern const struct dev_pm_ops tegra_pinctrl_pm; int tegra_pinctrl_probe(struct platform_device *pdev, const struct tegra_pinctrl_soc_data *soc_data); #endif diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c index 0b56ad5c9c1c..edd3f4606cdb 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c @@ -1571,6 +1571,7 @@ static struct platform_driver tegra210_pinctrl_driver = { .driver = { .name = "tegra210-pinctrl", .of_match_table = tegra210_pinctrl_of_match, + .pm = &tegra_pinctrl_pm, }, .probe = tegra210_pinctrl_probe, }; From patchwork Fri Jun 28 02:12:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123848 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Esh937kS"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgMR26H7z9sND for ; Fri, 28 Jun 2019 12:14:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726987AbfF1COs (ORCPT ); Thu, 27 Jun 2019 22:14:48 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19569 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726558AbfF1CNg (ORCPT ); Thu, 27 Jun 2019 22:13:36 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:32 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:34 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 27 Jun 2019 19:13:34 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:33 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:33 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:33 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:33 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 03/18] clk: tegra: Save and restore divider rate Date: Thu, 27 Jun 2019 19:12:37 -0700 Message-ID: <1561687972-19319-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688012; bh=Nd1v90bh7Ho/ojHQIob7we6JLN3yOOpS5vD9L3b3q98=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Esh937kSEIxLY5xzF34aqQUtuPveBpeB1+nKe2kKdtZPlDKZvqf40pCp06i5UiEB1 xXRmpZoHaizLBqysekD4RVh1r325jzvpheJ8ZfQeYberKYZPpErAZl+XEebBG5BnN5 VYoAyMorKOAx6j5HoBLbFfzBAmPJiuWDK1p8o1IuNhCgdctGwpvgGAlCxu+uW89TuL LrB190AUWCAb47w+UrRQToxSDwJmKqKuYOfW9l8l2MEz3yywJjTV9mSRPHSBIg3Ow0 C2KdNSdMxUjHEoH7yh6nHoTYg67JNc8rPrH+XgJOyGl2IV0Cr6Ov38s2Nd1i1c7h2n dp00VSTv97YPw== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch implements context save and restore for clock divider. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry the context of clock divider is saved and on resume context is restored back for normal operation. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-divider.c | 23 +++++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index e76731fb7d69..ecb7ff9ce97e 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -109,10 +109,33 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int clk_divider_save_context(struct clk_hw *hw) +{ + struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + divider->rate = clk_frac_div_recalc_rate(hw, parent_rate); + + return 0; +} + +static void clk_divider_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + if (clk_frac_div_set_rate(hw, divider->rate, parent_rate) < 0) + WARN_ON(1); +} + const struct clk_ops tegra_clk_frac_div_ops = { .recalc_rate = clk_frac_div_recalc_rate, .set_rate = clk_frac_div_set_rate, .round_rate = clk_frac_div_round_rate, + .save_context = clk_divider_save_context, + .restore_context = clk_divider_restore_context, }; struct clk *tegra_clk_register_divider(const char *name, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 905bf1096558..83623f5f55f3 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -42,6 +42,7 @@ struct clk *tegra_clk_register_sync_source(const char *name, * @width: width of the divider bit field * @frac_width: width of the fractional bit field * @lock: register lock + * @rate: rate during suspend and resume * * Flags: * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. @@ -62,6 +63,7 @@ struct tegra_clk_frac_div { u8 width; u8 frac_width; spinlock_t *lock; + unsigned long rate; }; #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) From patchwork Fri Jun 28 02:12:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123816 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="O9eOYxdk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgKt1wBjz9s7h for ; Fri, 28 Jun 2019 12:13:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726596AbfF1CNg (ORCPT ); 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Thu, 27 Jun 2019 19:13:33 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 04/18] clk: tegra: pllout: Save and restore pllout context Date: Thu, 27 Jun 2019 19:12:38 -0700 Message-ID: <1561687972-19319-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688017; bh=TqspXxSUMOnx+v+IVW31w3ws6+ZGaWHJIhoopYd5LSU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=O9eOYxdk9m0jJ/CVgPsOnW0OnW938t2EQiT1151+6g3Lit9Z8gDyYPABNQTTy8Awu YHHmI01jIgTFTk4hEKSZlP1zpK92A9m+90MolMu599U+WMvnoTb8X0XUOGiHfrXZZj bM761ThcCSOp3tE3SYkCfCAAld4E/glVN5XlERjiRXRCdl8HnTbT4N0VvQt9xkVzNG box83on4PX74XOKn1XcRAwl2KNaVCtHSSrIFkNIQPnAH7X7oXAgfB7VvU22F6K2eiY yayQ/r3PRgApygMSu8WLDqfEZUsH18QoHgNw/wWIomuC3LKIeRo9ouRoU2ABqpTaFy JZvXRq2rXZXfw== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch implements save and restore of pllout context. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry the state of pllout is saved and on resume it is restored back to have pllout in same state as before suspend. pllout rate is saved and restore in clock divider so it will be at same rate as before suspend when pllout state is restored. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-pll-out.c | 28 ++++++++++++++++++++++++++++ drivers/clk/tegra/clk-tegra210.c | 3 ++- drivers/clk/tegra/clk.h | 9 +++++++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c index 35f2bf00e1e6..8f26a7e3e579 100644 --- a/drivers/clk/tegra/clk-pll-out.c +++ b/drivers/clk/tegra/clk-pll-out.c @@ -69,10 +69,38 @@ static void clk_pll_out_disable(struct clk_hw *hw) spin_unlock_irqrestore(pll_out->lock, flags); } +static int tegra_clk_pll_out_save_context(struct clk_hw *hw) +{ + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); + + if (pll_out->flags & TEGRA_PLLRE_OUT) + pll_out->pllout_ctx = readl_relaxed(pll_out->reg); + else + pll_out->pllout_ctx = clk_hw_get_rate(hw); + + return 0; +} + +static void tegra_clk_pll_out_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); + + if (pll_out->flags & TEGRA_PLLRE_OUT) { + writel_relaxed(pll_out->pllout_ctx, pll_out->reg); + } else { + if (!__clk_get_enable_count(hw->clk)) + clk_pll_out_disable(hw); + else + clk_pll_out_enable(hw); + } +} + const struct clk_ops tegra_clk_pll_out_ops = { .is_enabled = clk_pll_out_is_enabled, .enable = clk_pll_out_enable, .disable = clk_pll_out_disable, + .save_context = tegra_clk_pll_out_save_context, + .restore_context = tegra_clk_pll_out_restore_context, }; struct clk *tegra_clk_register_pll_out(const char *name, diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index ac1d27a8c650..cbd77658dcf7 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3195,7 +3195,8 @@ static void __init tegra210_pll_init(void __iomem *clk_base, 8, 8, 1, NULL); clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div", clk_base + PLLRE_OUT1, 1, 0, - CLK_SET_RATE_PARENT, 0, NULL); + CLK_SET_RATE_PARENT, TEGRA_PLLRE_OUT, + NULL); clks[TEGRA210_CLK_PLL_RE_OUT1] = clk; /* PLLE */ diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 83623f5f55f3..fb29a8c27873 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -439,6 +439,12 @@ struct clk *tegra_clk_register_pllu_tegra210(const char *name, * @rst_bit_idx: bit to reset PLL divider * @lock: register lock * @flags: hardware-specific flags + * @pllout_ctx: pllout context to save and restore during suspend + * and resume + * + * Flags: + * TEGRA_PLLRE_OUT - This flag indicates that it is PLLRE_OUT and is used to + * identify PLLRE_OUT during clk_pll_out save and restore. */ struct tegra_clk_pll_out { struct clk_hw hw; @@ -447,8 +453,11 @@ struct tegra_clk_pll_out { u8 rst_bit_idx; spinlock_t *lock; u8 flags; + unsigned int pllout_ctx; }; +#define TEGRA_PLLRE_OUT BIT(0) + #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) extern const struct clk_ops tegra_clk_pll_out_ops; From patchwork Fri Jun 28 02:12:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123844 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="exw17T+D"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgMF4Q8Yz9sNC for ; Fri, 28 Jun 2019 12:14:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726571AbfF1COg (ORCPT ); Thu, 27 Jun 2019 22:14:36 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:17605 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726567AbfF1CNh (ORCPT ); Thu, 27 Jun 2019 22:13:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:33 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:34 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:34 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:34 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:33 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:34 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:33 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 05/18] clk: tegra: pll: Save and restore pll context Date: Thu, 27 Jun 2019 19:12:39 -0700 Message-ID: <1561687972-19319-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688014; bh=I02FhtmoD7Cwn4Ky9mX1RLOrZYRQcu3mM4I+flYne6Q=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=exw17T+D3RT/pqnd9PcnVGVpf4+HSwjai0hThAPP36hZTFDBkcEndI2+EmD5l7Zxt 4U1RmcnqZ7sPAl3sydWo0quoTXbIsnnJqS1fRQEHv5Gs0ZieNbu1SBj6XqIl6iCjUd lLPLzJps0H4zfoPtWxog7iG17ds7MzlnMxZ0wD4gR03U0jmgh/zfQk7U1MqCFILcTG 1WwKyY9JJdHOchVac4JDmZO9dO936eg3I/e4JAswOh558s3HXidmVQElRzMtpfHNZ1 h6CBtmawxwdO30dVsoMLYpq6vksT1hGvdNDgeN1Tq5pcgOYNhYtjq2DdVj3O2DOMqO 0G9RswQRjQM2Q== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch implements save and restore of PLL context. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry pll rate is stored and on resume it is restored back along with its state. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-pll.c | 121 ++++++++++++++++++++++++++++----------- drivers/clk/tegra/clk-tegra210.c | 2 +- drivers/clk/tegra/clk.h | 10 +++- 3 files changed, 99 insertions(+), 34 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 1583f5fc992f..3686ada022aa 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1008,6 +1008,59 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, return rate; } +void tegra_clk_sync_state_pll(struct clk_hw *hw) +{ + if (!__clk_get_enable_count(hw->clk)) + clk_pll_disable(hw); + else + clk_pll_enable(hw); +} + +static int tegra_clk_pll_save_context(struct clk_hw *hw) +{ + struct tegra_clk_pll *pll = to_clk_pll(hw); + u32 val = 0; + + pll->rate = clk_hw_get_rate(hw); + + if (pll->params->flags & TEGRA_PLLMB) + val = pll_readl_base(pll); + else if (pll->params->flags & TEGRA_PLLRE) + val = pll_readl_base(pll) & divp_mask_shifted(pll); + + pll->pllbase_ctx = val; + + return 0; +} + +static void tegra_clk_pll_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_pll *pll = to_clk_pll(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + u32 val; + + if (clk_pll_is_enabled(hw)) + return; + + if (pll->params->flags & TEGRA_PLLMB) { + pll_writel_base(pll->pllbase_ctx, pll); + } else if (pll->params->flags & TEGRA_PLLRE) { + val = pll_readl_base(pll); + val &= ~(divp_mask_shifted(pll)); + pll_writel_base(pll->pllbase_ctx | val, pll); + } + + if (pll->params->set_defaults) + pll->params->set_defaults(pll); + + clk_pll_set_rate(hw, pll->rate, parent_rate); + + /* do not sync pllx state here. pllx is sync'd after dfll resume */ + if (!(pll->params->flags & TEGRA_PLLX)) + tegra_clk_sync_state_pll(hw); +} + const struct clk_ops tegra_clk_pll_ops = { .is_enabled = clk_pll_is_enabled, .enable = clk_pll_enable, @@ -1015,6 +1068,8 @@ const struct clk_ops tegra_clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_round_rate, .set_rate = clk_pll_set_rate, + .save_context = tegra_clk_pll_save_context, + .restore_context = tegra_clk_pll_restore_context, }; const struct clk_ops tegra_clk_plle_ops = { @@ -1802,6 +1857,27 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw) return ret; } + +static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll) +{ + u32 val, val_aux; + + /* ensure parent is set to pll_ref */ + val = pll_readl_base(pll); + val_aux = pll_readl(pll->params->aux_reg, pll); + + if (val & PLL_BASE_ENABLE) { + if ((val_aux & PLLE_AUX_PLLRE_SEL) || + (val_aux & PLLE_AUX_PLLP_SEL)) + WARN(1, "pll_e enabled with unsupported parent %s\n", + (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : + "pll_re_vco"); + } else { + val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); + pll_writel(val_aux, pll->params->aux_reg, pll); + fence_udelay(1, pll->clk_base); + } +} #endif static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, @@ -2214,27 +2290,12 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name, { struct tegra_clk_pll *pll; struct clk *clk; - u32 val, val_aux; pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); if (IS_ERR(pll)) return ERR_CAST(pll); - /* ensure parent is set to pll_re_vco */ - - val = pll_readl_base(pll); - val_aux = pll_readl(pll_params->aux_reg, pll); - - if (val & PLL_BASE_ENABLE) { - if ((val_aux & PLLE_AUX_PLLRE_SEL) || - (val_aux & PLLE_AUX_PLLP_SEL)) - WARN(1, "pll_e enabled with unsupported parent %s\n", - (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : - "pll_re_vco"); - } else { - val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); - pll_writel(val_aux, pll_params->aux_reg, pll); - } + _clk_plle_tegra_init_parent(pll); clk = _tegra_clk_register_pll(pll, name, parent_name, flags, &tegra_clk_plle_tegra114_ops); @@ -2276,6 +2337,8 @@ static const struct clk_ops tegra_clk_pllss_ops = { .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_ramp_round_rate, .set_rate = clk_pllxc_set_rate, + .save_context = tegra_clk_pll_save_context, + .restore_context = tegra_clk_pll_restore_context, }; struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, @@ -2375,6 +2438,7 @@ struct clk *tegra_clk_register_pllre_tegra210(const char *name, pll_params->vco_min = pll_params->adjust_vco(pll_params, parent_rate); + pll_params->flags |= TEGRA_PLLRE; pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); if (IS_ERR(pll)) return ERR_CAST(pll); @@ -2520,11 +2584,19 @@ static void clk_plle_tegra210_disable(struct clk_hw *hw) spin_unlock_irqrestore(pll->lock, flags); } +static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_pll *pll = to_clk_pll(hw); + + _clk_plle_tegra_init_parent(pll); +} + static const struct clk_ops tegra_clk_plle_tegra210_ops = { .is_enabled = clk_plle_tegra210_is_enabled, .enable = clk_plle_tegra210_enable, .disable = clk_plle_tegra210_disable, .recalc_rate = clk_pll_recalc_rate, + .restore_context = tegra_clk_plle_t210_restore_context, }; struct clk *tegra_clk_register_plle_tegra210(const char *name, @@ -2535,27 +2607,12 @@ struct clk *tegra_clk_register_plle_tegra210(const char *name, { struct tegra_clk_pll *pll; struct clk *clk; - u32 val, val_aux; pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); if (IS_ERR(pll)) return ERR_CAST(pll); - /* ensure parent is set to pll_re_vco */ - - val = pll_readl_base(pll); - val_aux = pll_readl(pll_params->aux_reg, pll); - - if (val & PLLE_BASE_ENABLE) { - if ((val_aux & PLLE_AUX_PLLRE_SEL) || - (val_aux & PLLE_AUX_PLLP_SEL)) - WARN(1, "pll_e enabled with unsupported parent %s\n", - (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : - "pll_re_vco"); - } else { - val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); - pll_writel(val_aux, pll_params->aux_reg, pll); - } + _clk_plle_tegra_init_parent(pll); clk = _tegra_clk_register_pll(pll, name, parent_name, flags, &tegra_clk_plle_tegra210_ops); diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index cbd77658dcf7..7f90442462af 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -1597,7 +1597,7 @@ static struct tegra_clk_pll_params pll_x_params = { .pdiv_tohw = pll_qlin_pdiv_to_hw, .div_nmp = &pllx_nmp, .freq_table = pll_x_freq_table, - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, + .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLLX, .dyn_ramp = tegra210_pllx_dyn_ramp, .set_defaults = tegra210_pllx_set_defaults, .calc_rate = tegra210_pll_fixed_mdiv_cfg, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index fb29a8c27873..8532f5150091 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -235,6 +235,8 @@ struct tegra_clk_pll; * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This * flag indicated that it is PLLMB. * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output + * TEGRA_PLLRE - Used to indicate that it is PLLRE. + * TEGRA_PLLX - Used to indicate that it is PLLX. */ struct tegra_clk_pll_params { unsigned long input_min; @@ -301,6 +303,8 @@ struct tegra_clk_pll_params { #define TEGRA_MDIV_NEW BIT(11) #define TEGRA_PLLMB BIT(12) #define TEGRA_PLL_VCO_OUT BIT(13) +#define TEGRA_PLLRE BIT(14) +#define TEGRA_PLLX BIT(15) /** * struct tegra_clk_pll - Tegra PLL clock @@ -310,6 +314,8 @@ struct tegra_clk_pll_params { * @pmc: address of PMC, required to read override bits * @lock: register lock * @params: PLL parameters + * @rate: rate during system suspend and resume + * @pllbase_ctx: pll base register value during suspend and resume */ struct tegra_clk_pll { struct clk_hw hw; @@ -317,6 +323,8 @@ struct tegra_clk_pll { void __iomem *pmc; spinlock_t *lock; struct tegra_clk_pll_params *params; + unsigned long rate; + u32 pllbase_ctx; }; #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) @@ -840,7 +848,7 @@ u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, u8 frac_width, u8 flags); - +void tegra_clk_sync_state_pll(struct clk_hw *hw); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Fri Jun 28 02:12:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123837 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ZaXDCBGn"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgLz0T7zz9sNw for ; Fri, 28 Jun 2019 12:14:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726913AbfF1COW (ORCPT ); Thu, 27 Jun 2019 22:14:22 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5491 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726571AbfF1CNh (ORCPT ); Thu, 27 Jun 2019 22:13:37 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:37 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:34 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 27 Jun 2019 19:13:34 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:33 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:34 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:34 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 06/18] clk: tegra: Save and restore CPU and System clocks context Date: Thu, 27 Jun 2019 19:12:40 -0700 Message-ID: <1561687972-19319-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688017; bh=NfQJBDxSGbJbt5Ym1EvGOs1W2N3e2IDBWgFgSYrtpgo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ZaXDCBGnYZTU4FSSwrGMqEon3+S0XNFR+azLF69QT1R3QPXymm8KRCPOa76IhFLV0 UJcOPwmcr+nIxcWPr4A/9eC21Fxav0jPkxENufjQnjLVGWHac34uu8ZU0bdw7+8UNu utkjtbBOxgqmUku2QMvJb3c4/CiPgMOCNyvLSE+yoo+EqOYK7G8JKTIp1cSGte1duP sn3XMjDe0qcxSicX/FIuZJYjmjNO5shN6nJnxHN1jQfmS8Jo1M2/PsaQYuvO1oLgY1 NnIOAQk85FBtKqaTGGwSQG17m7XLvW7wOdATOhUKXhA5UNl6xxSHhstJ31Vw+38Nfu 6DV7ESEmuaunA== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org During system suspend state, core power goes off and looses all the CAR controller register settings. This patch creates APIs for saving and restoring the context of Tegra CPUG, CPULP and SCLK. CPU and System clock context includes - CPUG, CPULP, and SCLK burst policy settings for clock sourcea of all their normal states. - SCLK divisor and System clock rate for restoring SCLK, AHB and APB rates on resume. - OSC_DIV settings which are used as reference clock input to some PLLs. - SPARE_REG and CLK_MASK settings. These APIs are used in Tegra210 clock driver during suspend and resume operation. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra-super-gen4.c | 4 -- drivers/clk/tegra/clk.c | 80 ++++++++++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 14 ++++++ 3 files changed, 94 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index cdfe7c9697e1..ed69ec4d883e 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -19,10 +19,6 @@ #define PLLX_MISC2 0x514 #define PLLX_MISC3 0x518 -#define CCLKG_BURST_POLICY 0x368 -#define CCLKLP_BURST_POLICY 0x370 -#define SCLK_BURST_POLICY 0x028 -#define SYSTEM_CLK_RATE 0x030 #define SCLK_DIVIDER 0x2c static DEFINE_SPINLOCK(sysrate_lock); diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 573e3c967ae1..9e863362d2bf 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -70,6 +70,12 @@ static struct clk **clks; static int clk_num; static struct clk_onecell_data clk_data; +static u32 cclkg_burst_policy_ctx[2]; +static u32 cclklp_burst_policy_ctx[2]; +static u32 sclk_burst_policy_ctx[2]; +static u32 sys_clk_divisor_ctx, system_rate_ctx; +static u32 spare_ctx, misc_clk_enb_ctx, clk_arm_ctx; + /* Handlers for SoC-specific reset lines */ static int (*special_reset_assert)(unsigned long); static int (*special_reset_deassert)(unsigned long); @@ -199,6 +205,80 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid) } } +void tegra_cclkg_burst_policy_save_context(void) +{ + unsigned int i; + + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) + cclkg_burst_policy_ctx[i] = readl_relaxed(clk_base + + CCLKG_BURST_POLICY + + (i * 4)); +} + +void tegra_cclkg_burst_policy_restore_context(void) +{ + unsigned int i; + + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) + writel_relaxed(cclkg_burst_policy_ctx[i], + clk_base + CCLKG_BURST_POLICY + (i * 4)); + + fence_udelay(2, clk_base); +} + +void tegra_sclk_cclklp_burst_policy_save_context(void) +{ + unsigned int i; + + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) { + cclklp_burst_policy_ctx[i] = readl_relaxed(clk_base + + CCLKLP_BURST_POLICY + + (i * 4)); + + sclk_burst_policy_ctx[i] = readl_relaxed(clk_base + + SCLK_BURST_POLICY + + (i * 4)); + } + + sys_clk_divisor_ctx = readl_relaxed(clk_base + SYS_CLK_DIV); + system_rate_ctx = readl_relaxed(clk_base + SYSTEM_CLK_RATE); + spare_ctx = readl_relaxed(clk_base + SPARE_REG0); + misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB); + clk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM); +} + +void tegra_sclk_cpulp_burst_policy_restore_context(void) +{ + unsigned int i; + u32 val; + + /* + * resume SCLK and CPULP clocks + * for SCLk, set safe dividers values first and then restore source + * and dividers + */ + + writel_relaxed(0x1, clk_base + SYSTEM_CLK_RATE); + val = readl_relaxed(clk_base + SYS_CLK_DIV); + if (val < sys_clk_divisor_ctx) + writel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV); + + fence_udelay(2, clk_base); + + for (i = 0; i < BURST_POLICY_REG_SIZE; i++) { + writel_relaxed(cclklp_burst_policy_ctx[i], + clk_base + CCLKLP_BURST_POLICY + (i * 4)); + writel_relaxed(sclk_burst_policy_ctx[i], + clk_base + SCLK_BURST_POLICY + (i * 4)); + } + + writel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV); + writel_relaxed(system_rate_ctx, clk_base + SYSTEM_CLK_RATE); + writel_relaxed(spare_ctx, clk_base + SPARE_REG0); + writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB); + writel_relaxed(clk_arm_ctx, clk_base + CLK_MASK_ARM); +} + struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) { clk_base = regs; diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 8532f5150091..c66b0a73bb01 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -10,6 +10,16 @@ #include #include +#define SCLK_BURST_POLICY 0x28 +#define SYSTEM_CLK_RATE 0x30 +#define CLK_MASK_ARM 0x44 +#define MISC_CLK_ENB 0x48 +#define CCLKG_BURST_POLICY 0x368 +#define CCLKLP_BURST_POLICY 0x370 +#define SYS_CLK_DIV 0x400 +#define SPARE_REG0 0x55c +#define BURST_POLICY_REG_SIZE 2 + /** * struct tegra_clk_sync_source - external clock source from codec * @@ -849,6 +859,10 @@ int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, u8 frac_width, u8 flags); void tegra_clk_sync_state_pll(struct clk_hw *hw); +void tegra_cclkg_burst_policy_save_context(void); +void tegra_cclkg_burst_policy_restore_context(void); +void tegra_sclk_cclklp_burst_policy_save_context(void); +void tegra_sclk_cpulp_burst_policy_restore_context(void); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Fri Jun 28 02:12:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123851 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ru2F0sXy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgMW68rXz9sNp for ; Fri, 28 Jun 2019 12:15:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726622AbfF1CO6 (ORCPT ); Thu, 27 Jun 2019 22:14:58 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19578 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726574AbfF1CNg (ORCPT ); Thu, 27 Jun 2019 22:13:36 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:33 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:35 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 27 Jun 2019 19:13:35 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:34 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:34 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:33 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:34 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 07/18] clk: tegra: Support for saving and restoring OSC context Date: Thu, 27 Jun 2019 19:12:41 -0700 Message-ID: <1561687972-19319-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688013; bh=2YFtJYfYZEkx9Rsc+PePUh2qyM9iqhHjKzUjU/RdnjE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ru2F0sXyh8TG8aU8SgAnqEObkpZejB+BCea1b9og7ZdN4iE/v87ZYy5gSa1GIkXrz 9SKFvyCMUlfXiLyYKy3dJ1SftIWWlXbZWzLU7kzztUjJWIDPYAp6ay+Vbr/mHRTRiE lRc/TAwSPEOvECwL4dajrFXcftD5b5jZ/5H2J5DcV0RnJcqXdQFNEMBO2YOTLpfYZX fNoFb+n6exbQOwV+6/UEUOC+XdSMhwQ4FVLMoWA8dwYd0WtdN4kBNvzEVvdHOUzgSt l0/Z2km643rWaGpb/T4ADmkS/+JQZPgYshOcPI6GLjaLZhcaaUtxFghVTvOMANbQc5 GdlQQ0TyT7K/Q== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds support for storing OSC clock frequency and the drive-strength during OSC clock init and creates an API to restore OSC control register value from the saved context. This API is invoked by Tegra210 clock driver during system resume to restore the OSC clock settings. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra-fixed.c | 14 ++++++++++++++ drivers/clk/tegra/clk.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c index 8d91b2b191cf..e8df0ccbffd0 100644 --- a/drivers/clk/tegra/clk-tegra-fixed.c +++ b/drivers/clk/tegra/clk-tegra-fixed.c @@ -17,7 +17,10 @@ #define OSC_CTRL 0x50 #define OSC_CTRL_OSC_FREQ_SHIFT 28 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 +#define OSC_CTRL_MASK (0x3f2 | \ + (0xf << OSC_CTRL_OSC_FREQ_SHIFT)) +static u32 osc_ctrl_ctx; int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, unsigned long *input_freqs, unsigned int num, unsigned int clk_m_div, unsigned long *osc_freq, @@ -29,6 +32,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, unsigned osc_idx; val = readl_relaxed(clk_base + OSC_CTRL); + osc_ctrl_ctx = val & OSC_CTRL_MASK; osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT; if (osc_idx < num) @@ -96,3 +100,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks) *dt_clk = clk; } } + +void tegra_clk_osc_resume(void __iomem *clk_base) +{ + u32 val; + + val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK; + val |= osc_ctrl_ctx; + writel_relaxed(val, clk_base + OSC_CTRL); + fence_udelay(2, clk_base); +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index c66b0a73bb01..a687ed6127b6 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -863,6 +863,7 @@ void tegra_cclkg_burst_policy_save_context(void); void tegra_cclkg_burst_policy_restore_context(void); void tegra_sclk_cclklp_burst_policy_save_context(void); void tegra_sclk_cpulp_burst_policy_restore_context(void); +void tegra_clk_osc_resume(void __iomem *clk_base); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Fri Jun 28 02:12:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123841 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="njilldqn"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgMB3zYxz9sNd for ; Fri, 28 Jun 2019 12:14:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726961AbfF1COh (ORCPT ); Thu, 27 Jun 2019 22:14:37 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:17614 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726572AbfF1CNh (ORCPT ); Thu, 27 Jun 2019 22:13:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:34 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:35 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:35 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:34 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:34 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:34 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:34 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 08/18] clk: tegra: Add suspend resume support for DFLL Date: Thu, 27 Jun 2019 19:12:42 -0700 Message-ID: <1561687972-19319-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688014; bh=dps+xdpNYqPp4cSiwoi1+rWcYiqKiL43QEvLjCGhFJY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=njilldqndHtEh9BLnwi0r+GhoSuQpcuNohDMCN8MwQDfHyooYR10Hs/teKY3E8LAQ hRPzmidxR71jdttUwIdZnFWEyuqWbQHirDZraeVMJcQj8/TiPBpintC+dvQUBAJ+tc qW2EM+Zdne/10N+uSqBilqG+TUwknAy5Qgd5kBgo8hlz07vfMAsGVHSI3Hp3pqWXbT RsKz8W0U+O3DUiLQESy4w19oLYuOqBXkmeFEPtVFnlnR4ik8d8ZyLHYyuJJQBjy7F0 0icroQtj8p3MTGOnmqC0dsl6bxaRuEfLAGwS9y/Pr6yrFWDkxmMPtnVvCrEcQqL40x RkRvayrYU2kgQ== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch creates APIs for supporting Tegra210 clock driver to perform DFLL suspend and resume operation. During suspend, DFLL mode is saved and on resume Tegra210 clock driver invokes DFLL resume API to re-initialize DFLL to enable target device clock in open loop mode or closed loop mode. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-dfll.c | 78 ++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/tegra/clk-dfll.h | 2 ++ 2 files changed, 80 insertions(+) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index f8688c2ddf1a..a1f37cf99b00 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -277,6 +277,7 @@ struct tegra_dfll { unsigned long dvco_rate_min; enum dfll_ctrl_mode mode; + enum dfll_ctrl_mode resume_mode; enum dfll_tune_range tune_range; struct dentry *debugfs_dir; struct clk_hw dfll_clk_hw; @@ -1864,6 +1865,83 @@ static int dfll_fetch_common_params(struct tegra_dfll *td) } /* + * tegra_dfll_suspend + * @pdev: DFLL instance + * + * dfll controls clock/voltage to other devices, including CPU. Therefore, + * dfll driver pm suspend callback does not stop cl-dvfs operations. + */ +void tegra_dfll_suspend(struct platform_device *pdev) +{ + struct tegra_dfll *td = dev_get_drvdata(&pdev->dev); + + if (!td) + return; + + if (td->mode <= DFLL_DISABLED) + return; + + td->resume_mode = td->mode; + switch (td->mode) { + case DFLL_CLOSED_LOOP: + dfll_set_mode(td, DFLL_CLOSED_LOOP); + dfll_set_frequency_request(td, &td->last_req); + + dfll_unlock(td); + break; + default: + break; + } +} + +/** + * tegra_dfll_resume - reprogram the DFLL after context-loss + * @pdev: DFLL instance + * + * Re-initialize and enable target device clock in open loop mode. Called + * directly from SoC clock resume syscore operation. Closed loop will be + * re-entered in platform syscore ops as well after CPU clock source is + * switched to DFLL in open loop. + */ +void tegra_dfll_resume(struct platform_device *pdev, bool on_dfll) +{ + struct tegra_dfll *td = dev_get_drvdata(&pdev->dev); + + if (!td) + return; + + if (on_dfll) { + if (td->resume_mode == DFLL_CLOSED_LOOP) + dfll_lock(td); + td->resume_mode = DFLL_DISABLED; + return; + } + + reset_control_deassert(td->dvco_rst); + + pm_runtime_get(td->dev); + + /* Re-init DFLL */ + dfll_init_out_if(td); + dfll_set_default_params(td); + dfll_set_open_loop_config(td); + + pm_runtime_put(td->dev); + + /* Restore last request and mode up to open loop */ + switch (td->resume_mode) { + case DFLL_CLOSED_LOOP: + case DFLL_OPEN_LOOP: + dfll_set_mode(td, DFLL_OPEN_LOOP); + if (td->pmu_if == TEGRA_DFLL_PMU_I2C) + dfll_i2c_set_output_enabled(td, false); + break; + default: + break; + } +} + +/* * API exported to per-SoC platform drivers */ diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index 1b14ebe7268b..c21fc2061a20 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -40,6 +40,8 @@ struct tegra_dfll_soc_data { int tegra_dfll_register(struct platform_device *pdev, struct tegra_dfll_soc_data *soc); struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev); +void tegra_dfll_suspend(struct platform_device *pdev); +void tegra_dfll_resume(struct platform_device *pdev, bool on_dfll); int tegra_dfll_runtime_suspend(struct device *dev); int tegra_dfll_runtime_resume(struct device *dev); From patchwork Fri Jun 28 02:12:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123828 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="DBm1DHbW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgLT0dL5z9sNt for ; Fri, 28 Jun 2019 12:14:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726859AbfF1COG (ORCPT ); Thu, 27 Jun 2019 22:14:06 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5503 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726605AbfF1CNi (ORCPT ); Thu, 27 Jun 2019 22:13:38 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:37 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:34 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:34 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:34 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:34 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:34 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 09/18] clk: tegra: Add save and restore context support for peripheral clocks Date: Thu, 27 Jun 2019 19:12:43 -0700 Message-ID: <1561687972-19319-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688017; bh=GlWc+jkwLE8zt750HT4URregRkYMrhHEPmcOa/Wd3gE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=DBm1DHbW5GE9bf0B5LFMOX5WVk3+LiPbm5V4veXV73H8rCB8yeluTZ4BiFcOZmFhE 6TYO7KuvXpp8F1tsJpgN73Qmz5UV3hEjpTraNqyhiB+rzGJnYfaCQpcSeDW96tsuV8 Mi0rQGxyEz/eNaY/o85srbMBHCf8B6+8RiYKcT4g7ElBN7zQjUSSKGnnoSkH2pHeDe rD7A5o1tNUpe5seV1EuLfvrOe94TDEADdFpZkaT6tWE46WXZ3ylum/GyiBDlUJUah+ OVh0wrGM55iMSNg9eM9fWeO0Yd/INYr55G8V3ZcDl3o8OM3gh6G3PqUTcIyeQBU92X yQyszd2O5VyPA== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch implements save and restore context for peripheral fixed clock ops, peripheral gate clock ops, sdmmc mux clock ops, and peripheral clock ops. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry clock and reset state of peripherals is saved and on resume they are restored to have clocks back to same rate and state as before suspend. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-periph-fixed.c | 31 ++++++++++++++++++++++++++ drivers/clk/tegra/clk-periph-gate.c | 34 ++++++++++++++++++++++++++++ drivers/clk/tegra/clk-periph.c | 43 ++++++++++++++++++++++++++++++++++++ drivers/clk/tegra/clk-sdmmc-mux.c | 30 +++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 8 +++++++ 5 files changed, 146 insertions(+) diff --git a/drivers/clk/tegra/clk-periph-fixed.c b/drivers/clk/tegra/clk-periph-fixed.c index c088e7a280df..981f68b0a937 100644 --- a/drivers/clk/tegra/clk-periph-fixed.c +++ b/drivers/clk/tegra/clk-periph-fixed.c @@ -60,11 +60,42 @@ tegra_clk_periph_fixed_recalc_rate(struct clk_hw *hw, return (unsigned long)rate; } +static int tegra_clk_periph_fixed_save_context(struct clk_hw *hw) +{ + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); + u32 mask = 1 << (fixed->num % 32); + + fixed->enb_ctx = readl(fixed->base + fixed->regs->enb_reg) & mask; + fixed->rst_ctx = readl(fixed->base + fixed->regs->rst_reg) & mask; + + return 0; +} + +static void tegra_clk_periph_fixed_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); + u32 mask = 1 << (fixed->num % 32); + + if (fixed->enb_ctx) + tegra_clk_periph_fixed_enable(hw); + else + tegra_clk_periph_fixed_disable(hw); + + udelay(2); + + if (!fixed->rst_ctx) { + udelay(5); /* reset propogation delay */ + writel(mask, fixed->base + fixed->regs->rst_reg); + } +} + static const struct clk_ops tegra_clk_periph_fixed_ops = { .is_enabled = tegra_clk_periph_fixed_is_enabled, .enable = tegra_clk_periph_fixed_enable, .disable = tegra_clk_periph_fixed_disable, .recalc_rate = tegra_clk_periph_fixed_recalc_rate, + .save_context = tegra_clk_periph_fixed_save_context, + .restore_context = tegra_clk_periph_fixed_restore_context, }; struct clk *tegra_clk_register_periph_fixed(const char *name, diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 4b31beefc9fc..6ba5b08e0787 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -25,6 +25,8 @@ static DEFINE_SPINLOCK(periph_ref_lock); #define read_rst(gate) \ readl_relaxed(gate->clk_base + (gate->regs->rst_reg)) +#define write_rst_set(val, gate) \ + writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg)) #define write_rst_clr(val, gate) \ writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg)) @@ -110,10 +112,42 @@ static void clk_periph_disable(struct clk_hw *hw) spin_unlock_irqrestore(&periph_ref_lock, flags); } +static int clk_periph_gate_save_context(struct clk_hw *hw) +{ + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); + + gate->clk_state_ctx = read_enb(gate) & periph_clk_to_bit(gate); + gate->rst_state_ctx = read_rst(gate) & periph_clk_to_bit(gate); + + return 0; +} + +static void clk_periph_gate_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); + + if (gate->clk_state_ctx) + write_enb_set(periph_clk_to_bit(gate), gate); + else + write_enb_clr(periph_clk_to_bit(gate), gate); + + udelay(5); + + if (!(gate->flags & TEGRA_PERIPH_NO_RESET) && + !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) { + if (gate->rst_state_ctx) + write_rst_set(periph_clk_to_bit(gate), gate); + else + write_rst_clr(periph_clk_to_bit(gate), gate); + } +} + const struct clk_ops tegra_clk_periph_gate_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .save_context = clk_periph_gate_save_context, + .restore_context = clk_periph_gate_restore_context, }; struct clk *tegra_clk_register_periph_gate(const char *name, diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 58437da25156..d07882656e66 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -99,6 +100,42 @@ static void clk_periph_disable(struct clk_hw *hw) gate_ops->disable(gate_hw); } +static int clk_periph_save_context(struct clk_hw *hw) +{ + struct tegra_clk_periph *periph = to_clk_periph(hw); + const struct clk_ops *gate_ops = periph->gate_ops; + struct clk_hw *gate_hw = &periph->gate.hw; + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + if (!(periph->gate.flags & TEGRA_PERIPH_NO_GATE)) + gate_ops->save_context(gate_hw); + + if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV)) + periph->rate_ctx = clk_periph_recalc_rate(hw, parent_rate); + + periph->parent_ctx = clk_periph_get_parent(hw); + + return 0; +} + +static void clk_periph_restore_context(struct clk_hw *hw) +{ + struct tegra_clk_periph *periph = to_clk_periph(hw); + const struct clk_ops *gate_ops = periph->gate_ops; + struct clk_hw *gate_hw = &periph->gate.hw; + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + if (!(periph->gate.flags & TEGRA_PERIPH_NO_GATE)) + gate_ops->restore_context(gate_hw); + + clk_periph_set_parent(hw, periph->parent_ctx); + + if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV)) + clk_periph_set_rate(hw, periph->rate_ctx, parent_rate); +} + const struct clk_ops tegra_clk_periph_ops = { .get_parent = clk_periph_get_parent, .set_parent = clk_periph_set_parent, @@ -108,6 +145,8 @@ const struct clk_ops tegra_clk_periph_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .save_context = clk_periph_save_context, + .restore_context = clk_periph_restore_context, }; static const struct clk_ops tegra_clk_periph_nodiv_ops = { @@ -116,6 +155,8 @@ static const struct clk_ops tegra_clk_periph_nodiv_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .save_context = clk_periph_save_context, + .restore_context = clk_periph_restore_context, }; static const struct clk_ops tegra_clk_periph_no_gate_ops = { @@ -124,6 +165,8 @@ static const struct clk_ops tegra_clk_periph_no_gate_ops = { .recalc_rate = clk_periph_recalc_rate, .round_rate = clk_periph_round_rate, .set_rate = clk_periph_set_rate, + .save_context = clk_periph_save_context, + .restore_context = clk_periph_restore_context, }; static struct clk *_tegra_clk_register_periph(const char *name, diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmmc-mux.c index a5cd3e31dbae..fffe08e02c10 100644 --- a/drivers/clk/tegra/clk-sdmmc-mux.c +++ b/drivers/clk/tegra/clk-sdmmc-mux.c @@ -194,6 +194,34 @@ static void clk_sdmmc_mux_disable(struct clk_hw *hw) gate_ops->disable(gate_hw); } +static int clk_sdmmc_mux_save_context(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + sdmmc_mux->rate_ctx = clk_sdmmc_mux_recalc_rate(hw, parent_rate); + sdmmc_mux->parent_ctx = clk_sdmmc_mux_get_parent(hw); + gate_ops->save_context(gate_hw); + + return 0; +} + +static void clk_sdmmc_mux_restore_context(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + + clk_sdmmc_mux_set_parent(hw, sdmmc_mux->parent_ctx); + clk_sdmmc_mux_set_rate(hw, sdmmc_mux->rate_ctx, parent_rate); + gate_ops->restore_context(gate_hw); +} + static const struct clk_ops tegra_clk_sdmmc_mux_ops = { .get_parent = clk_sdmmc_mux_get_parent, .set_parent = clk_sdmmc_mux_set_parent, @@ -203,6 +231,8 @@ static const struct clk_ops tegra_clk_sdmmc_mux_ops = { .is_enabled = clk_sdmmc_mux_is_enabled, .enable = clk_sdmmc_mux_enable, .disable = clk_sdmmc_mux_disable, + .save_context = clk_sdmmc_mux_save_context, + .restore_context = clk_sdmmc_mux_restore_context, }; struct clk *tegra_clk_register_sdmmc_mux_div(const char *name, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index a687ed6127b6..13e16359ebbe 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -533,6 +533,8 @@ struct tegra_clk_periph_gate { int clk_num; int *enable_refcnt; const struct tegra_clk_periph_regs *regs; + bool clk_state_ctx; + bool rst_state_ctx; }; #define to_clk_periph_gate(_hw) \ @@ -559,6 +561,8 @@ struct tegra_clk_periph_fixed { unsigned int mul; unsigned int div; unsigned int num; + bool enb_ctx; + bool rst_ctx; }; struct clk *tegra_clk_register_periph_fixed(const char *name, @@ -591,6 +595,8 @@ struct tegra_clk_periph { const struct clk_ops *mux_ops; const struct clk_ops *div_ops; const struct clk_ops *gate_ops; + unsigned long rate_ctx; + u8 parent_ctx; }; #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) @@ -742,6 +748,8 @@ struct tegra_sdmmc_mux { const struct clk_ops *gate_ops; struct tegra_clk_periph_gate gate; u8 div_flags; + unsigned long rate_ctx; + u8 parent_ctx; }; #define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw) From patchwork Fri Jun 28 02:12:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123839 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="iLZFm7Ao"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgM111HFz9sNw for ; Fri, 28 Jun 2019 12:14:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726909AbfF1COW (ORCPT ); Thu, 27 Jun 2019 22:14:22 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5504 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726618AbfF1CNh (ORCPT ); Thu, 27 Jun 2019 22:13:37 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:38 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:35 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 27 Jun 2019 19:13:35 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:35 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:34 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:34 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:34 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 10/18] clk: tegra210: Use fence_udelay during PLLU init Date: Thu, 27 Jun 2019 19:12:44 -0700 Message-ID: <1561687972-19319-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688018; bh=xqhwILz/Sn/NsMkmMnHLFLG0V6+/ga/n+S6KiTKUBRg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=iLZFm7Ao1Xip/E2ikDPRaZsZ2dPVX6jG/cz1QwXtWJVqHrHkTZHrFOgG66+Ld7Z24 4jtOTJW85UpU2Obpr0auggd6zQyF56b4tOzeA5gWJFTy4iFRkTjddytypLDw/bq18F s377wHubIY1AOy3OkFFpvwpKnFj2LlshmVGULyZv1jVlcBqCqAsWiSYocwR1Wdw+L6 Te98furkDkYz9Yadd6uMIK62CtjxtZ2utmQSlaF6KEPkOH23lC93QIu0GKyVj2+KVG Hith+9hgBIXCttcY/XcRDuopHEwYxNjfgvVVm/+Ls1YsvV3aUVBV11qbsIaoP1fXCw YHDFVt02IZ3fA== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch uses fence_udelay rather than udelay during PLLU initialization to ensure writes to clock registers happens before waiting for specified delay. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 7f90442462af..1c08c53482a5 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2836,7 +2836,7 @@ static int tegra210_enable_pllu(void) reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); reg &= ~BIT(pllu.params->iddq_bit_idx); writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); - udelay(5); + fence_udelay(5, clk_base); reg = readl_relaxed(clk_base + PLLU_BASE); reg &= ~GENMASK(20, 0); @@ -2844,7 +2844,7 @@ static int tegra210_enable_pllu(void) reg |= fentry->n << 8; reg |= fentry->p << 16; writel(reg, clk_base + PLLU_BASE); - udelay(1); + fence_udelay(1, clk_base); reg |= PLL_ENABLE; writel(reg, clk_base + PLLU_BASE); @@ -2890,12 +2890,12 @@ static int tegra210_init_pllu(void) reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); - udelay(1); + fence_udelay(1, clk_base); reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); - udelay(1); + fence_udelay(1, clk_base); reg = readl_relaxed(clk_base + PLLU_BASE); reg &= ~PLLU_BASE_CLKENABLE_USB; From patchwork Fri Jun 28 02:12:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123817 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="N0C8Z2Ek"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgKv39NCz9s3Z for ; Fri, 28 Jun 2019 12:13:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726682AbfF1CNi (ORCPT ); Thu, 27 Jun 2019 22:13:38 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19591 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726648AbfF1CNh (ORCPT ); Thu, 27 Jun 2019 22:13:37 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:33 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:35 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 27 Jun 2019 19:13:35 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:35 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:34 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:35 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:34 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 11/18] clk: tegra210: Add support for Tegra210 clocks Date: Thu, 27 Jun 2019 19:12:45 -0700 Message-ID: <1561687972-19319-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688013; bh=Ufis+QDezP1XyERiO1WUwrZDgPC5sW2ihyZt4R1YFZY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=N0C8Z2EkCJKqQbzweaF/Qh9h42Y1P9R/4dIviSShLBwHdgwEZUvNVa8KRdsGO3D97 fn5h8s0QfcxTnLIqbWPQ4LPwthU3JkKpZd1Ak5yMEj6J+iYdY8CQXQPkW7TTSvCalC /Eykh4rGBQpqafWGSIYKQZrRPQd9v2sFqtr8FVbb3F7uzP8bobQgmHuG51YnNUMpIQ tVTa6F7BtThwaz2nGeQnsJF8S26ffUdgaDpRCbLZjl0P4Jg4ngtPQawQLBlp11jEGg FkKzpYlvQpKXFtcQNPVYLU3zHuXOZIjYs9fRDYvdyaxAU7ZYmme9Rn93Tu5lZMUOTJ lGQAKpEnjnNWQ== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds system suspend and resume support for Tegra210 clocks. All the CAR controller settings are lost on suspend when core power goes off. This patch has implementation for saving and restoring all the PLLs and clocks context during system suspend and resume to have the clocks back to same state for normal operation. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 115 ++++++++++++++++++++++++++++++++++++++- drivers/clk/tegra/clk.c | 14 +++++ drivers/clk/tegra/clk.h | 1 + 3 files changed, 127 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 1c08c53482a5..1b839544e086 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -9,10 +9,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -20,6 +22,7 @@ #include #include "clk.h" +#include "clk-dfll.h" #include "clk-id.h" /* @@ -225,6 +228,7 @@ #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac +#define CPU_SOFTRST_CTRL 0x380 #define LVL2_CLK_GATE_OVRA 0xf8 #define LVL2_CLK_GATE_OVRC 0x3a0 @@ -2820,6 +2824,7 @@ static int tegra210_enable_pllu(void) struct tegra_clk_pll_freq_table *fentry; struct tegra_clk_pll pllu; u32 reg; + int ret; for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) { if (fentry->input_rate == pll_ref_freq) @@ -2847,10 +2852,10 @@ static int tegra210_enable_pllu(void) fence_udelay(1, clk_base); reg |= PLL_ENABLE; writel(reg, clk_base + PLLU_BASE); + fence_udelay(1, clk_base); - readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg, - reg & PLL_BASE_LOCK, 2, 1000); - if (!(reg & PLL_BASE_LOCK)) { + ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK); + if (ret) { pr_err("Timed out waiting for PLL_U to lock\n"); return -ETIMEDOUT; } @@ -3283,6 +3288,103 @@ static void tegra210_disable_cpu_clock(u32 cpu) } #ifdef CONFIG_PM_SLEEP +static u32 cpu_softrst_ctx[3]; +static struct platform_device *dfll_pdev; +#define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4)) +#define car_writel(_val, _base, _off) \ + writel_relaxed(_val, clk_base + (_base) + ((_off) * 4)) + +static int tegra210_clk_suspend(void) +{ + unsigned int i; + struct device_node *node; + + tegra_cclkg_burst_policy_save_context(); + + if (!dfll_pdev) { + node = of_find_compatible_node(NULL, NULL, + "nvidia,tegra210-dfll"); + if (node) + dfll_pdev = of_find_device_by_node(node); + + of_node_put(node); + if (!dfll_pdev) + pr_err("dfll node not found. no suspend for dfll\n"); + } + + if (dfll_pdev) + tegra_dfll_suspend(dfll_pdev); + + /* Enable PLLP_OUT_CPU after dfll suspend */ + tegra_clk_set_pllp_out_cpu(true); + + tegra_sclk_cclklp_burst_policy_save_context(); + + clk_save_context(); + + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++) + cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i); + + return 0; +} + +static void tegra210_clk_resume(void) +{ + unsigned int i; + struct clk_hw *parent; + struct clk *clk; + + /* + * clk_restore_context restores clocks as per the clock tree. + * + * dfllCPU_out is first in the clock tree to get restored and it + * involves programming DFLL controller along with restoring CPUG + * clock burst policy. + * + * DFLL programming needs dfll_ref and dfll_soc peripheral clocks + * to be restores which are part ofthe peripheral clocks. + * So, peripheral clocks restore should happen prior to dfll clock + * restore. + */ + + tegra_clk_osc_resume(clk_base); + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++) + car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i); + + /* restore all plls and peripheral clocks */ + tegra210_init_pllu(); + clk_restore_context(); + + fence_udelay(5, clk_base); + + /* resume SCLK and CPULP clocks */ + tegra_sclk_cpulp_burst_policy_restore_context(); + + /* + * restore CPUG clocks: + * - enable DFLL in open loop mode + * - switch CPUG to DFLL clock source + * - close DFLL loop + * - sync PLLX state + */ + if (dfll_pdev) + tegra_dfll_resume(dfll_pdev, false); + + tegra_cclkg_burst_policy_restore_context(); + fence_udelay(2, clk_base); + + if (dfll_pdev) + tegra_dfll_resume(dfll_pdev, true); + + parent = clk_hw_get_parent(__clk_get_hw(clks[TEGRA210_CLK_CCLK_G])); + clk = clks[TEGRA210_CLK_PLL_X]; + if (parent != __clk_get_hw(clk)) + tegra_clk_sync_state_pll(__clk_get_hw(clk)); + + /* Disable PLL_OUT_CPU after DFLL resume */ + tegra_clk_set_pllp_out_cpu(false); +} + static void tegra210_cpu_clock_suspend(void) { /* switch coresite to clk_m, save off original source */ @@ -3298,6 +3400,11 @@ static void tegra210_cpu_clock_resume(void) } #endif +static struct syscore_ops tegra_clk_syscore_ops = { + .suspend = tegra210_clk_suspend, + .resume = tegra210_clk_resume, +}; + static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { .wait_for_reset = tegra210_wait_cpu_in_reset, .disable_clock = tegra210_disable_cpu_clock, @@ -3583,5 +3690,7 @@ static void __init tegra210_clock_init(struct device_node *np) tegra210_mbist_clk_init(); tegra_cpu_car_ops = &tegra210_cpu_car_ops; + + register_syscore_ops(&tegra_clk_syscore_ops); } CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 9e863362d2bf..96cc9937ea37 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -23,6 +23,7 @@ #define CLK_OUT_ENB_W 0x364 #define CLK_OUT_ENB_X 0x280 #define CLK_OUT_ENB_Y 0x298 +#define CLK_ENB_PLLP_OUT_CPU BIT(31) #define CLK_OUT_ENB_SET_L 0x320 #define CLK_OUT_ENB_CLR_L 0x324 #define CLK_OUT_ENB_SET_H 0x328 @@ -205,6 +206,19 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid) } } +void tegra_clk_set_pllp_out_cpu(bool enable) +{ + u32 val; + + val = readl_relaxed(clk_base + CLK_OUT_ENB_Y); + if (enable) + val |= CLK_ENB_PLLP_OUT_CPU; + else + val &= ~CLK_ENB_PLLP_OUT_CPU; + + writel_relaxed(val, clk_base + CLK_OUT_ENB_Y); +} + void tegra_cclkg_burst_policy_save_context(void) { unsigned int i; diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 13e16359ebbe..a0fbebc1d913 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -872,6 +872,7 @@ void tegra_cclkg_burst_policy_restore_context(void); void tegra_sclk_cclklp_burst_policy_save_context(void); void tegra_sclk_cpulp_burst_policy_restore_context(void); void tegra_clk_osc_resume(void __iomem *clk_base); +void tegra_clk_set_pllp_out_cpu(bool enable); /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ From patchwork Fri Jun 28 02:12:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123834 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="EWysqwD2"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgLp3HTXz9sN6 for ; Fri, 28 Jun 2019 12:14:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726671AbfF1CNi (ORCPT ); Thu, 27 Jun 2019 22:13:38 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:17629 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726646AbfF1CNh (ORCPT ); Thu, 27 Jun 2019 22:13:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:35 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:35 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:35 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:35 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:35 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:35 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:35 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 12/18] soc/tegra: pmc: Allow support for more tegra wake Date: Thu, 27 Jun 2019 19:12:46 -0700 Message-ID: <1561687972-19319-13-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688015; bh=2GvhhOatfsM2bYQzuVGHbcx4hR8oEy2cTWpoIl1r38Y=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=EWysqwD20Hw+TrWjze8+lirhX1q7Wr0zQjD/3DWWlzX5VZ1ARs/TL0SiGs9y/NKGe nWZV5w66pjgJul5UW8mHwnzx7ogsrRC9dekpauXW83IBOOzZnSGD/yxu2de1Y9KjOg ksX9FMK3G6/E3hSFVK5GSuMMEioqRQnIO0yGtyri1S+unh4VWsskQsdSEYUXOlO1+u sDOXrHFHIs/aYFS7OiBSao7cj04xl6p45bp3B1zG8eQPpl86lOUPRlDkhvnHauTqfp 13Vv4v3lNeY5lupg825EdDmiPmzHqvYhmZNZKnQeUZK6zp3frITTskmmhDw7CJ2Wo0 a2rkHrsAJdFqw== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch allows to create separate irq_set_wake and irq_set_type implementations for different tegra designs PMC that has different wake models which require difference wake registers and different programming sequence. AOWAKE model support is available for Tegra186 and Tegra194 only and it resides within PMC and supports tiered wake architecture. Tegra210 and prior tegra designs uses PMC directly to receive wake events and coordinate the wake sequence. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 9f9c1c677cf4..91c84d0e66ae 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -226,6 +226,8 @@ struct tegra_pmc_soc { void (*setup_irq_polarity)(struct tegra_pmc *pmc, struct device_node *np, bool invert); + int (*irq_set_wake)(struct irq_data *data, unsigned int on); + int (*irq_set_type)(struct irq_data *data, unsigned int type); const char * const *reset_sources; unsigned int num_reset_sources; @@ -1920,7 +1922,7 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; -static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); unsigned int offset, bit; @@ -1952,7 +1954,7 @@ static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } -static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type) +static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); u32 value; @@ -2006,8 +2008,8 @@ static int tegra_pmc_irq_init(struct tegra_pmc *pmc) pmc->irq.irq_unmask = irq_chip_unmask_parent; pmc->irq.irq_eoi = irq_chip_eoi_parent; pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent; - pmc->irq.irq_set_type = tegra_pmc_irq_set_type; - pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake; + pmc->irq.irq_set_type = pmc->soc->irq_set_type; + pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, &tegra_pmc_irq_domain_ops, pmc); @@ -2680,6 +2682,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .regs = &tegra186_pmc_regs, .init = NULL, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, + .irq_set_wake = tegra186_pmc_irq_set_wake, + .irq_set_type = tegra186_pmc_irq_set_type, .reset_sources = tegra186_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), .reset_levels = tegra186_reset_levels, From patchwork Fri Jun 28 02:12:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123830 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="cp01WqXh"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgLf3Bmnz9sNd for ; Fri, 28 Jun 2019 12:14:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726869AbfF1COH (ORCPT ); Thu, 27 Jun 2019 22:14:07 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:17635 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725770AbfF1CNi (ORCPT ); Thu, 27 Jun 2019 22:13:38 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:35 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:35 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:35 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:35 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:35 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:35 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 13/18] soc/tegra: pmc: Add pmc wake support for tegra210 Date: Thu, 27 Jun 2019 19:12:47 -0700 Message-ID: <1561687972-19319-14-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688015; bh=eFC+lQbv0+s8fpS/9uOfXjpuEt4wMc1u15Tgc3FtoRw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=cp01WqXh5eIflVOZ4IXaL5bNbslMuNC560qucr8MNkX1jqM423iv4btQQ8KJdztB5 u/V3kOqXF9YU06zgDmPvTxe02hwbN7takXxKs+PayynBsKSslakx/JbKJQbhih3oLk cinWlkJmiRsVRSva76kiLGiRPPX6PpFyjCGUvLzc3Jte1yZNkAb9+am6va6+HAaIak f8135gBS3olUTgIErtatfi+advD+Vi3S0ZTYXn2eP4veLBTwBHE34Ip/cCwpMM0JTs qIi5lxHFD6dj5Tzb9w10dnPsQpMNN8kZEoKfLVr/7QpX0P2F/0v5XFUWznJZIFy3MW UC+b5h2TyTPAQ== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch implements PMC wakeup sequence for Tegra210 and defines common used RTC alarm wake event. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 91c84d0e66ae..194100d77243 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -57,6 +57,12 @@ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ #define PMC_CNTRL_MAIN_RST BIT(4) +#define PMC_CNTRL_LATCH_WAKEUPS BIT(5) + +#define PMC_WAKE_MASK 0x0c +#define PMC_WAKE_LEVEL 0x10 +#define PMC_WAKE_STATUS 0x14 +#define PMC_SW_WAKE_STATUS 0x18 #define DPD_SAMPLE 0x020 #define DPD_SAMPLE_ENABLE BIT(0) @@ -87,6 +93,11 @@ #define PMC_SCRATCH41 0x140 +#define PMC_WAKE2_MASK 0x160 +#define PMC_WAKE2_LEVEL 0x164 +#define PMC_WAKE2_STATUS 0x168 +#define PMC_SW_WAKE2_STATUS 0x16c + #define PMC_SENSOR_CTRL 0x1b0 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) @@ -1922,6 +1933,55 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; +static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + /* + * latch wakeups to SW_WAKE_STATUS register to capture events + * that would not make it into wakeup event register during LP0 exit. + */ + value = tegra_pmc_readl(pmc, PMC_CNTRL); + value |= PMC_CNTRL_LATCH_WAKEUPS; + tegra_pmc_writel(pmc, value, PMC_CNTRL); + udelay(120); + + value &= ~PMC_CNTRL_LATCH_WAKEUPS; + tegra_pmc_writel(pmc, value, PMC_CNTRL); + udelay(120); + + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); + + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); + + /* enable PMC wake */ + if (data->hwirq >= 32) + offset = PMC_WAKE2_MASK; + else + offset = PMC_WAKE_MASK; + + value = tegra_pmc_readl(pmc, offset); + + if (on) + value |= 1 << bit; + else + value &= ~(1 << bit); + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -1954,6 +2014,49 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); + unsigned int offset, bit; + u32 value; + + if (data->hwirq == ULONG_MAX) + return 0; + + offset = data->hwirq / 32; + bit = data->hwirq % 32; + + if (data->hwirq >= 32) + offset = PMC_WAKE2_LEVEL; + else + offset = PMC_WAKE_LEVEL; + + value = tegra_pmc_readl(pmc, offset); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_LEVEL_HIGH: + value |= 1 << bit; + break; + + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_LEVEL_LOW: + value &= ~(1 << bit); + break; + + case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: + value ^= 1 << bit; + break; + + default: + return -EINVAL; + } + + tegra_pmc_writel(pmc, value, offset); + + return 0; +} + static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -2540,6 +2643,10 @@ static const struct pinctrl_pin_desc tegra210_pin_descs[] = { TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) }; +static const struct tegra_wake_event tegra210_wake_events[] = { + TEGRA_WAKE_IRQ("rtc", 16, 2), +}; + static const struct tegra_pmc_soc tegra210_pmc_soc = { .num_powergates = ARRAY_SIZE(tegra210_powergates), .powergates = tegra210_powergates, @@ -2557,10 +2664,14 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .regs = &tegra20_pmc_regs, .init = tegra20_pmc_init, .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, + .irq_set_wake = tegra210_pmc_irq_set_wake, + .irq_set_type = tegra210_pmc_irq_set_type, .reset_sources = tegra210_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), .reset_levels = NULL, .num_reset_levels = 0, + .num_wake_events = ARRAY_SIZE(tegra210_wake_events), + .wake_events = tegra210_wake_events, }; #define TEGRA186_IO_PAD_TABLE(_pad) \ From patchwork Fri Jun 28 02:12:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123840 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="kcHrPswf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgM161lhz9s3Z for ; Fri, 28 Jun 2019 12:14:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726695AbfF1COV (ORCPT ); Thu, 27 Jun 2019 22:14:21 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19590 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726647AbfF1CNh (ORCPT ); Thu, 27 Jun 2019 22:13:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:34 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:36 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:36 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:35 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:35 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:35 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 14/18] arm64: tegra: Enable wake from deep sleep on RTC alarm. Date: Thu, 27 Jun 2019 19:12:48 -0700 Message-ID: <1561687972-19319-15-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688014; bh=r/7sch8XJz5tT01ckyUKnesfNR9nppNjP97KIR+puRI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=kcHrPswfiZz65Baz23jNP4sHHpiUaPgRgJ8DI/q/I0KpmKTjwbcbmJGzuWgXjyNoL n0AGEN1kG0M6kbe4bu4Y41QiUAk24ggOJAzPJDPL4j9odJjjMm9k3jQwJUE04KJbB6 KyZPOWShOK0FKgmp6HWmwuyqqNn1UM1Vm1ThLegSoQ+rIxWz+AoT8h4E4+UBUwWv1S nB2H+e4sp4+XN11soY6nTgrJ3zk/sDq/6cAfJL+MxEiJgC4nqxXbaaDB/J6OJTUvju Wr+yY2b7IAwrXNskQHihymPuXEnkZdkjMw+JIfK9kPFxzbtLSMbUgmqv5iI2GH0nuz b4f2Qt77KsycA== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch updates device tree for RTC and PMC to allow system wake from deep sleep on RTC alarm. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 659753118e96..30a7c48385a2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -768,7 +768,8 @@ rtc@7000e000 { compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = ; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pmc>; clocks = <&tegra_car TEGRA210_CLK_RTC>; clock-names = "rtc"; }; @@ -778,6 +779,8 @@ reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #interrupt-cells = <2>; + interrupt-controller; powergates { pd_audio: aud { From patchwork Fri Jun 28 02:12:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123833 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="b+Nz4Qhu"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgLk3Tk9z9sPH for ; Fri, 28 Jun 2019 12:14:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726682AbfF1COG (ORCPT ); Thu, 27 Jun 2019 22:14:06 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:17636 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726657AbfF1CNi (ORCPT ); Thu, 27 Jun 2019 22:13:38 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:35 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:36 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 27 Jun 2019 19:13:36 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:35 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:35 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:35 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 15/18] soc/tegra: pmc: Configure core power request polarity Date: Thu, 27 Jun 2019 19:12:49 -0700 Message-ID: <1561687972-19319-16-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688015; bh=ERKuxl3VXTCSt7ZlOTdJl+Ti8kkBSY5vvhGXUlExL9k=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=b+Nz4QhuQfKLjQwtpiYRZWIrNdsgN2oCg/p16Y4NbBHhONFZAhUu+6OyyXIdjXza3 zYrXVr2TU0enjfReEok1xsRyisdZ6pzhNQypP+yUVqJJAY+sS33y+Tuu1UNUuZt4qe ldS+nXLouvRbvxKKdZSLhKSB3Hg0RJ/vsN388BT1b3BY3SuZojLWM6PRFo9d9xP2wy jprVaoo1cDMog7nBGtrnz/huM19gDtfF7NCAvilkkUxeD3itB0Azx+yaqFAr1qX4OQ IIX6SVqrc0MVJPWfG5xeRRq1wP1LwTrVDNF38PF2MLkE/74ymDmwIg8CZXajjAPa5m fINxzSVbQiKnQ== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch configures polarity of the core power request signal in PMC control register based on the device tree property. PMC asserts and de-asserts power request signal based on it polarity when it need to power-up and power-down the core rail during SC7. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 194100d77243..ed83c0cd09a3 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -56,6 +56,7 @@ #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ +#define PMC_CNTRL_PWRREQ_POLARITY BIT(8) #define PMC_CNTRL_MAIN_RST BIT(4) #define PMC_CNTRL_LATCH_WAKEUPS BIT(5) @@ -2303,6 +2304,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) else value |= PMC_CNTRL_SYSCLK_POLARITY; + if (pmc->corereq_high) + value &= ~PMC_CNTRL_PWRREQ_POLARITY; + else + value |= PMC_CNTRL_PWRREQ_POLARITY; + /* configure the output polarity while the request is tristated */ tegra_pmc_writel(pmc, value, PMC_CNTRL); From patchwork Fri Jun 28 02:12:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123826 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="rbiOVfdp"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgLR69Grz9sND for ; Fri, 28 Jun 2019 12:14:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726664AbfF1CN5 (ORCPT ); Thu, 27 Jun 2019 22:13:57 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5511 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726659AbfF1CNi (ORCPT ); Thu, 27 Jun 2019 22:13:38 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:39 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:36 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:36 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:36 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:36 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:36 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 16/18] soc/tegra: pmc: Configure deep sleep control settings Date: Thu, 27 Jun 2019 19:12:50 -0700 Message-ID: <1561687972-19319-17-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688019; bh=yMF0oM3+uebVoba25pi7TTeIEke1092zLym6YFQg1MQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rbiOVfdp9R58xH6NOj1wyxEfUXrvoVQ4oE+jg12coxJfKKYW7y4QI1YtDtA26wD4j qQaaK/Cwx+YNLTCrd4NqzNXNPi0sk5mw63k9GVlBfbLBkvi4TIhW9h2ISuraD+UUxV bj5ZuRoHsqaW1SBSru1aR1k+TGuzeCdRDF14JbhKiinI8XgbUCvhX7RC3kFzE16u5l qPPxqB9B/dHcQyyG1Uj16Nibe77Ub54bOGAMo/IM4SkXH6NhQ+sbPu94b/JWpeaz6Y Sy+M6V8aIH4u1MZw20+fHSdq+VQG6fO6Z6xnoL395IP4oHNzIe1MDbO8/SEk2IZgWQ qsSpkg16ceA1A== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Tegra210 and prior Tegra chips have deep sleep entry and wakeup related timings which are platform specific that should be configured before entering into deep sleep. Below are the timing specific configurations for deep sleep entry and wakeup. - Core rail power-on stabilization timer - OSC clock stabilization timer after SOC rail power is stabilized. - Core power off time is the minimum wake delay to keep the system in deep sleep state irrespective of any quick wake event. These values depends on the discharge time of regulators and turn OFF time of the PMIC to allow the complete system to finish entering into deep sleep state. These values vary based on the platform design and are specified through the device tree. This patch has implementation to configure these timings which are must to have for proper deep sleep and wakeup operations. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index ed83c0cd09a3..7e4a8f04f4c4 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -89,6 +89,8 @@ #define PMC_CPUPWRGOOD_TIMER 0xc8 #define PMC_CPUPWROFF_TIMER 0xcc +#define PMC_COREPWRGOOD_TIMER 0x3c +#define PMC_COREPWROFF_TIMER 0xe0 #define PMC_PWR_DET_VALUE 0xe4 @@ -2291,6 +2293,7 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = { static void tegra20_pmc_init(struct tegra_pmc *pmc) { u32 value; + unsigned long osc, pmu, off; /* Always enable CPU power request */ value = tegra_pmc_readl(pmc, PMC_CNTRL); @@ -2316,6 +2319,15 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) value = tegra_pmc_readl(pmc, PMC_CNTRL); value |= PMC_CNTRL_SYSCLK_OE; tegra_pmc_writel(pmc, value, PMC_CNTRL); + + osc = DIV_ROUND_UP_ULL(pmc->core_osc_time * 8192, 1000000); + pmu = DIV_ROUND_UP_ULL(pmc->core_pmu_time * 32768, 1000000); + off = DIV_ROUND_UP_ULL(pmc->core_off_time * 32768, 1000000); + if (osc && pmu) + tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), + PMC_COREPWRGOOD_TIMER); + if (off) + tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); } static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, From patchwork Fri Jun 28 02:12:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="HsxdyK2C"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgLG5Ys0z9s9h for ; Fri, 28 Jun 2019 12:13:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726813AbfF1CN5 (ORCPT ); Thu, 27 Jun 2019 22:13:57 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19599 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726660AbfF1CNi (ORCPT ); Thu, 27 Jun 2019 22:13:38 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:34 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:36 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:36 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:36 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:36 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:36 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 17/18] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Date: Thu, 27 Jun 2019 19:12:51 -0700 Message-ID: <1561687972-19319-18-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688014; bh=3ikE8x0cNN1fPtdTTddMKObVTKhfyEJPwIrj8ksa4Wg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=HsxdyK2CjO+XsApdFXFQYrIsjiU5FG7w/iV3ZSBBvE+87Juwe8pMxWKZbAu6ViDKA cHC1Ezn5QmxwZH6RUf7AS7RGLIJBFE+oguHABUM0xh11MKBk+q5qZJT4DY5IXZWWRD MLB87R48tlMHuboCDtVskIqmOO/tyYMEafy0Gow2IVRj38R1dTL0cXBOXbZJDjR7Ur uJtpD2k4Bw7TldkVnaf/4WX9lENTvhh1A0f9C3kNOEEiYD5NdCsSgOcdZViwPvf6Rs ssZK/6DXQAbfYN1UCF0jsZY5W5s14T/GBgL3DYvjLdzNQAOmUEm7qwyCrpKdFzWbQB +fjghbc+PoMcg== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch has Jetson TX1 platform specific SC7 timing configuration in device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 27723829d033..cb58f79deb48 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -279,6 +279,13 @@ pmc@7000e400 { nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; /* eMMC */ From patchwork Fri Jun 28 02:12:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1123821 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="lV07bS1n"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45ZgLF3yVcz9sNC for ; Fri, 28 Jun 2019 12:13:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726694AbfF1CNv (ORCPT ); Thu, 27 Jun 2019 22:13:51 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:17643 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbfF1CNj (ORCPT ); Thu, 27 Jun 2019 22:13:39 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 27 Jun 2019 19:13:36 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 27 Jun 2019 19:13:37 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 27 Jun 2019 19:13:37 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:37 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 28 Jun 2019 02:13:36 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 28 Jun 2019 02:13:36 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.155]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 27 Jun 2019 19:13:36 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V5 18/18] arm64: dts: tegra210-p3450: Jetson nano SC7 timings Date: Thu, 27 Jun 2019 19:12:52 -0700 Message-ID: <1561687972-19319-19-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> References: <1561687972-19319-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561688016; bh=nUcVR3aZhc7CmOqQ/Gf0Or0b77WEAikV513SetsAm3o=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=lV07bS1nw6Nyav+vjPMiy5zgQnmLOJyQ8iBL05bLAZxsqvAkPZm4pvjAu9G3/loHd v39prKHsdCGeOTbBQBfiJfJHfX15MR373/8gVHDi07luwpwEfwNaNr9JghYaDUPvlt eVhlsRK458IhZT6LIHRPHvUwNSbMx9xMFZb4TpPL/wL7v3rywlSQryJSAXW709u/Kz 8BN+icPwB73mJ/xSlwBc2chhvx2TzTETtNH53BS+cF/jMkJ8pOITVCHZvMgw0PhgEy 2rm6GIKIt7dCO/bj1VSmsxiCoOxXmuevPT23KfqCJOLwQAPfT7a7rLlkWD3SPYQpw+ 7KQcNQ0s5s0lA== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds Jetson nano platform specific SC7 timing configuration in the device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9d17ec707bce..b81bfdfbc115 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -382,6 +382,13 @@ pmc@7000e400 { nvidia,invert-interrupt; ++ nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; hda@70030000 {