From patchwork Thu Jun 27 15:19:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123437 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZNzT54rkz9s3l for ; Fri, 28 Jun 2019 01:26:45 +1000 (AEST) Received: from localhost ([::1]:51692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWIN-0001B0-9L for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:26:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60531) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWFG-000173-B9 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:23:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWFD-0006VB-Ar for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:23:29 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:41815) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWFB-0006Rd-0t for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:23:25 -0400 Received: by mail-pg1-f195.google.com with SMTP id c70so1046729pga.8 for ; Thu, 27 Jun 2019 08:23:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:mime-version :content-transfer-encoding:cc:from:to; bh=Pw2Nr3I+/5EVRnOzDOc9YXIEf5FJ+JDG7yoiQZALAIQ=; b=SlqdiMjPq6FW3a0T+c6l5YQeIOJMS10k1WjcQUSbldRkQygZIdtLvXBEmr5TOCdR9l 3cgcMQ4NYqj5SQ0Ep9UvNyfuahTbngrfdUs9qS4RTKR2RTcJHoGw2Ju9YzZTeeRNCG9H i2+u5teuK6jjX4iHIKOP1VAwSnqq+i98AJWCi2EZiE+29rNaFWnlexJ5ooZyErmvhSz6 q0SHAIhZQ1RvMkiu3zDt0k51e0uXQNIuYvFt6Smk3DFpzyRIPg5C0WaauwD698NtStXP OTxDaWzfBSDUPrgTAgPe28FeKhgvelYMOpUCEDYfZDaiSCJZee3TdYiZerlZv+7dqS7m srQg== X-Gm-Message-State: APjAAAVosBnjU+DYMLsWZDC208eBvtHkHBLGqemUDZm86aFtTT2ZabO7 P+4DBfsHBRsu0rB9bImsrnZf9A== X-Google-Smtp-Source: APXvYqzQfZZ4dwHMuhEdtSvhWi4F6pS6UG9Unovot9YhQRtlnZZ+GkFKKbc5iPOGImaLYhL/NWxrqQ== X-Received: by 2002:a17:90a:ac0e:: with SMTP id o14mr6784262pjq.142.1561649001369; Thu, 27 Jun 2019 08:23:21 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id f15sm7644455pje.17.2019.06.27.08.23.20 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:20 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:37 -0700 Message-Id: <20190627152011.18686-1-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.195 Subject: [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" merged tag 'mips-queue-jun-21-2019' The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 15:40:50 +0100) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1 for you to fetch changes up to c08a8317e31033ec76b8460a0b75cbcdaeeef481: hw/riscv: Load OpenSBI as the default firmware (2019-06-27 02:47:06 -0700) ---------------------------------------------------------------- RISC-V Patches for the 4.1 Soft Freeze, Part 2 This pull request contains a handful of patches that I'd like to target for the 4.1 soft freeze. There are a handful of new features: * The -bios option now works sanely, including both a built-in copy of OpenSBI and the ability to load external versions. Users no longer need to figure out how to build their own firmware. * Support for the 1.11.0, the latest privileged specification. * Support for reading and writing the PRCI registers. * Better control over the ISA of the target machine. * Support for the cpu-topology device tree node. Additionally, there are a handful of bug fixes including: * Load reservations are now broken by both store conditional and by scheduling, which fixes issues with parallel applications. * Various fixes to the PMP implementation. * Fixes to the 32-bit linux-user syscall ABI. * Various fixes for instruction decodeing. * A fix to the PCI device tree "bus-range" property. This boots 32-bit and 64-bit OpenEmbedded. ---------------------------------------------------------------- Alistair Francis (14): target/riscv: Allow setting ISA extensions via CPU props target/riscv: Restructure deprecatd CPUs target/riscv: Add the privledge spec version 1.11.0 target/riscv: Add the mcountinhibit CSR target/riscv: Set privledge spec 1.11.0 as default qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 target/riscv: Require either I or E base extension target/riscv: Remove user version information target/riscv: Add support for disabling/enabling Counters hw/riscv: Split out the boot functions hw/riscv: Add support for loading a firmware hw/riscv: Extend the kernel loading support roms: Add OpenSBI version 0.3 hw/riscv: Load OpenSBI as the default firmware Atish Patra (1): riscv: virt: Add cpu-topology DT node. Bin Meng (3): riscv: virt: Correct pci "bus-range" encoding riscv: sifive_u: Do not create hard-coded phandles in DT riscv: sifive_u: Update the plic hart config to support multicore Dayeol Lee (1): target/riscv: Fix PMP range boundary address bug Hesham Almatary (6): RISC-V: Only Check PMP if MMU translation succeeds RISC-V: Raise access fault exceptions on PMP violations RISC-V: Check for the effective memory privilege mode during PMP checks RISC-V: Check PMP during Page Table Walks RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off RISC-V: Fix a PMP check with the correct access size Jim Wilson (1): RISC-V: Update syscall list for 32-bit support. Joel Sing (1): RISC-V: Clear load reservations on context switch and SC Michael Clark (2): target/riscv: Implement riscv_cpu_unassigned_access disas/riscv: Disassemble reserved compressed encodings as illegal Nathaniel Graff (1): sifive_prci: Read and write PRCI registers Palmer Dabbelt (3): RISC-V: Fix a memory leak when realizing a sifive_e RISC-V: Add support for the Zifencei extension RISC-V: Add support for the Zicsr extension Wladimir J. van der Laan (1): disas/riscv: Fix `rdinstreth` constraint .gitmodules | 3 + Makefile | 5 +- disas/riscv.c | 65 ++++++++--- hw/riscv/Makefile.objs | 1 + hw/riscv/boot.c | 154 +++++++++++++++++++++++++ hw/riscv/sifive_e.c | 30 ++--- hw/riscv/sifive_prci.c | 49 ++++++-- hw/riscv/sifive_u.c | 55 +++++---- hw/riscv/spike.c | 21 +--- hw/riscv/virt.c | 84 ++++++-------- include/hw/riscv/boot.h | 32 +++++ include/hw/riscv/sifive_e.h | 2 + include/hw/riscv/sifive_prci.h | 32 +++++ linux-user/riscv/syscall_nr.h | 15 ++- pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 0 -> 28848 bytes pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 0 -> 28904 bytes pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin 0 -> 28904 bytes qemu-deprecated.texi | 28 +++++ roms/Makefile | 48 ++++++-- roms/opensbi | 1 + target/riscv/cpu.c | 137 ++++++++++++++++------ target/riscv/cpu.h | 33 ++++-- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 55 ++++++++- target/riscv/csr.c | 30 ++++- target/riscv/insn_trans/trans_privileged.inc.c | 2 +- target/riscv/insn_trans/trans_rva.inc.c | 8 +- target/riscv/insn_trans/trans_rvi.inc.c | 4 + target/riscv/pmp.c | 17 +-- target/riscv/pmp.h | 2 +- target/riscv/translate.c | 3 + 31 files changed, 705 insertions(+), 212 deletions(-) create mode 100644 hw/riscv/boot.c create mode 100644 include/hw/riscv/boot.h create mode 100644 pc-bios/opensbi-riscv32-virt-fw_jump.bin create mode 100644 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin create mode 100644 pc-bios/opensbi-riscv64-virt-fw_jump.bin create mode 160000 roms/opensbi From patchwork Thu Jun 27 15:19:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123438 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZNzW5fgSz9s3l for ; Fri, 28 Jun 2019 01:26:47 +1000 (AEST) Received: from localhost ([::1]:51694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWIP-0001IY-QJ for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:26:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60589) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWFL-0001At-Rs for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:23:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWFI-0006Z3-6T for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:23:33 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:34117) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWFG-0006VY-Br for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:23:31 -0400 Received: by mail-pl1-f193.google.com with SMTP id i2so1492189plt.1 for ; Thu, 27 Jun 2019 08:23:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=skpCsY6OAelSjirFF1wZzpzLaY2+CMd8k4r3QNyFPh4=; b=Apmb5UiQjDjltCaVAw5i8hz+tZigr0zPBPpXh1+eoQPn5/6KxbfRCN+lo0AhxbaCVB BDn77OzKSp/n9VJUfMeEYf8Lgmstd0wG3aESj4En9zg668w7/4lMRQNraJp+s6QYUoUT 5kh1662dG3bTBlC8TlpMc4uxkoQ07X1wBlkERDTIX1GaZqJZRQHvFf2JwyYUtPl79srn rczhDDQ0DqVl/TD8r4jUfrTiQ4NP+cV/xyKvv8N1LSeu+7VTyTZ9shzSe6VwhzBDr6qF S9i65HJ26deyOqKGjDaKlFB8L0pY0Srf4C5Y3fScKm4vc9/xh7+ZfsOiRl1QburAmWl+ ynhw== X-Gm-Message-State: APjAAAUPKty/D3EBQWji71hPltxXIoeG6Z6+aTL95qPRstfcKlAIDxDm H/I1FwFXzeZAVRv7TvS6Od8ThQ== X-Google-Smtp-Source: APXvYqw5igcTkIulzG0XzC2nR1GXO//87ZtAwk+TL9KVkTl6rdxcSJHXY7oYPi23MOdiTkgbJFVHrg== X-Received: by 2002:a17:902:ac86:: with SMTP id h6mr5006282plr.98.1561649007217; Thu, 27 Jun 2019 08:23:27 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id f7sm2739438pgc.82.2019.06.27.08.23.26 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:26 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:39 -0700 Message-Id: <20190627152011.18686-3-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.193 Subject: [Qemu-devel] [PULL 02/34] sifive_prci: Read and write PRCI registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nathaniel Graff , Michael Clark , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Nathaniel Graff Writes to the SiFive PRCI registers are preserved while leaving the ready bits set for the HFX/HFR oscillators and the lock bit set for the PLL. Signed-off-by: Nathaniel Graff Reviewed-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_prci.c | 49 ++++++++++++++++++++++++++++------ include/hw/riscv/sifive_prci.h | 32 ++++++++++++++++++++++ 2 files changed, 73 insertions(+), 8 deletions(-) diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c index fa136b5a9fe9..f406682c91f1 100644 --- a/hw/riscv/sifive_prci.c +++ b/hw/riscv/sifive_prci.c @@ -24,15 +24,18 @@ #include "target/riscv/cpu.h" #include "hw/riscv/sifive_prci.h" -/* currently implements enough to mock freedom-e-sdk BSP clock programming */ - static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) { - if (addr == 0 /* PRCI_HFROSCCFG */) { - return 1 << 31; /* ROSC_RDY */ - } - if (addr == 8 /* PRCI_PLLCFG */) { - return 1 << 31; /* PLL_LOCK */ + SiFivePRCIState *s = opaque; + switch (addr) { + case SIFIVE_PRCI_HFROSCCFG: + return s->hfrosccfg; + case SIFIVE_PRCI_HFXOSCCFG: + return s->hfxosccfg; + case SIFIVE_PRCI_PLLCFG: + return s->pllcfg; + case SIFIVE_PRCI_PLLOUTDIV: + return s->plloutdiv; } hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); return 0; @@ -41,7 +44,30 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) static void sifive_prci_write(void *opaque, hwaddr addr, uint64_t val64, unsigned int size) { - /* discard writes */ + SiFivePRCIState *s = opaque; + switch (addr) { + case SIFIVE_PRCI_HFROSCCFG: + s->hfrosccfg = (uint32_t) val64; + /* OSC stays ready */ + s->hfrosccfg |= SIFIVE_PRCI_HFROSCCFG_RDY; + break; + case SIFIVE_PRCI_HFXOSCCFG: + s->hfxosccfg = (uint32_t) val64; + /* OSC stays ready */ + s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY; + break; + case SIFIVE_PRCI_PLLCFG: + s->pllcfg = (uint32_t) val64; + /* PLL stays locked */ + s->pllcfg |= SIFIVE_PRCI_PLLCFG_LOCK; + break; + case SIFIVE_PRCI_PLLOUTDIV: + s->plloutdiv = (uint32_t) val64; + break; + default: + hw_error("%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)val64); + } } static const MemoryRegionOps sifive_prci_ops = { @@ -61,6 +87,13 @@ static void sifive_prci_init(Object *obj) memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, TYPE_SIFIVE_PRCI, 0x8000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); + s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); + s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS | + SIFIVE_PRCI_PLLCFG_LOCK); + s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1; + } static const TypeInfo sifive_prci_info = { diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h index b6f4c486cc1e..bd51c4af3c1c 100644 --- a/include/hw/riscv/sifive_prci.h +++ b/include/hw/riscv/sifive_prci.h @@ -19,6 +19,34 @@ #ifndef HW_SIFIVE_PRCI_H #define HW_SIFIVE_PRCI_H +enum { + SIFIVE_PRCI_HFROSCCFG = 0x0, + SIFIVE_PRCI_HFXOSCCFG = 0x4, + SIFIVE_PRCI_PLLCFG = 0x8, + SIFIVE_PRCI_PLLOUTDIV = 0xC +}; + +enum { + SIFIVE_PRCI_HFROSCCFG_RDY = (1 << 31), + SIFIVE_PRCI_HFROSCCFG_EN = (1 << 30) +}; + +enum { + SIFIVE_PRCI_HFXOSCCFG_RDY = (1 << 31), + SIFIVE_PRCI_HFXOSCCFG_EN = (1 << 30) +}; + +enum { + SIFIVE_PRCI_PLLCFG_PLLSEL = (1 << 16), + SIFIVE_PRCI_PLLCFG_REFSEL = (1 << 17), + SIFIVE_PRCI_PLLCFG_BYPASS = (1 << 18), + SIFIVE_PRCI_PLLCFG_LOCK = (1 << 31) +}; + +enum { + SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8) +}; + #define TYPE_SIFIVE_PRCI "riscv.sifive.prci" #define SIFIVE_PRCI(obj) \ @@ -30,6 +58,10 @@ typedef struct SiFivePRCIState { /*< public >*/ MemoryRegion mmio; + uint32_t hfrosccfg; + uint32_t hfxosccfg; + uint32_t pllcfg; + uint32_t plloutdiv; } SiFivePRCIState; DeviceState *sifive_prci_create(hwaddr addr); From patchwork Thu Jun 27 15:19:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123439 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZNzs45Gvz9s3l for ; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id h1sm4117306pfg.55.2019.06.27.08.23.28 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:28 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:40 -0700 Message-Id: <20190627152011.18686-4-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.196 Subject: [Qemu-devel] [PULL 03/34] target/riscv: Fix PMP range boundary address bug X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Dayeol Lee , Palmer Dabbelt , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Dayeol Lee A wrong address is passed to `pmp_is_in_range` while checking if a memory access is within a PMP range. Since the ending address of the pmp range (i.e., pmp_state.addr[i].ea) is set to the last address in the range (i.e., pmp base + pmp size - 1), memory accesses containg the last address in the range will always fail. For example, assume that a PMP range is 4KB from 0x87654000 such that the last address within the range is 0x87654fff. 1-byte access to 0x87654fff should be considered to be fully inside the PMP range. However the access now fails and complains partial inclusion because pmp_is_in_range(env, i, addr + size) returns 0 whereas pmp_is_in_range(env, i, addr) returns 1. Signed-off-by: Dayeol Lee Reviewed-by: Alistair Francis Reviewed-by: Michael Clark Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index fed1c3c0301b..e0fe2064074a 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -245,7 +245,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, from low to high */ for (i = 0; i < MAX_RISCV_PMPS; i++) { s = pmp_is_in_range(env, i, addr); - e = pmp_is_in_range(env, i, addr + size); + e = pmp_is_in_range(env, i, addr + size - 1); /* partially inside */ if ((s + e) == 1) { From patchwork Thu Jun 27 15:19:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123442 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZP3X5gftz9s3l for ; Fri, 28 Jun 2019 01:30:13 +1000 (AEST) Received: from localhost ([::1]:51744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWLj-0006Zq-DQ for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:30:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60696) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWFk-0001V4-MT for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWFW-0006kb-Tz for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:23:51 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:34237) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWFQ-0006Zy-F1 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:23:40 -0400 Received: by mail-pg1-f194.google.com with SMTP id p10so1186875pgn.1 for ; Thu, 27 Jun 2019 08:23:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=jUXXdmFSNX/hvuM0z5WGc23QfyAO7JYoqYw1PuN09oU=; b=BLM8pCzK6d9Q1AVjjUTg1UlZBj8ZhkTH43PBlj3dFQd+DImph5XzamjucMLmwCTCdY /FJFgUSyD6iPbgAv3WDDIIwcgx0BZQvuWvnlNn1vNt6KgKDIDNpL3RGX4NS1i84k1h8o 7Bxk5Dq5xHx8JHqdM4tLlFUqQZBi3yxHorIDVaGWN1Wx/QGGUuXumcsth1IlNS0SC6Mb NC+9aNIuuTaZjObX114860b9TgnIfEOrXSo+O4B+meVlyP594BY+lkzuFQb7XiJGe6p/ 4Fdr00K4pT8bhI4K5EJxQbHIeDjOwfo13fpnoYpxqwTkeSiI5aKL7w92ditBSOkqHULd vWIw== X-Gm-Message-State: APjAAAXnI+AV62tovRL/nmkqWYyUz1rHboyTLWCuNincxXnEKwxpCft0 xu9tLFe15EzuzZpjLVruOv7t5nm+W9fcTw== X-Google-Smtp-Source: APXvYqwQHGWSi5dQ3ZNIi59TpZXIwgAa73Mgr6WM9PldSQ9IL3PqR2z+jBZxZz56eoNToDxxzmV1Rg== X-Received: by 2002:a63:88c1:: with SMTP id l184mr4300973pgd.376.1561649012380; Thu, 27 Jun 2019 08:23:32 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id v13sm3821903pfe.105.2019.06.27.08.23.31 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:31 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:41 -0700 Message-Id: <20190627152011.18686-5-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.194 Subject: [Qemu-devel] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Michael Clark , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Michael Clark This patch adds support for the riscv_cpu_unassigned_access call and will raise a load or store access fault. Signed-off-by: Michael Clark [Changes by AF: - Squash two patches and rewrite commit message - Set baddr to the access address ] Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 16 ++++++++++++++++ 3 files changed, 19 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0632ac08cf35..5b9fae608cca 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -482,6 +482,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY + cc->do_unassigned_access = riscv_cpu_unassigned_access; cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b47cde501766..2e743312536b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -259,6 +259,8 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write, + bool is_exec, int unused, unsigned size); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8b6754b91798..0bbfb7f48b79 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -375,6 +375,22 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } +void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, + bool is_exec, int unused, unsigned size) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (is_write) { + cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + } else { + cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; + } + + env->badaddr = addr; + riscv_raise_exception(&cpu->env, cs->exception_index, GETPC()); +} + void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) From patchwork Thu Jun 27 15:19:42 2019 Content-Type: text/plain; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id i126sm3786390pfb.32.2019.06.27.08.23.33 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:34 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:42 -0700 Message-Id: <20190627152011.18686-6-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.194 Subject: [Qemu-devel] [PULL 05/34] RISC-V: Only Check PMP if MMU translation succeeds X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Hesham Almatary Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Hesham Almatary The current implementation unnecessarily checks for PMP even if MMU translation failed. This may trigger a wrong PMP access exception instead of a page exception. For example, the very first instruction fetched after the first satp write in S-Mode will trigger a PMP access fault instead of an instruction fetch page fault. This patch prioritises MMU exceptions over PMP exceptions and only checks for PMP if MMU translation succeeds. This patch is required for future commits that properly report PMP exception violations if PTW succeeds. Signed-off-by: Hesham Almatary Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0bbfb7f48b79..a45b05ef8395 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -436,6 +436,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, " prot %d\n", __func__, address, ret, pa, prot); if (riscv_feature(env, RISCV_FEATURE_PMP) && + (ret == TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { ret = TRANSLATE_FAIL; } From patchwork Thu Jun 27 15:19:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123475 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPGr4wsBz9s3l for ; Fri, 28 Jun 2019 01:40:04 +1000 (AEST) Received: from localhost ([::1]:51838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWVG-00084b-Oi for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:40:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60784) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWGX-0001fa-2o for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWGS-0007TQ-PS for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:47 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:41834) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWGJ-0006do-Ey for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:41 -0400 Received: by mail-pg1-f196.google.com with SMTP id c70so1047003pga.8 for ; Thu, 27 Jun 2019 08:23:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=D1HIL5SBmBBlqGmn3DV7OFXg5gWo+HXWOwuA3mR3IqE=; b=mmwq4OM2z/PEyqZHgwXBjovyVMsy1feGGuWYBYi/v5c00HiSlgjlWoe3TsPB4wJQkE EE22/bu6TTFgbR9CKoDO51QOEzPG0YRehAwyw58SL6OeQrFoM/DLLvi7svA7dJMscIGG gRza5fdhDwZMcXf89gAQlDQoe6OVmmD0jwzecrLz3W5K/ORE5rRwvuUJG0fFLun1f0Ay MnFwjEb3mJ1HFptb8c/ByJ/C/lI47JhfRMA1Y0YyDusYOEQcknErlFiHQpIv2QRIPTOt YIgvRAPCP4pr0jbE9NBvsEdF49J3rBdXSdR39yrPx9GNjMQVl23TI4is0HDJRJ6jQ+ss u/Ww== X-Gm-Message-State: APjAAAXbQlc+M/oZUWk0yLNiBUB/1LlEdUOMOTkXUc1hHViBFPduF1Ha knc2HOFqkIqOXSuyarpJN5+AIA== X-Google-Smtp-Source: APXvYqxDaEWLLQB8fkwoK3yZU7rCX3qjMztCZ/F/6l+n7NunyB7bfU+/KEkS8baPbYJsjd/WtAiEYg== X-Received: by 2002:a17:90a:2430:: with SMTP id h45mr6962496pje.14.1561649016893; Thu, 27 Jun 2019 08:23:36 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id h1sm3166288pfo.152.2019.06.27.08.23.36 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:36 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:43 -0700 Message-Id: <20190627152011.18686-7-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.196 Subject: [Qemu-devel] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Hesham Almatary Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Hesham Almatary Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations report "access exceptions." The current PMP implementation has a bug which wrongly reports "page exceptions" on PMP violations. This patch fixes this bug by reporting the correct PMP access exceptions trap values. Signed-off-by: Hesham Almatary Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a45b05ef8395..ffbfaf433268 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -337,12 +337,13 @@ restart: } static void raise_mmu_exception(CPURISCVState *env, target_ulong address, - MMUAccessType access_type) + MMUAccessType access_type, bool pmp_violation) { CPUState *cs = env_cpu(env); int page_fault_exceptions = (env->priv_ver >= PRIV_VERSION_1_10_0) && - get_field(env->satp, SATP_MODE) != VM_1_10_MBARE; + get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && + !pmp_violation; switch (access_type) { case MMU_INST_FETCH: cs->exception_index = page_fault_exceptions ? @@ -424,6 +425,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, CPURISCVState *env = &cpu->env; hwaddr pa = 0; int prot; + bool pmp_violation = false; int ret = TRANSLATE_FAIL; qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", @@ -438,6 +440,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { + pmp_violation = true; ret = TRANSLATE_FAIL; } if (ret == TRANSLATE_SUCCESS) { @@ -447,7 +450,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type); + raise_mmu_exception(env, address, access_type, pmp_violation); riscv_raise_exception(env, cs->exception_index, retaddr); } #else From patchwork Thu Jun 27 15:19:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123482 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPS22n6yz9s3l for ; Fri, 28 Jun 2019 01:48:01 +1000 (AEST) Received: from localhost ([::1]:51926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWcx-0007Iw-Tv for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:47:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33176) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHd-0003FT-Kt for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHZ-0000Bn-7z for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:56 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:40849) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHW-0006g1-Te for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:51 -0400 Received: by mail-pl1-f195.google.com with SMTP id a93so1492675pla.7 for ; Thu, 27 Jun 2019 08:23:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=88zslYUcPLzZ8t2plNr1KKUO0CCDFAsO4z2B6UJDjVI=; b=cKiyWHQTlusATTUVD4DeX1L0w8qHWKJ568EVlNHF8MK58HP3gYY3/jhoGzbsI6iasJ yU7YDAEaChjaY1LGS0kIQOz84Po1xfbAuc75VF/oyx5ttb7VbZWRnTgNl6BhkAFomVuI +EuURV+jPwF0Eo60CUZZp73gmZT0CzKZuV+3fuxN5FKaS8sgCVK4pPPplL9jGcaOkmkY QFqboJrx7n+3C4beaK5XbjvjUVEN+5SRLQ/6PCkC8HZ4IGJOciHAK+7ed4yaB0k6TcFQ A7VMZ0zEe0Dr6GaUraf3gezXT9Zu2aXOyhUzEXiId8hyRgiyACwHZu+zdCz8DSyVPI5X GwHg== X-Gm-Message-State: APjAAAWnVwmSOQknq9Ysn+eMRPZJ/LZ05Mu6I9iUId9Avw0lgnU+4rgq 8oTMFQlE4yT2QzCc7jRt5c6G9w== X-Google-Smtp-Source: APXvYqzfYJMkURulSsXl5tjWUD75OA2vhPy3ZvA/dEdMimihJ4Cy0ZlHAntJAM8QtQyj57rBifNmUQ== X-Received: by 2002:a17:902:2a27:: with SMTP id i36mr5241418plb.161.1561649019753; Thu, 27 Jun 2019 08:23:39 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id q126sm5110291pfq.123.2019.06.27.08.23.38 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:39 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:44 -0700 Message-Id: <20190627152011.18686-8-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.195 Subject: [Qemu-devel] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Hesham Almatary Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Hesham Almatary The current PMP check function checks for env->priv which is not the effective memory privilege mode. For example, mstatus.MPRV could be set while executing in M-Mode, and in that case the privilege mode for the PMP check should be S-Mode rather than M-Mode (in env->priv) if mstatus.MPP == PRV_S. This patch passes the effective memory privilege mode to the PMP check. Functions that call the PMP check should pass the correct memory privilege mode after reading mstatus' MPRV/MPP or hstatus.SPRV (if Hypervisor mode exists). Suggested-by: Alistair Francis Signed-off-by: Hesham Almatary Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 10 +++++++++- target/riscv/pmp.c | 6 +++--- target/riscv/pmp.h | 2 +- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ffbfaf433268..71b8123b1019 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -427,19 +427,27 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, int prot; bool pmp_violation = false; int ret = TRANSLATE_FAIL; + int mode = mmu_idx; qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx); + if (mode == PRV_M && access_type != MMU_INST_FETCH) { + if (get_field(env->mstatus, MSTATUS_MPRV)) { + mode = get_field(env->mstatus, MSTATUS_MPP); + } + } + qemu_log_mask(CPU_LOG_MMU, "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx " prot %d\n", __func__, address, ret, pa, prot); if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type, + mode)) { pmp_violation = true; ret = TRANSLATE_FAIL; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index e0fe2064074a..5944f4cb6607 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -228,7 +228,7 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) * Check if the address has required RWX privs to complete desired operation */ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, - target_ulong size, pmp_priv_t privs) + target_ulong size, pmp_priv_t privs, target_ulong mode) { int i = 0; int ret = -1; @@ -264,7 +264,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, } allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; - if ((env->priv != PRV_M) || pmp_is_locked(env, i)) { + if ((mode != PRV_M) || pmp_is_locked(env, i)) { allowed_privs &= env->pmp_state.pmp[i].cfg_reg; } @@ -280,7 +280,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, /* No rule matched */ if (ret == -1) { - if (env->priv == PRV_M) { + if (mode == PRV_M) { ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an * M-Mode access, the access succeeds */ } else { diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index 66790950eb75..8e19793132db 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -59,6 +59,6 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, target_ulong val); target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, - target_ulong size, pmp_priv_t priv); + target_ulong size, pmp_priv_t priv, target_ulong mode); #endif From patchwork Thu Jun 27 15:19:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123479 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id 12sm3088819pfi.60.2019.06.27.08.23.41 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:41 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:45 -0700 Message-Id: <20190627152011.18686-9-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.170 Subject: [Qemu-devel] [PULL 08/34] RISC-V: Check PMP during Page Table Walks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Behrens , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Hesham Almatary Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Hesham Almatary The PMP should be checked when doing a page table walk, and report access fault exception if the to-be-read PTE failed the PMP check. Suggested-by: Jonathan Behrens Signed-off-by: Hesham Almatary Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2e743312536b..934b71c85e13 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ enum { #define PRIV_VERSION_1_09_1 0x00010901 #define PRIV_VERSION_1_10_0 0x00011000 +#define TRANSLATE_PMP_FAIL 2 #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 #define MMU_USER_IDX 3 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 71b8123b1019..66be83210f11 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -230,6 +230,12 @@ restart: /* check that physical address of PTE is legal */ target_ulong pte_addr = base + idx * ptesize; + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), + 1 << MMU_DATA_LOAD, PRV_S)) { + return TRANSLATE_PMP_FAIL; + } #if defined(TARGET_RISCV32) target_ulong pte = ldl_phys(cs->as, pte_addr); #elif defined(TARGET_RISCV64) @@ -448,8 +454,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, (ret == TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type, mode)) { + ret = TRANSLATE_PMP_FAIL; + } + if (ret == TRANSLATE_PMP_FAIL) { pmp_violation = true; - ret = TRANSLATE_FAIL; } if (ret == TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, From patchwork Thu Jun 27 15:19:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123484 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPWt45Kqz9s3l for ; Fri, 28 Jun 2019 01:51:22 +1000 (AEST) Received: from localhost ([::1]:51952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWgB-00006p-Kp for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:51:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32825) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHJ-0002gX-01 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHE-0008Hj-Fp for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:35 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:36623) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWH9-0006jD-2i for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:32 -0400 Received: by mail-pg1-f193.google.com with SMTP id c13so1180633pgg.3 for ; Thu, 27 Jun 2019 08:23:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=nCqKF3oInYRXPwJWI7RpGGCzJlHRvb4E4bj4yY7JdO8=; b=jrN0RRKRimVoU+wqDpnazVVPiMByEgVKyJSBcL9KjJVL7jGXMv2akmfoSPD/qRNFx1 JuRTS0gmEoj886lwjSxsya9+6RGGtFEr4OQk2vrXTq/ZmNutyj2psDgEqYzsRquHBEej LkNgGlhPnlLOrv7Q//l6Niimrpa8cbqXoEiEFJRVh7ZAh6fd88bAZDWhjPeAdXWmQ6Z8 eZqM79KuEd9rjqP/DLzSo0c1QuwzWQ+mdF3Mu/dzXVPyU9K4CRKpyANE6X8VkRH4Jl6C ncytNPi6CpVM/f6LBYpLhznQmciPznwjKzvpsUh3+MT4fkOxtmtrgAKk0ToEPpckOcyn 3jwg== X-Gm-Message-State: APjAAAWtcrhzEQU/sLQmvz8lhFYN6ppqqbNdZ8vuWgziKbE8qnjR6xrM CVyEixky/BOfIpos5ihCvGHKkA== X-Google-Smtp-Source: APXvYqxQicao0ppWeUilfhR+0a2GeGzhgPiD9dF6hP9iUcRv+KdNY+sceD6OEu6ncermiJcsuH5SEw== X-Received: by 2002:a63:2ad5:: with SMTP id q204mr4370120pgq.140.1561649024131; Thu, 27 Jun 2019 08:23:44 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id y23sm5311422pfo.106.2019.06.27.08.23.43 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:43 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:46 -0700 Message-Id: <20190627152011.18686-10-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.193 Subject: [Qemu-devel] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Hesham Almatary Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Hesham Almatary The current implementation returns 1 (PMP check success) if the address is in range even if the PMP entry is off. This is a bug. For example, if there is a PMP check in S-Mode which is in range, but its PMP entry is off, this will succeed, which it should not. The patch fixes this bug by only checking the PMP permissions if the address is in range and its corresponding PMP entry it not off. Otherwise, it will keep the ret = -1 which will be checked and handled correctly at the end of the function. Signed-off-by: Hesham Almatary Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 5944f4cb6607..958c7502a0e0 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -258,11 +258,12 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, /* fully inside */ const uint8_t a_field = pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); - if ((s + e) == 2) { - if (PMP_AMATCH_OFF == a_field) { - return 1; - } + /* + * If the PMP entry is not off and the address is in range, do the priv + * check + */ + if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) { allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; if ((mode != PRV_M) || pmp_is_locked(env, i)) { allowed_privs &= env->pmp_state.pmp[i].cfg_reg; From patchwork Thu Jun 27 15:19:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123492 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPhm1Qcbz9s3l for ; Fri, 28 Jun 2019 01:59:03 +1000 (AEST) Received: from localhost ([::1]:52018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWnd-0001a3-Pq for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:59:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33010) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHW-0003A1-P3 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHU-00005B-I7 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:50 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:39100) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHT-0006l2-Ff for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:47 -0400 Received: by mail-pl1-f193.google.com with SMTP id b7so1484209pls.6 for ; Thu, 27 Jun 2019 08:23:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=EKsqQug7v7zszsNqo0b9Js3bl54LND9OiSrVub9vLW4=; b=G+ww913SqskSV/csvNAEWyObTKRHgWt/6gIAwrOoAfBPQfwuPYj9Y4K77134dMRjg8 q6KMxVqLonZm6EBVrmu8NbPXcgnAR8Gc+SHLJh5cbTs06iKkE+fQ9Ng8p3CtwWRG93nQ JUU3mKBB8CabWapVcYeIuaE3Xn/d5NIHGneEyfoNeQTyzNzMXs41wK+8U875l+8SXyUO /qPY6zEN+UtH73G9jgYi5Xy2SP4VVXWS9n9HDXqrPp5yhCtNNGN6xovXmXvWhBV7/Ky5 2ADlB8zCEDjBtnsd8WMEFYgegxlOMnA+66qVUbv357TydXltf6YyZ3fVWDMovXMVH62s vxBA== X-Gm-Message-State: APjAAAX3rWqvywLnKO6RGvfhwwmzAJBbm0sfcNqHTetRpqIs9LrG1c2Q UL8D+m9rnPXNv6uaGzMVkv/qNg== X-Google-Smtp-Source: APXvYqyRMQg2H4LjYcqHOJbejMMN+hBHC7SOa/P/+uW0VsKzuXmE5DIcEDTPnnw01BoTEWHqExXJ+A== X-Received: by 2002:a17:902:a517:: with SMTP id s23mr5262268plq.306.1561649026947; Thu, 27 Jun 2019 08:23:46 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id o14sm5045356pjp.29.2019.06.27.08.23.46 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:46 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:47 -0700 Message-Id: <20190627152011.18686-11-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.193 Subject: [Qemu-devel] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Hesham Almatary Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Hesham Almatary The PMP check should be of the memory access size rather than TARGET_PAGE_SIZE. Signed-off-by: Hesham Almatary Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 66be83210f11..e1b079e69c60 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -452,8 +452,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type, - mode)) { + !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { ret = TRANSLATE_PMP_FAIL; } if (ret == TRANSLATE_PMP_FAIL) { From patchwork Thu Jun 27 15:19:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123485 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPXM6glcz9s3l for ; Fri, 28 Jun 2019 01:51:47 +1000 (AEST) Received: from localhost ([::1]:51960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWgc-0000OM-0J for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:51:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33119) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHa-0003Dn-HO for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHW-00008O-Uk for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:53 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:34260) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHW-0006mV-HB for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:50 -0400 Received: by mail-pg1-f196.google.com with SMTP id p10so1187191pgn.1 for ; Thu, 27 Jun 2019 08:23:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=tHJ8TJeA8y3lZE06LLG15C3UoFOsuUPcKgVUlFGD2eo=; b=gFVJJJOaYU7EKQ2w7fZ5Se9Dco0JFQpvOxGsllFTAVKFApiyEgkPsjaVEz1E1+ANnT DSws7brIqY39pJpKPhkaHrYNYsVYsjBCmykVdpuqykfoQWsXHvgs5nDSKMjbdUaC56Ei LM2jdilqiJu3R+4L0oXtxq1IEqCPpNAyLDpnh85R3ftXw9yO797sFLa1XwrexTO5o+u3 7dwC6JHHUvcbidQnbQzllQqAs2BBZQRBsDRdsDn9r35oE2jX6swDd/f7qxYBWXG7pw3y QKPigw9h5lp7Id2eP9knrlMr760NNLb3Z232IAU1NJLdijoLMymcIbcadFtKhz01vJ8x 63vA== X-Gm-Message-State: APjAAAWXvoMvx8dHbwt/tPL/Ai/vS8Orp+7YoNvaA2SCA8wyXnG8D1TC K3CaZL4oUnJV31cmx6swVobd9Q== X-Google-Smtp-Source: APXvYqxAAiSGsJEMq09qAbmcVjS+lWBRmocPW0miY46BEjRuxT0HRsJB0zJ/PMtGlOiiuAHiSv9DZA== X-Received: by 2002:a17:90a:7f02:: with SMTP id k2mr6180344pjl.78.1561649029253; Thu, 27 Jun 2019 08:23:49 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id f186sm3156781pfb.5.2019.06.27.08.23.48 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:48 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:48 -0700 Message-Id: <20190627152011.18686-12-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.196 Subject: [Qemu-devel] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng The largest pci bus number should be calculated from ECAM size, instead of its base address. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 84d94d0c42d8..487f61404b21 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -298,7 +298,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0); qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0, - memmap[VIRT_PCIE_ECAM].base / + memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base, From patchwork Thu Jun 27 15:19:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123478 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPLQ38lyz9s3l for ; Fri, 28 Jun 2019 01:43:09 +1000 (AEST) Received: from localhost ([::1]:51860 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWYA-0003GP-DD for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:43:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33170) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHc-0003Dq-KU for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHX-00008m-5L for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:54 -0400 Received: from mail-pg1-f173.google.com ([209.85.215.173]:34410) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHW-0006pM-Nz for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:50 -0400 Received: by mail-pg1-f173.google.com with SMTP id p10so1187236pgn.1 for ; Thu, 27 Jun 2019 08:23:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=4yIbg4wQD3g4mppuKoX6VmO7ZtWwJtsrHDtVUEb9gdk=; b=m8yfKnaUPlomR5QJZxb9vT1ACuMcFQuqlS6HJMlgwMSa2EIQ0LGSDXm2wvwEbvOwfN QSshCbdV62m6hmRNV+ei8/kF+NhG5CaNVeqz0cdSGBCUCmYLTR6+QjtsWJjgj56mrj6w ft4FHNn1eox70xJ1zw/wiVfTsm1z0YR0Fh1AFCr2PwUXqo4jqrmQAWx8nia8dYWBrqzP eMMVImnPJgeDb322QCidE0RaruGeK9TsLArrlm5Jb0AUMDBKFuQhdt3VOY+C7HfbuVxl 8cRES2A8lk43v9FgCaLduY5gxPhfWgbwM9ZImHdO96OrS09Jl2gYoWwyNqfet+gFiSRf 8Nzg== X-Gm-Message-State: APjAAAXVVM8n9HRuAwKjyqq3S8bhZ2r8jt1yzLx7tSaUtX5UL0f8Ymtw v+S4FABQOYHrPkstJ9E6qkdNCQ== X-Google-Smtp-Source: APXvYqz6pcnvPX2KZOFHTXI7pFTur2BiU0yki97vVm4XDwHQNkUZkVKZDwP3Yvd6v8BIPoCiPUY8SQ== X-Received: by 2002:a17:90a:1d8:: with SMTP id 24mr6891888pjd.70.1561649032005; Thu, 27 Jun 2019 08:23:52 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id h21sm2503665pgg.75.2019.06.27.08.23.51 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:51 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:49 -0700 Message-Id: <20190627152011.18686-13-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.173 Subject: [Qemu-devel] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-riscv@nongnu.org, Palmer Dabbelt , qemu-devel@nongnu.org, Alistair Francis , ilippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(), where a pair of recently added MemoryRegion instances would not be freed if there were errors elsewhere in the function. The fix here is to simply not use dynamic allocation for these instances: there's always one of each in SiFiveESoCState, so instead we just include them within the struct. Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device") Signed-off-by: Palmer Dabbelt Suggested-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c | 13 ++++++------- include/hw/riscv/sifive_e.h | 2 ++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 80ac56fa7d5e..a5b4086da36d 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -158,17 +158,15 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) SiFiveESoCState *s = RISCV_E_SOC(dev); MemoryRegion *sys_mem = get_system_memory(); - MemoryRegion *xip_mem = g_new(MemoryRegion, 1); - MemoryRegion *mask_rom = g_new(MemoryRegion, 1); object_property_set_bool(OBJECT(&s->cpus), true, "realized", &error_abort); /* Mask ROM */ - memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom", + memory_region_init_rom(&s->mask_rom, NULL, "riscv.sifive.e.mrom", memmap[SIFIVE_E_MROM].size, &error_fatal); memory_region_add_subregion(sys_mem, - memmap[SIFIVE_E_MROM].base, mask_rom); + memmap[SIFIVE_E_MROM].base, &s->mask_rom); /* MMIO */ s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, @@ -228,10 +226,11 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); /* Flash memory */ - memory_region_init_ram(xip_mem, NULL, "riscv.sifive.e.xip", + memory_region_init_ram(&s->xip_mem, NULL, "riscv.sifive.e.xip", memmap[SIFIVE_E_XIP].size, &error_fatal); - memory_region_set_readonly(xip_mem, true); - memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem); + memory_region_set_readonly(&s->xip_mem, true); + memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, + &s->xip_mem); } static void riscv_sifive_e_machine_init(MachineClass *mc) diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 3b14eb74621f..d175b24cb209 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -33,6 +33,8 @@ typedef struct SiFiveESoCState { RISCVHartArrayState cpus; DeviceState *plic; SIFIVEGPIOState gpio; + MemoryRegion xip_mem; + MemoryRegion mask_rom; } SiFiveESoCState; typedef struct SiFiveEState { From patchwork Thu Jun 27 15:19:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123473 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPFC3hbbz9s3l for ; Fri, 28 Jun 2019 01:38:39 +1000 (AEST) Received: from localhost ([::1]:51822 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWTt-00064Q-IC for incoming@patchwork.ozlabs.org; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id 131sm7652151pfx.57.2019.06.27.08.23.53 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:53 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:50 -0700 Message-Id: <20190627152011.18686-14-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.176 Subject: [Qemu-devel] [PULL 13/34] target/riscv: Restructure deprecatd CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Restructure the deprecated CPUs to make it clear in the code that these are depreated. They are already marked as deprecated in qemu-deprecated.texi. There are no functional changes. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 18 ++++++++++-------- target/riscv/cpu.h | 13 +++++++------ 2 files changed, 17 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5b9fae608cca..17467c3d8705 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -559,18 +559,20 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init) + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), + /* Depreacted */ + DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init) #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init) + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init), + /* Deprecated */ + DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init) #endif }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 934b71c85e13..5eb9cab2ad62 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -35,16 +35,17 @@ #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +/* Deprecated */ +#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") +#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") +#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") +#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") +#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") +#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) From patchwork Thu Jun 27 15:19:51 2019 Content-Type: text/plain; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id y17sm2811152pfe.148.2019.06.27.08.23.56 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:56 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:51 -0700 Message-Id: <20190627152011.18686-15-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.195 Subject: [Qemu-devel] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Add support for the ratified RISC-V privledge spec. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_privileged.inc.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5eb9cab2ad62..d559d28bcda8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ enum { #define USER_VERSION_2_02_0 0x00020200 #define PRIV_VERSION_1_09_1 0x00010901 #define PRIV_VERSION_1_10_0 0x00011000 +#define PRIV_VERSION_1_11_0 0x00011100 #define TRANSLATE_PMP_FAIL 2 #define TRANSLATE_FAIL 1 diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c index 664d6ba3f2cc..c5e4b3e49a3e 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -90,7 +90,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver == PRIV_VERSION_1_10_0) { + if (ctx->priv_ver >= PRIV_VERSION_1_10_0) { gen_helper_tlb_flush(cpu_env); return true; } From patchwork Thu Jun 27 15:19:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123440 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZP3125hVz9s3l for ; Fri, 28 Jun 2019 01:29:49 +1000 (AEST) Received: from localhost ([::1]:51734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWLL-0006Jz-5h for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:29:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60748) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWGP-0001dX-4K for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWGB-0007Fz-Lb for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:30 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:41956) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWG6-0006ui-Au for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:24 -0400 Received: by mail-pf1-f193.google.com with SMTP id m30so1396910pff.8 for ; Thu, 27 Jun 2019 08:24:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=dUa00V6qaWWvVsCSIWO0c3PzQTzV7TrVR8O4HvR6bag=; b=RYz4i1QSA3J56ZzubxD+B9rEIng+WMQZ/G1HZptWncD//Zry5bk14saQPhtQaaZO+A PIwh5pj1I5b5t1seF5yWv4042nxUBrk0rrNHvAHCM4iWMdKC+UPrme7GHPIxQ1Ssf6BU gx/FyOu/k5zbD6EB28ATbAXQp97UButtp3Ko45GwMwHyz5xN80QuhIddEgShV3sPcHIX IQyBTKN5jQYpw3IMWGakMo4Z5ono3NgZfxjJAzGTSybuCyEwT1OyzTkzL6bZPuQsZOnk +o6kr0TxRjNlcFWjwpBTjnh3AgYS1F3U4TpmUhbPk6NHYhqWYw0rB9RCvue/DiCMrhSK c1nA== X-Gm-Message-State: APjAAAXFpxl7tvppCIf3zJ2Ef18T4Y3rcs2xtuzEyRCSjWlWHeD5M28S 5/LQmabOi1Jfy3xbiwVKv5GWav3lxUDDRQ== X-Google-Smtp-Source: APXvYqwQgN5/LmKjlIe2CqkG8AttvBcAU71oo+Phep6R727Cf8Wu7mi+ef3OwvECyNUt/tT9pKyRyg== X-Received: by 2002:a17:90a:fa07:: with SMTP id cm7mr6535545pjb.138.1561649039305; Thu, 27 Jun 2019 08:23:59 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id v13sm3822822pfe.105.2019.06.27.08.23.58 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:23:58 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:52 -0700 Message-Id: <20190627152011.18686-16-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.193 Subject: [Qemu-devel] [PULL 15/34] target/riscv: Add the mcountinhibit CSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis 1.11 defines mcountinhibit, which has the same numeric CSR value as mucounteren from 1.09.1 but has different semantics. This patch enables the CSR for 1.11-based targets, which is trivial to implement because the counters in QEMU never tick (legal according to the spec). Signed-off-by: Alistair Francis [Palmer: Fix counter access semantics, change commit message to indicate the behavior is fully emulated.] Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 17 +++++++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 47450a3cdb75..11f971ad5df0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -136,6 +136,7 @@ #define CSR_MCOUNTEREN 0x306 /* Legacy Counter Setup (priv v1.9.1) */ +/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */ #define CSR_MUCOUNTEREN 0x320 #define CSR_MSCOUNTEREN 0x321 #define CSR_MHCOUNTEREN 0x322 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c67d29e20618..448162e484a3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -56,6 +56,15 @@ static int fs(CPURISCVState *env, int csrno) static int ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) + /* + * The counters are always enabled on newer priv specs, as the CSR has + * changed from controlling that the counters can be read to controlling + * that the counters increment. + */ + if (env->priv_ver > PRIV_VERSION_1_09_1) { + return 0; + } + uint32_t ctr_en = ~0u; if (env->priv < PRV_M) { @@ -461,18 +470,22 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) return 0; } +/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) { - if (env->priv_ver > PRIV_VERSION_1_09_1) { + if (env->priv_ver > PRIV_VERSION_1_09_1 + && env->priv_ver < PRIV_VERSION_1_11_0) { return -1; } *val = env->mcounteren; return 0; } +/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) { - if (env->priv_ver > PRIV_VERSION_1_09_1) { + if (env->priv_ver > PRIV_VERSION_1_09_1 + && env->priv_ver < PRIV_VERSION_1_11_0) { return -1; } env->mcounteren = val; From patchwork Thu Jun 27 15:19:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPML3Prnz9s3l for ; Fri, 28 Jun 2019 01:43:58 +1000 (AEST) Received: from localhost ([::1]:51884 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWZ2-0004R6-Ht for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:43:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32794) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHD-0002RZ-Nv for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWGz-000867-Uo for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:22 -0400 Received: from mail-pg1-f175.google.com ([209.85.215.175]:35341) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWGs-0006wO-EH for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:12 -0400 Received: by mail-pg1-f175.google.com with SMTP id s27so1181736pgl.2 for ; Thu, 27 Jun 2019 08:24:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=CCTUA83WsmaGam2XV7hw8vEWvHgX2YXg8c48BvbdAho=; b=Ut8NElNL/vjp6H6pXcpYolFrMadSNU8muQgeby7sWG1OAj+LlL08iPopcEdTjWrGxk pniIofgE93Jri3W5HSRz4So6/luGqK44z0rJVPVCfJDEZwJlmZE/MqdJe3JwwL7wESfN vxW8gfC0nHW8LtVH8emAYl+05y+V7i11+328K388jAvq1QsTsHhrEYn0ycT5Zunnu4lx pkLCWZVWtzYlsFZbadxpCw/grCaOWRqFp5kdkspRiF9GvyVF/0eWDQlrLJtl8x87EE24 P3tOYdvOH1f0tA4/J9OPYSnHZQX0h0AwDHhu3fbcxPoKfNzKFjb5UDEE258ypkG0WnVw 3QqA== X-Gm-Message-State: APjAAAWnZeb9Ws8KlOl3Uy0hatj/GWTY8HdPhYQBrlk4syQHfrP6cqr+ kv1YNUoqUIFB0KwxMkSEgV+orw== X-Google-Smtp-Source: APXvYqwdun/Pc4FDTZr4WsAuLyEp5dsBzZz48Gz4opJwCxarnmVLacjTq48APNlgcRfNTot7dUA/3Q== X-Received: by 2002:a17:90a:a397:: with SMTP id x23mr6870749pjp.118.1561649041728; Thu, 27 Jun 2019 08:24:01 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id f10sm2485802pgq.73.2019.06.27.08.24.00 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:01 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:53 -0700 Message-Id: <20190627152011.18686-17-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.175 Subject: [Qemu-devel] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Set the priv spec version 1.11.0 as the default and allow selecting it via the command line. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 17467c3d8705..ba1325f43533 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -111,7 +111,7 @@ static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); - set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_11_0); set_resetvec(env, DEFAULT_RSTVEC); } @@ -316,7 +316,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) RISCVCPU *cpu = RISCV_CPU(dev); CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); - int priv_version = PRIV_VERSION_1_10_0; + int priv_version = PRIV_VERSION_1_11_0; int user_version = USER_VERSION_2_02_0; target_ulong target_misa = 0; Error *local_err = NULL; @@ -328,7 +328,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + priv_version = PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { priv_version = PRIV_VERSION_1_10_0; } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) { priv_version = PRIV_VERSION_1_09_1; From patchwork Thu Jun 27 15:19:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPs94d0Lz9s4Y for ; Fri, 28 Jun 2019 02:06:21 +1000 (AEST) Received: from localhost ([::1]:52066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWug-0006Sn-KA for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 12:06:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33015) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHW-0003A6-P4 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHU-00004y-I2 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:50 -0400 Received: from mail-pf1-f182.google.com ([209.85.210.182]:44341) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHT-0006yB-Ij for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:47 -0400 Received: by mail-pf1-f182.google.com with SMTP id t16so1392669pfe.11 for ; Thu, 27 Jun 2019 08:24:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=tqiS7O8nKvNing+E8WwiszCtPiLlK33kP79Ar4czLaU=; b=oUYwonsvbtOehNAPCc68VsyeA2dwF6jwT+lb6sMmuWMp3RsYD9XbrgsgudmFazrTOM ob7/TukO2BryuC7WYb11tDtN6Glc1a3l8fOllp+bz1Vvc4bVSQ+9XIeFt5FWLpNWlRwR SuvIoKtU28XeVi/a2O/nEyUC35CNyALTC/24SBxolmw/kqiJ5jgaeQea756lx7Xz2xuv +sK2MNIgA/4anvCFPxKWIrnur0LjT7myXu156JzqCj8KpvpPtau5YwTu82l34OTISd6l TnxO6Z4qRE2WwKfFDaWOVAirb6FTxwEotioOY3VO5/ErEmPUZevHSpWWKpQFe7Y3v/ox ZuCg== X-Gm-Message-State: APjAAAXplIesir/UCCuKjuzmQlN2qdURR3f4KBZIQr9AFZHQbR09t872 F/bKjpQ4DhbiP2uj/Rl/WgALygmsLACGsg== X-Google-Smtp-Source: APXvYqz4HgwfLHomu9GYtfbmHFaxeAkcApncvVLSSz0rgVyDrt/RXlulYvCVWYc0EhsHxAUulnhFYA== X-Received: by 2002:a63:1462:: with SMTP id 34mr4283972pgu.417.1561649044358; Thu, 27 Jun 2019 08:24:04 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id d123sm3437041pfc.144.2019.06.27.08.24.03 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:03 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:54 -0700 Message-Id: <20190627152011.18686-18-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.182 Subject: [Qemu-devel] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new 1.10.0 and the ratified 1.11.0. Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- qemu-deprecated.texi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi index df04f2840bd9..97ea4ef3001a 100644 --- a/qemu-deprecated.texi +++ b/qemu-deprecated.texi @@ -144,6 +144,14 @@ The ``acl_show'', ``acl_reset'', ``acl_policy'', ``acl_add'', and ``acl_remove'' commands are deprecated with no replacement. Authorization for VNC should be performed using the pluggable QAuthZ objects. +@section Guest Emulator ISAs + +@subsection RISC-V ISA privledge specification version 1.09.1 (since 4.1) + +The RISC-V ISA privledge specification version 1.09.1 has been deprecated. +QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these +should be used instead of the 1.09.1 version. + @section System emulator CPUS @subsection RISC-V ISA CPUs (since 4.1) From patchwork Thu Jun 27 15:19:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123498 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPt75Kl4z9s4Y for ; Fri, 28 Jun 2019 02:07:11 +1000 (AEST) Received: from localhost ([::1]:52076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWvV-0000Bj-Px for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 12:07:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33289) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHk-0003Kd-HC for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHg-0000LU-KA for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:01 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:40893) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHe-0006zd-6d for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:59 -0400 Received: by mail-pl1-f195.google.com with SMTP id a93so1493291pla.7 for ; Thu, 27 Jun 2019 08:24:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=WFOcqA5bhC2gv8hijUonjP/cUpFUXz32Bb/6MGXuT1U=; b=Qxbfci8BCjMkQDWgwIp7Qoqk1E8Gz9kJeC8+Q/BObFnFZ8ZpYwpIaEoAwLxstulukd La54cOrPqjNqHoYBRR4cCCvnl8qMODDHFFnSpHyXMuFmBrQmOXpndx1vWsKi/iT9q/T9 GRPthuAMKuJFH7aTqDLnRVHsRhHtE55tnLXCvjamC375PtIKzqlTCbc1ZsFnDMBuD0hZ 9kWJbI9lv/+23SADpZVfrF/mW6Ir0igYbHonlY2V+23gk+KBLcZ0GnuP4cF6JU9gPZnL leV20Pn6YeTzsdKrj9uzDr87bO+JkUlnX9cYl73foOqYco1/cyO2wDl02jUlSWh4wTc/ VBCQ== X-Gm-Message-State: APjAAAXLApLjQ5kHgjn+op48oEp+8kILS4YmGCQc/uUAunlpkqMTQUrJ e/Bea9CR4pdLupB9xXW7YfhBlw== X-Google-Smtp-Source: APXvYqxG+ii9erYoAAqHdSYPSfz4oS3lxy4uCURenbKkx2GKib/HRzewyohSuqz9t37LPiWGQUwmlw== X-Received: by 2002:a17:902:f204:: with SMTP id gn4mr5376927plb.3.1561649046472; Thu, 27 Jun 2019 08:24:06 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id p6sm2648446pgs.77.2019.06.27.08.24.05 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:06 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:55 -0700 Message-Id: <20190627152011.18686-19-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.195 Subject: [Qemu-devel] [PULL 18/34] target/riscv: Require either I or E base extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ba1325f43533..1689ffecf85f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -373,6 +373,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & cpu->cfg.ext_a & cpu->cfg.ext_f & cpu->cfg.ext_d)) { From patchwork Thu Jun 27 15:19:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123472 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZP9l6PjLz9s3l for ; Fri, 28 Jun 2019 01:35:39 +1000 (AEST) Received: from localhost ([::1]:51799 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWQz-0003D4-TO for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:35:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60818) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWGc-0001l0-K6 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWGa-0007cS-0v for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:54 -0400 Received: from mail-pl1-f173.google.com ([209.85.214.173]:39226) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWGY-00071I-Ux for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:51 -0400 Received: by mail-pl1-f173.google.com with SMTP id b7so1484720pls.6 for ; Thu, 27 Jun 2019 08:24:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=f47wk3zk+NrAkxWNULcRjGx8TZzZ5xzH7RJlcRZY1+U=; b=Qr1bmkQTuiWpRmPpGIHEuDehNWM7//yd+Eh4+CvbnXEnUoPuL3dalyBYdYevLOQCfB gyimL/Rt4bDFwwJLrFNaUGoVzqYTrJj7rndBqgaM/Zk/WEh7mHrlZWrJAKUj7eQz/Eh+ 2Z6GHRhRkR+knDYFsZJ34plUvZb+bvSqBs+uwtJ74dZBo4H3BpqHSt9DsK5mREU8FXxe v/zJ7fjv8eNTx+WkX1JD/TkyvsjjMKYsf6rfaWDsF15q6mMEM/DtVc0CZCudBb1Rj4BI pBhqkKM82w5zQVusOsEpE+vJHBzYKzNokRDxdvLN/f+D5YRSXUYxcMgVhAVNQdgewT1B Wnzw== X-Gm-Message-State: APjAAAXAwBb7TuOudnxVkwgc1g8PMdiBteD2Q/K+WlQvDyDyToC9BPfG E0EXASZmBMHDR75CtgBmiKurxg== X-Google-Smtp-Source: APXvYqxR5iOKD9MBtwxw88Bz8JzTXzb+lyy9NHsUm1AvKlcLO7HNsdDFYLSpXlS7s3GKXbH/8gmmRQ== X-Received: by 2002:a17:902:294a:: with SMTP id g68mr5427324plb.169.1561649048711; Thu, 27 Jun 2019 08:24:08 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id t2sm3302141pfh.166.2019.06.27.08.24.07 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:08 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:56 -0700 Message-Id: <20190627152011.18686-20-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.173 Subject: [Qemu-devel] [PULL 19/34] target/riscv: Remove user version information X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Remove the user version information. This was never used and never publically exposed in a release of QEMU, so let's just remove it. In future to manage versions we can extend the extension properties to specify version. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 32 +++++++++----------------------- target/riscv/cpu.h | 2 -- 2 files changed, 9 insertions(+), 25 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1689ffecf85f..6a54ebf10c62 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -89,9 +89,8 @@ static void set_misa(CPURISCVState *env, target_ulong misa) env->misa_mask = env->misa = misa; } -static void set_versions(CPURISCVState *env, int user_ver, int priv_ver) +static void set_priv_version(CPURISCVState *env, int priv_ver) { - env->user_ver = user_ver; env->priv_ver = priv_ver; } @@ -111,7 +110,7 @@ static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); - set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_11_0); set_resetvec(env, DEFAULT_RSTVEC); } @@ -128,7 +127,7 @@ static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1); + set_priv_version(env, PRIV_VERSION_1_09_1); set_resetvec(env, DEFAULT_RSTVEC); set_feature(env, RISCV_FEATURE_MMU); set_feature(env, RISCV_FEATURE_PMP); @@ -138,7 +137,7 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); set_feature(env, RISCV_FEATURE_MMU); set_feature(env, RISCV_FEATURE_PMP); @@ -148,7 +147,7 @@ static void rv32imacu_nommu_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); - set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); set_feature(env, RISCV_FEATURE_PMP); } @@ -166,7 +165,7 @@ static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1); + set_priv_version(env, PRIV_VERSION_1_09_1); set_resetvec(env, DEFAULT_RSTVEC); set_feature(env, RISCV_FEATURE_MMU); set_feature(env, RISCV_FEATURE_PMP); @@ -176,7 +175,7 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); set_feature(env, RISCV_FEATURE_MMU); set_feature(env, RISCV_FEATURE_PMP); @@ -186,7 +185,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); - set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); set_feature(env, RISCV_FEATURE_PMP); } @@ -317,7 +316,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); int priv_version = PRIV_VERSION_1_11_0; - int user_version = USER_VERSION_2_02_0; target_ulong target_misa = 0; Error *local_err = NULL; @@ -342,18 +340,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (cpu->cfg.user_spec) { - if (!g_strcmp0(cpu->cfg.user_spec, "v2.02.0")) { - user_version = USER_VERSION_2_02_0; - } else { - error_setg(errp, - "Unsupported user spec version '%s'", - cpu->cfg.user_spec); - return; - } - } - - set_versions(env, user_version, priv_version); + set_priv_version(env, priv_version); set_resetvec(env, DEFAULT_RSTVEC); if (cpu->cfg.mmu) { @@ -454,7 +441,6 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("user_spec", RISCVCPU, cfg.user_spec), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d559d28bcda8..0855277b92d4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -78,7 +78,6 @@ enum { RISCV_FEATURE_MISA }; -#define USER_VERSION_2_02_0 0x00020200 #define PRIV_VERSION_1_09_1 0x00010901 #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 @@ -105,7 +104,6 @@ struct CPURISCVState { target_ulong badaddr; - target_ulong user_ver; target_ulong priv_ver; target_ulong misa; target_ulong misa_mask; From patchwork Thu Jun 27 15:19:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123474 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPGq0PRcz9sLt for ; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id e4sm3143729pfi.35.2019.06.27.08.24.10 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:10 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:57 -0700 Message-Id: <20190627152011.18686-21-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.193 Subject: [Qemu-devel] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Add support for disabling/enabling the "Counters" extension. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/csr.c | 17 ++++++++++++----- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a54ebf10c62..be90fa7d0808 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -440,6 +440,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0855277b92d4..4d4e0f89e206 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -222,6 +222,7 @@ typedef struct RISCVCPU { bool ext_c; bool ext_s; bool ext_u; + bool ext_counters; char *priv_spec; char *user_spec; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 448162e484a3..de67741f3648 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -56,17 +56,24 @@ static int fs(CPURISCVState *env, int csrno) static int ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) + CPUState *cs = env_cpu(env); + RISCVCPU *cpu = RISCV_CPU(cs); + uint32_t ctr_en = ~0u; + + if (!cpu->cfg.ext_counters) { + /* The Counters extensions is not enabled */ + return -1; + } + /* - * The counters are always enabled on newer priv specs, as the CSR has - * changed from controlling that the counters can be read to controlling - * that the counters increment. + * The counters are always enabled at run time on newer priv specs, as the + * CSR has changed from controlling that the counters can be read to + * controlling that the counters increment. */ if (env->priv_ver > PRIV_VERSION_1_09_1) { return 0; } - uint32_t ctr_en = ~0u; - if (env->priv < PRV_M) { ctr_en &= env->mcounteren; } From patchwork Thu Jun 27 15:19:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123490 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPcz17v6z9s3l for ; Fri, 28 Jun 2019 01:55:47 +1000 (AEST) Received: from localhost ([::1]:52000 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWkT-0004en-7A for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:55:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33263) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHh-0003JE-TC for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHe-0000JG-9M for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:00 -0400 Received: from mail-pl1-f175.google.com ([209.85.214.175]:43194) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHd-000758-Rf for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:58 -0400 Received: by mail-pl1-f175.google.com with SMTP id cl9so1477225plb.10 for ; Thu, 27 Jun 2019 08:24:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=NIyWvQXIInPHkbPMAYxhV18GTR99MjAgFa+NcGYzhSA=; b=nLi/t9SbRwoRwV7d4GQxmWjSjdICOL77o7lm88ucBhz5WVOg9ESW5APIOsTWE8K1fX E2kr6jRf3bCVQ4V8Rv1zqFAgczd7QPdxP07MOFLjGTP5N4m/G977Ideeolz6Q0SsLYlm FE/AugcQBdTK8aRjtNYrBnXtc297mquY1u2hEDdXEdPnLsLjcIgkJLz/fQ1NLnTldaAX ScN0/uvKneSbbmIH2cpDzadtB+mCyU/WPAoQD83DEHIo+wVbUDMtJ93SZ0NhmpaC5YJL PWFQBaOJDQ7dRqIz+1z6Zp/y48YoxNYmaiYQQEcXfn4aVbDf3Tkzv2YTy9jdHQQal6LH 7zhg== X-Gm-Message-State: APjAAAWJVW24qcKsDA8j4Rpqw3HbF025vUMADdoKBNBWzaxOWzr00aOi 1+9E5Al7dcQgR/dXZlhK2Svaiw== X-Google-Smtp-Source: APXvYqyi3rn8zrtd2Z0uYr+mkuIokMLDTPl1fr1eT2EsA1ZtcmCbhAsa1L/p0Spok4JtIQPhLNvGDg== X-Received: by 2002:a17:902:2f84:: with SMTP id t4mr5429590plb.57.1561649053705; Thu, 27 Jun 2019 08:24:13 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id w18sm4578420pfj.37.2019.06.27.08.24.12 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:13 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:58 -0700 Message-Id: <20190627152011.18686-22-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.175 Subject: [Qemu-devel] [PULL 21/34] RISC-V: Add support for the Zifencei extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_rvi.inc.c | 4 ++++ target/riscv/translate.c | 3 +++ 4 files changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index be90fa7d0808..bbad39a337b3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -441,6 +441,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d4e0f89e206..ba551cd3082c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -223,6 +223,7 @@ typedef struct RISCVCPU { bool ext_s; bool ext_u; bool ext_counters; + bool ext_ifencei; char *priv_spec; char *user_spec; diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 6cda078ed6ba..ea6473111ce8 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -484,6 +484,10 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a) static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) { + if (!ctx->ext_ifencei) { + return false; + } + /* * FENCE_I is a no-op in QEMU, * however we need to end the translation block diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 313c27b70073..8d6ab732588d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -54,6 +54,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; + bool ext_ifencei; } DisasContext; #ifdef TARGET_RISCV64 @@ -752,6 +753,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPURISCVState *env = cs->env_ptr; + RISCVCPU *cpu = RISCV_CPU(cs); ctx->pc_succ_insn = ctx->base.pc_first; ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; @@ -759,6 +761,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->priv_ver = env->priv_ver; ctx->misa = env->misa; ctx->frm = -1; /* unknown rounding mode */ + ctx->ext_ifencei = cpu->cfg.ext_ifencei; } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) From patchwork Thu Jun 27 15:19:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id e188sm4126519pfh.99.2019.06.27.08.24.15 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:15 -0700 (PDT) Date: Thu, 27 Jun 2019 08:19:59 -0700 Message-Id: <20190627152011.18686-23-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.177 Subject: [Qemu-devel] [PULL 22/34] RISC-V: Add support for the Zicsr extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The various CSR instructions have been split out of the base ISA as part of the ratification process. This patch adds a Zicsr argument, which disables all the CSR instructions. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/csr.c | 6 ++++++ 3 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bbad39a337b3..915b9e77df33 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), + DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ba551cd3082c..0adb307f3298 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -224,6 +224,7 @@ typedef struct RISCVCPU { bool ext_u; bool ext_counters; bool ext_ifencei; + bool ext_icsr; char *priv_spec; char *user_spec; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index de67741f3648..e0d45867607a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -793,6 +793,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, { int ret; target_ulong old_value; + RISCVCPU *cpu = env_archcpu(env); /* check privileges and return -1 if check fails */ #if !defined(CONFIG_USER_ONLY) @@ -803,6 +804,11 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, } #endif + /* ensure the CSR extension is enabled. */ + if (!cpu->cfg.ext_icsr) { + return -1; + } + /* check predicate */ if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { return -1; From patchwork Thu Jun 27 15:20:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123483 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPWm53ljz9s3l for ; Fri, 28 Jun 2019 01:51:16 +1000 (AEST) Received: from localhost ([::1]:51946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWg6-0008U2-GK for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:51:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33149) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHb-0003Dp-Fk for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHX-00008t-4n for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:53 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:35083) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHW-00078D-O4 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:50 -0400 Received: by mail-pf1-f193.google.com with SMTP id d126so1410540pfd.2 for ; Thu, 27 Jun 2019 08:24:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=/utRw/o8PW3YQm+ZhJWNBeL8gDnPNYLiS6dXiDJvvqI=; b=m72LBMRtuLmuX9CBY+jIZRk0OMroSCe4OmEM1N9pLL/13qL/PJbOXuZaCCyeI4XYK4 zuBDmfJACxfdCOZXT5iFFAK9ptgJUwPz8jY+LIF+0un/tT7ugkgmI5+7Z9abqItE0e2w fucwJQ6y2kIpsNKT11yKK7j5qd+TmwMcaE2DR+BiIQa6RuR4BnH0k3o0BhXjuLUdzN5O i1kfgXnaBIv/BIRpdvvB6Kq5y2iXwkgyMcGleDYkz1GpxFf1Pv2Y14Gy1GkhEzsRyMGr /98+uyDkCE9iv1kFTrdizn5DC+bc+b2WqHYqZTEMUhiBi67mNSrqCfGvTub56R4w/buI 4N+A== X-Gm-Message-State: APjAAAVWQ4ZekoSuStZjR5jWJtkwZasvgFK1DxDRNbwCFmprJAejoD6T Kg7GwxjZqv1yYSjCcm9TjS0rzg== X-Google-Smtp-Source: APXvYqwqMNKPZN0oG/XToM+BO4sKOn/5VD2//Xh6ky/uOvwnVSrI8PIxKIsCGc8JOz/LwDQrOkeiGg== X-Received: by 2002:a17:90a:634a:: with SMTP id v10mr6872490pjs.16.1561649058777; Thu, 27 Jun 2019 08:24:18 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id p2sm5388157pfb.118.2019.06.27.08.24.18 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:18 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:00 -0700 Message-Id: <20190627152011.18686-24-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.193 Subject: [Qemu-devel] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Joel Sing , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Joel Sing This prevents a load reservation from being placed in one context/process, then being used in another, resulting in an SC succeeding incorrectly and breaking atomics. Signed-off-by: Joel Sing Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 1 + target/riscv/cpu_helper.c | 10 ++++++++++ target/riscv/insn_trans/trans_rva.inc.c | 8 +++++++- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 915b9e77df33..f8d07bd20ad7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -297,6 +297,7 @@ static void riscv_cpu_reset(CPUState *cs) env->pc = env->resetvec; #endif cs->exception_index = EXCP_NONE; + env->load_res = -1; set_default_nan_mode(1, &env->fp_status); } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1b079e69c60..e32b6126af05 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -132,6 +132,16 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) } /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv = newpriv; + + /* + * Clear the load reservation - otherwise a reservation placed in one + * context/process can be used by another, resulting in an SC succeeding + * incorrectly. Version 2.2 of the ISA specification explicitly requires + * this behaviour, while later revisions say that the kernel "should" use + * an SC instruction to force the yielding of a load reservation on a + * preemptive context switch. As a result, do both. + */ + env->load_res = -1; } /* get_physical_address - get the physical address for this virtual address diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c index f6dbbc065e15..fadd88849e2b 100644 --- a/target/riscv/insn_trans/trans_rva.inc.c +++ b/target/riscv/insn_trans/trans_rva.inc.c @@ -61,7 +61,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop) gen_set_label(l1); /* - * Address comparion failure. However, we still need to + * Address comparison failure. However, we still need to * provide the memory barrier implied by AQ/RL. */ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL); @@ -69,6 +69,12 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop) gen_set_gpr(a->rd, dat); gen_set_label(l2); + /* + * Clear the load reservation, since an SC must fail if there is + * an SC to any address, in between an LR and SC pair. + */ + tcg_gen_movi_tl(load_res, -1); + tcg_temp_free(dat); tcg_temp_free(src1); tcg_temp_free(src2); From patchwork Thu Jun 27 15:20:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123500 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPx06G2tz9s4Y for ; Fri, 28 Jun 2019 02:09:40 +1000 (AEST) Received: from localhost ([::1]:52100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWxu-0002U8-Es for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 12:09:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33259) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHh-0003JB-RM for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHe-0000JV-EN for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:00 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:35090) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHd-0007A1-U1 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:58 -0400 Received: by mail-pf1-f196.google.com with SMTP id d126so1410584pfd.2 for ; Thu, 27 Jun 2019 08:24:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=MsITP9g02yPdJ/4apRI29XJbL0BqwsUIcjd2jJ0cnTY=; b=TVcCpaHstW0vyrdVcXrPpPPdbehby1k1xLaQDjuJvy3Wjp+/wS9pPFVGJR1ZuDVC7h /1o0uxgWyafiYrLfBtl/I0gAjZEpKJlZ5iLm7LIf2NEhjSFPlsmXarlBghMFpBdjdEar HMXHajA5xDwKTAWVVBLQ1uybujRs3n3IMBKQxjmu7Ng3CTREPPBpg3EpIPVD+rAMo99R IFNOlrFLt0YTKdVEpshhkodRkn1BX+tVnGEHSdMDTe6GOcJp5yLU9chGimq1DBIcAfj1 eK884niMrI8clWtpLpTMd9pFSl+7fHFBvC9jdZkTwqMJT3MYPJleqD38gC2ZANSkikkX TwBQ== X-Gm-Message-State: APjAAAW16721WTptRRO4c9TKsije+eacsMI5kC8p4bmuL5GBA7jgNUym D1+6dCu8TNRIpv3mjHJs2BfilUd1U/kbWA== X-Google-Smtp-Source: APXvYqwP3X0J8lWjIMxxmjd7unuQEoMoZbWww3FjeBzFoPZmdGngKnGlZcGK9un87W8Y8mo+4XkOCQ== X-Received: by 2002:a17:90a:b011:: with SMTP id x17mr6764327pjq.113.1561649060874; Thu, 27 Jun 2019 08:24:20 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id q10sm2309063pgg.35.2019.06.27.08.24.20 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:20 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:01 -0700 Message-Id: <20190627152011.18686-25-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.196 Subject: [Qemu-devel] [PULL 24/34] RISC-V: Update syscall list for 32-bit support. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Jim Wilson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Jim Wilson 32-bit RISC-V uses _llseek instead of lseek as syscall number 62. Update syscall list from open-embedded build, primarily because 32-bit RISC-V requires statx support. Tested with cross gcc testsuite runs for rv32 and rv64, with the pending statx patch also applied. Signed-off-by: Jim Wilson Reviewed-by: Laurent Vivier Signed-off-by: Palmer Dabbelt --- linux-user/riscv/syscall_nr.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/linux-user/riscv/syscall_nr.h b/linux-user/riscv/syscall_nr.h index dab6509e3ade..5c8728220994 100644 --- a/linux-user/riscv/syscall_nr.h +++ b/linux-user/riscv/syscall_nr.h @@ -72,7 +72,11 @@ #define TARGET_NR_pipe2 59 #define TARGET_NR_quotactl 60 #define TARGET_NR_getdents64 61 +#ifdef TARGET_RISCV32 +#define TARGET_NR__llseek 62 +#else #define TARGET_NR_lseek 62 +#endif #define TARGET_NR_read 63 #define TARGET_NR_write 64 #define TARGET_NR_readv 65 @@ -286,7 +290,16 @@ #define TARGET_NR_membarrier 283 #define TARGET_NR_mlock2 284 #define TARGET_NR_copy_file_range 285 +#define TARGET_NR_preadv2 286 +#define TARGET_NR_pwritev2 287 +#define TARGET_NR_pkey_mprotect 288 +#define TARGET_NR_pkey_alloc 289 +#define TARGET_NR_pkey_free 290 +#define TARGET_NR_statx 291 +#define TARGET_NR_io_pgetevents 292 +#define TARGET_NR_rseq 293 +#define TARGET_NR_kexec_file_load 294 -#define TARGET_NR_syscalls (TARGET_NR_copy_file_range + 1) +#define TARGET_NR_syscalls (TARGET_NR_kexec_file_load + 1) #endif From patchwork Thu Jun 27 15:20:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123469 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZP894Nqmz9sLt for ; Fri, 28 Jun 2019 01:34:17 +1000 (AEST) Received: from localhost ([::1]:51776 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWPc-0001BH-SZ for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:34:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60817) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWGc-0001kz-K5 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWGZ-0007cG-Ul for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:54 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:39638) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWGY-0007Bn-Ly for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:24:50 -0400 Received: by mail-pg1-f193.google.com with SMTP id 196so1176193pgc.6 for ; Thu, 27 Jun 2019 08:24:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=8AbRazPuGbBA4/wcOJ0NXPkCs6Kyha3rsVtogdXoPZc=; b=T1Fec8Wcme9ueq082nIQxWHahovbYLh1URkJuOG3K4ekH4bbBMduvGh5WKTgKdXK3N B5407q+QzYNX17Illxe0lRZRfD8rXV63x39Y8kADcBZRQ4AfqLG9Ilb3TcfkYxFK6TkL U9Ab5ShExXf+2WW0oVD0pXmdi7T6ncgH6/OKuFDE2DDZpwkFRIN9NERBYUerHYLMgKxY 3ZzadHnQsBWu04xxhRkTBq3xd+arQDmZvONQz9kpR52NnIeQW0Ov+4WfRBHAnXxClY3D iOkVmvXswB4fnTp9wO4Wuu9GDaCvzGxqO24oty8ATNJviXizqn/eMiOei6COdJ3KhFW1 DsZQ== X-Gm-Message-State: APjAAAXZYHc/I57GD1cJ5DROCbnBChhVcsDaABfHYObvnLT5DY2tV8yI /LgNSYZ/OScaSmidbfIX097euw== X-Google-Smtp-Source: APXvYqzmdMaz0BLAinf0AXmX0ZIlx452q1OeoLFnWvHmGVotYU/yHg4yZbyX8mN3LRVilS39kkGv6A== X-Received: by 2002:a63:3f48:: with SMTP id m69mr4214170pga.17.1561649063184; Thu, 27 Jun 2019 08:24:23 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id t29sm4262679pfq.156.2019.06.27.08.24.22 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:22 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:02 -0700 Message-Id: <20190627152011.18686-26-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.193 Subject: [Qemu-devel] [PULL 25/34] riscv: virt: Add cpu-topology DT node. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Atish Patra Currently, there is no cpu topology defined in RISC-V. Define a device tree node that clearly describes the entire topology. This saves the trouble of scanning individual cache to figure out the topology. Here is the linux kernel patch series that enables topology for RISC-V. http://lists.infradead.org/pipermail/linux-riscv/2019-June/005072.html CPU topology after applying this patch in QEMU & above series in kernel / # cat /sys/devices/system/cpu/cpu2/topology/thread_siblings_list 2 / # cat /sys/devices/system/cpu/cpu2/topology/physical_package_id 0 / # cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list 0-7 Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 487f61404b21..28d96daf8c5b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -191,6 +191,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { int cpu_phandle = phandle++; + int intc_phandle; nodename = g_strdup_printf("/cpus/cpu@%d", cpu); char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); char *isa = riscv_isa_string(&s->soc.harts[cpu]); @@ -203,9 +204,12 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle); + intc_phandle = phandle++; qemu_fdt_add_subnode(fdt, intc); - qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle); + qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle); + qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); @@ -214,6 +218,20 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, g_free(nodename); } + /* Add cpu-topology node */ + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0"); + for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { + char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d", + cpu); + char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu); + uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename); + qemu_fdt_add_subnode(fdt, core_nodename); + qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle); + g_free(core_nodename); + g_free(cpu_nodename); + } + cells = g_new0(uint32_t, s->soc.num_harts * 4); for (cpu = 0; cpu < s->soc.num_harts; cpu++) { nodename = From patchwork Thu Jun 27 15:20:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123481 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id i1sm7282477pjt.3.2019.06.27.08.24.25 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:25 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:03 -0700 Message-Id: <20190627152011.18686-27-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.194 Subject: [Qemu-devel] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Michael Clark , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Michael Clark Due to the design of the disassembler, the immediate is not known during decoding of the opcode; so to handle compressed encodings with reserved immediate values (non-zero), we need to add an additional check during decompression to match reserved encodings with zero immediates and translate them into the illegal instruction. The following compressed opcodes have reserved encodings with zero immediates: c.addi4spn, c.addi, c.lui, c.addi16sp, c.srli, c.srai, c.andi and c.slli Signed-off-by: Michael Clark Signed-off-by: Alistair Francis [Palmer: Broke long lines] Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- disas/riscv.c | 62 +++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 45 insertions(+), 17 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 59a9b0437a5f..d37312705516 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -504,14 +504,19 @@ typedef struct { const rvc_constraint *constraints; } rv_comp_data; +enum { + rvcd_imm_nz = 0x1 +}; + typedef struct { const char * const name; const rv_codec codec; const char * const format; const rv_comp_data *pseudo; - const int decomp_rv32; - const int decomp_rv64; - const int decomp_rv128; + const short decomp_rv32; + const short decomp_rv64; + const short decomp_rv128; + const short decomp_data; } rv_opcode_data; /* register names */ @@ -1011,7 +1016,8 @@ const rv_opcode_data opcode_data[] = { { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, - { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, + { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, + rv_op_addi, rv_op_addi, rvcd_imm_nz }, { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 }, { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw }, { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, @@ -1019,14 +1025,20 @@ const rv_opcode_data opcode_data[] = { { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw }, { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, - { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, + { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, + rv_op_addi, rvcd_imm_nz }, { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 }, { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, - { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, - { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, rv_op_lui }, - { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli }, - { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai }, - { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi }, + { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, + rv_op_addi, rv_op_addi, rvcd_imm_nz }, + { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, + rv_op_lui, rvcd_imm_nz }, + { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, + rv_op_srli, rv_op_srli, rvcd_imm_nz }, + { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, + rv_op_srai, rv_op_srai, rvcd_imm_nz }, + { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, + rv_op_andi, rv_op_andi, rvcd_imm_nz }, { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub }, { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor }, { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or }, @@ -1036,7 +1048,8 @@ const rv_opcode_data opcode_data[] = { { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal }, { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq }, { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne }, - { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, rv_op_slli, rv_op_slli }, + { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, + rv_op_slli, rv_op_slli, rvcd_imm_nz }, { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld }, { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw }, { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, @@ -2795,8 +2808,13 @@ static void decode_inst_decompress_rv32(rv_decode *dec) { int decomp_op = opcode_data[dec->op].decomp_rv32; if (decomp_op != rv_op_illegal) { - dec->op = decomp_op; - dec->codec = opcode_data[decomp_op].codec; + if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) + && dec->imm == 0) { + dec->op = rv_op_illegal; + } else { + dec->op = decomp_op; + dec->codec = opcode_data[decomp_op].codec; + } } } @@ -2804,8 +2822,13 @@ static void decode_inst_decompress_rv64(rv_decode *dec) { int decomp_op = opcode_data[dec->op].decomp_rv64; if (decomp_op != rv_op_illegal) { - dec->op = decomp_op; - dec->codec = opcode_data[decomp_op].codec; + if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) + && dec->imm == 0) { + dec->op = rv_op_illegal; + } else { + dec->op = decomp_op; + dec->codec = opcode_data[decomp_op].codec; + } } } @@ -2813,8 +2836,13 @@ static void decode_inst_decompress_rv128(rv_decode *dec) { int decomp_op = opcode_data[dec->op].decomp_rv128; if (decomp_op != rv_op_illegal) { - dec->op = decomp_op; - dec->codec = opcode_data[decomp_op].codec; + if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) + && dec->imm == 0) { + dec->op = rv_op_illegal; + } else { + dec->op = decomp_op; + dec->codec = opcode_data[decomp_op].codec; + } } } From patchwork Thu Jun 27 15:20:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123501 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPyW1VGbz9s4Y for ; Fri, 28 Jun 2019 02:10:59 +1000 (AEST) Received: from localhost ([::1]:52116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWzB-0003yu-9u for incoming@patchwork.ozlabs.org; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id k3sm2637153pgo.81.2019.06.27.08.24.27 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:27 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:04 -0700 Message-Id: <20190627152011.18686-28-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.194 Subject: [Qemu-devel] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Wladimir J. van der Laan" , Palmer Dabbelt , qemu-devel@nongnu.org, Michael Clark , Alistair Francis , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Wladimir J. van der Laan" The constraint for `rdinstreth` was comparing the csr number to 0xc80, which is `cycleh` instead. Fix this. Signed-off-by: Wladimir J. van der Laan Signed-off-by: Michael Clark Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- disas/riscv.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index d37312705516..278d9be9247e 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -614,7 +614,8 @@ static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, r static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end }; static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end }; static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end }; -static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end }; +static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, + rvc_csr_eq_0xc82, rvc_end }; static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end }; static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end }; static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end }; @@ -1038,7 +1039,7 @@ const rv_opcode_data opcode_data[] = { { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai, rvcd_imm_nz }, { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, - rv_op_andi, rv_op_andi, rvcd_imm_nz }, + rv_op_andi, rv_op_andi }, { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub }, { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor }, { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or }, From patchwork Thu Jun 27 15:20:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123493 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPhn0Swsz9sLt for ; Fri, 28 Jun 2019 01:59:05 +1000 (AEST) Received: from localhost ([::1]:52020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWnf-0001fN-5F for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:59:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33116) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHa-0003Dm-Gn for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHW-00008U-Uy for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:53 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:40614) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHW-0007Jn-HL for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:50 -0400 Received: by mail-pf1-f194.google.com with SMTP id p184so1402697pfp.7 for ; Thu, 27 Jun 2019 08:24:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=KdUinYphzGQDVuTLX+/ZSu8nDN42cj53AMC4AE9KtVs=; b=uRKlI+4f+r+h6LPdELFbC28BKzZRjebc6Q8rocdc6jWBIDFx99Uj/gqxc9mOvUdGMh WHqAhX8zqDiTJnjDmZDjlStgWlQVIkEmXSuIaCF66c297FUPXd1g3rE8mnnFh6QwnDS9 Mu318vCkDwsm7o1pM7iwr7g338q4PUo1aupo12kEpXR0C8sItJjrEAs7ud/BCwCYE9z7 HqbYxtvRxlPIt5dA0lJl4LlYKadKVnvYKFHVQcKMl4WBsHn8D0fe1MkF9NsK0UTU3VHc m0T4TQ29olBD31QCyaspTLQmcyQHdPnlU3khscJ6r3wVuZQ/pnLteVodg2mSAD74TTnw ig9Q== X-Gm-Message-State: APjAAAVOE6ciG0IMLS/TIansHzfqwx5hhtnTsAYNWPqx4bNiD8iWh1lu 2XlTgkP5bxCLS/NMbihcb1s6hg== X-Google-Smtp-Source: APXvYqyGxX5moljggF5ozAHX52vpD4fFQ5y2J4e7tXcErYTzW55922HaNG1n3SoPDeWJ0a+jJ4eLeA== X-Received: by 2002:a63:58c:: with SMTP id 134mr1395499pgf.106.1561649071910; Thu, 27 Jun 2019 08:24:31 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id d9sm2374315pgj.34.2019.06.27.08.24.30 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:31 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:05 -0700 Message-Id: <20190627152011.18686-29-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.194 Subject: [Qemu-devel] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present the cpu, plic and ethclk nodes' phandles are hard-coded to 1/2/3 in DT. If we configure more than 1 cpu for the machine, all cpu nodes' phandles conflict with each other as they are all 1. Fix it by removing the hardcode. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 5ecc47cea35d..e2120ac7a5d3 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -86,7 +86,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, uint32_t *cells; char *nodename; char ethclk_names[] = "pclk\0hclk\0tx_clk"; - uint32_t plic_phandle, ethclk_phandle; + uint32_t plic_phandle, ethclk_phandle, phandle = 1; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -121,6 +121,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { + int cpu_phandle = phandle++; nodename = g_strdup_printf("/cpus/cpu@%d", cpu); char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); @@ -134,8 +135,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); qemu_fdt_add_subnode(fdt, intc); - qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1); + qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); + qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); @@ -167,6 +168,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); + plic_phandle = phandle++; cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { nodename = @@ -192,20 +194,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); - qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2); - qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2); + qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); + ethclk_phandle = phandle++; nodename = g_strdup_printf("/soc/ethclk"); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_GEM_CLOCK_FREQ); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", 3); - qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", 3); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle); ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(nodename); From patchwork Thu Jun 27 15:20:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123489 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPch4Wqpz9sLt for ; Fri, 28 Jun 2019 01:55:32 +1000 (AEST) Received: from localhost ([::1]:51994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWkE-0004KC-I9 for incoming@patchwork.ozlabs.org; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id q144sm4013593pfc.103.2019.06.27.08.24.33 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:33 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:06 -0700 Message-Id: <20190627152011.18686-30-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.193 Subject: [Qemu-devel] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present the PLIC is instantiated to support only one hart, while the machine allows at most 4 harts to be created. When more than 1 hart is configured, PLIC needs to instantiated to support multicore, otherwise an SMP OS does not work. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index e2120ac7a5d3..a416d5d08b4d 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -344,6 +344,8 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) MemoryRegion *system_memory = get_system_memory(); MemoryRegion *mask_rom = g_new(MemoryRegion, 1); qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; + char *plic_hart_config; + size_t plic_hart_config_len; int i; Error *err = NULL; NICInfo *nd = &nd_table[0]; @@ -357,9 +359,21 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, mask_rom); + /* create PLIC hart topology configuration string */ + plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * smp_cpus; + plic_hart_config = g_malloc0(plic_hart_config_len); + for (i = 0; i < smp_cpus; i++) { + if (i != 0) { + strncat(plic_hart_config, ",", plic_hart_config_len); + } + strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG, + plic_hart_config_len); + plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); + } + /* MMIO */ s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, - (char *)SIFIVE_U_PLIC_HART_CONFIG, + plic_hart_config, SIFIVE_U_PLIC_NUM_SOURCES, SIFIVE_U_PLIC_NUM_PRIORITIES, SIFIVE_U_PLIC_PRIORITY_BASE, From patchwork Thu Jun 27 15:20:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123470 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZP9L0jGrz9s3l for ; Fri, 28 Jun 2019 01:35:17 +1000 (AEST) Received: from localhost ([::1]:51786 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWQd-0002hV-6Z for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:35:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60912) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWGn-0001p1-5q for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWGj-0007mQ-Hl for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:04 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:43086) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWGh-0007NI-8A for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:00 -0400 Received: by mail-pg1-f194.google.com with SMTP id f25so1168674pgv.10 for ; Thu, 27 Jun 2019 08:24:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=AjHoyr0UySwycrqVbGqhPd/G36L+Az+7aEEjVYksGCg=; b=j1iDCz+S6YCJSyo/SkwrlyeeOwb7+ilchNkr0fU0xpe4EPZJ/NMqFHTcHw80rU2N7r VDS8NKYH1P09bNdf1CKnQtrFZlqcPOzN5IA670OiWkpbn9h8r4+dqCqgUU7Q0ui5R/LY zkmHzly+/FDvaMkQGh0dHPk/y2es8mpp0Z1QZ4tZZwmL3/C4MZxXW+Oua5vebJ1eXQg2 kh3rOb0vkynfJ8RPTidoi6z7VgFRL1nHta6QfW3Yei/816JdQisGcAfH8LTYb4/6cAOo OGseus6i5DVkuGPRAYsw7xtN5AkDHdMQTOr2LoeQChITcYLHvMsXBvGHPjD/PJNwwyUS aVMQ== X-Gm-Message-State: APjAAAU2cDQc8j/1ZEP2Dmpxvx99LI9dhyZhywOfWkhOOE0LV0A0lI0X BfR63n2s6uu/JcONFdmBszyvKQ== X-Google-Smtp-Source: APXvYqxsI4LGENnkg5LVnu2MLhFJH2kqk+wWwIKrxB20ZTCAugiZfap9XF2kRdnI0AvEWN65BiXYyg== X-Received: by 2002:a65:538d:: with SMTP id x13mr4355737pgq.190.1561649076935; Thu, 27 Jun 2019 08:24:36 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id e4sm3144669pfi.35.2019.06.27.08.24.36 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:36 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:07 -0700 Message-Id: <20190627152011.18686-31-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.194 Subject: [Qemu-devel] [PULL 30/34] hw/riscv: Split out the boot functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Split the common RISC-V boot functions into a seperate file. This allows us to share the common code. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/Makefile.objs | 1 + hw/riscv/boot.c | 69 +++++++++++++++++++++++++++++++++++++++++ hw/riscv/sifive_e.c | 17 ++-------- hw/riscv/sifive_u.c | 17 ++-------- hw/riscv/spike.c | 21 +++---------- hw/riscv/virt.c | 51 +++--------------------------- include/hw/riscv/boot.h | 27 ++++++++++++++++ 7 files changed, 110 insertions(+), 93 deletions(-) create mode 100644 hw/riscv/boot.c create mode 100644 include/hw/riscv/boot.h diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index a65027304a2c..eb9d4f9ffc9e 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -1,3 +1,4 @@ +obj-y += boot.o obj-$(CONFIG_SPIKE) += riscv_htif.o obj-$(CONFIG_HART) += riscv_hart.o obj-$(CONFIG_SIFIVE_E) += sifive_e.o diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c new file mode 100644 index 000000000000..0c8e72e455d7 --- /dev/null +++ b/hw/riscv/boot.c @@ -0,0 +1,69 @@ +/* + * QEMU RISC-V Boot Helper + * + * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Alistair Francis + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "exec/cpu-defs.h" +#include "hw/loader.h" +#include "hw/riscv/boot.h" +#include "elf.h" + +target_ulong riscv_load_kernel(const char *kernel_filename) +{ + uint64_t kernel_entry, kernel_high; + + if (load_elf(kernel_filename, NULL, NULL, NULL, + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) < 0) { + error_report("could not load kernel '%s'", kernel_filename); + exit(1); + } + + return kernel_entry; +} + +hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, + uint64_t kernel_entry, hwaddr *start) +{ + int size; + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size = load_ramdisk(filename, *start, mem_size - *start); + if (size == -1) { + size = load_image_targphys(filename, *start, mem_size - *start); + if (size == -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + return *start + size; +} diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index a5b4086da36d..d27f626529fe 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -44,10 +44,10 @@ #include "hw/riscv/sifive_prci.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" +#include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "exec/address-spaces.h" -#include "elf.h" static const struct MemmapEntry { hwaddr base; @@ -74,19 +74,6 @@ static const struct MemmapEntry { [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } }; -static target_ulong load_kernel(const char *kernel_filename) -{ - uint64_t kernel_entry, kernel_high; - - if (load_elf(kernel_filename, NULL, NULL, NULL, - &kernel_entry, NULL, &kernel_high, - 0, EM_RISCV, 1, 0) < 0) { - error_report("could not load kernel '%s'", kernel_filename); - exit(1); - } - return kernel_entry; -} - static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, uintptr_t offset, uintptr_t length) { @@ -131,7 +118,7 @@ static void riscv_sifive_e_init(MachineState *machine) memmap[SIFIVE_E_MROM].base, &address_space_memory); if (machine->kernel_filename) { - load_kernel(machine->kernel_filename); + riscv_load_kernel(machine->kernel_filename); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a416d5d08b4d..f6b9c12e6094 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -41,11 +41,11 @@ #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_prci.h" #include "hw/riscv/sifive_u.h" +#include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "exec/address-spaces.h" -#include "elf.h" #include @@ -65,19 +65,6 @@ static const struct MemmapEntry { #define GEM_REVISION 0x10070109 -static target_ulong load_kernel(const char *kernel_filename) -{ - uint64_t kernel_entry, kernel_high; - - if (load_elf(kernel_filename, NULL, NULL, NULL, - &kernel_entry, NULL, &kernel_high, - 0, EM_RISCV, 1, 0) < 0) { - error_report("could not load kernel '%s'", kernel_filename); - exit(1); - } - return kernel_entry; -} - static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { @@ -283,7 +270,7 @@ static void riscv_sifive_u_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); if (machine->kernel_filename) { - load_kernel(machine->kernel_filename); + riscv_load_kernel(machine->kernel_filename); } /* reset vector */ diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 5b33d4be3bbc..e68be00a5fe8 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -36,12 +36,12 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_clint.h" #include "hw/riscv/spike.h" +#include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "sysemu/qtest.h" #include "exec/address-spaces.h" -#include "elf.h" #include @@ -54,19 +54,6 @@ static const struct MemmapEntry { [SPIKE_DRAM] = { 0x80000000, 0x0 }, }; -static target_ulong load_kernel(const char *kernel_filename) -{ - uint64_t kernel_entry, kernel_high; - - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, - &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0, - NULL, true, htif_symbol_callback) < 0) { - error_report("could not load kernel '%s'", kernel_filename); - exit(1); - } - return kernel_entry; -} - static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { @@ -199,7 +186,7 @@ static void spike_board_init(MachineState *machine) mask_rom); if (machine->kernel_filename) { - load_kernel(machine->kernel_filename); + riscv_load_kernel(machine->kernel_filename); } /* reset vector */ @@ -287,7 +274,7 @@ static void spike_v1_10_0_board_init(MachineState *machine) mask_rom); if (machine->kernel_filename) { - load_kernel(machine->kernel_filename); + riscv_load_kernel(machine->kernel_filename); } /* reset vector */ @@ -372,7 +359,7 @@ static void spike_v1_09_1_board_init(MachineState *machine) mask_rom); if (machine->kernel_filename) { - load_kernel(machine->kernel_filename); + riscv_load_kernel(machine->kernel_filename); } /* reset vector */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 28d96daf8c5b..485aefa99523 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -34,13 +34,13 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_test.h" #include "hw/riscv/virt.h" +#include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "exec/address-spaces.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" -#include "elf.h" #include @@ -61,47 +61,6 @@ static const struct MemmapEntry { [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, }; -static target_ulong load_kernel(const char *kernel_filename) -{ - uint64_t kernel_entry, kernel_high; - - if (load_elf(kernel_filename, NULL, NULL, NULL, - &kernel_entry, NULL, &kernel_high, - 0, EM_RISCV, 1, 0) < 0) { - error_report("could not load kernel '%s'", kernel_filename); - exit(1); - } - return kernel_entry; -} - -static hwaddr load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, hwaddr *start) -{ - int size; - - /* We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size = load_ramdisk(filename, *start, mem_size - *start); - if (size == -1) { - size = load_image_targphys(filename, *start, mem_size - *start); - if (size == -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - return *start + size; -} - static void create_pcie_irq_map(void *fdt, char *nodename, uint32_t plic_phandle) { @@ -440,13 +399,13 @@ static void riscv_virt_board_init(MachineState *machine) mask_rom); if (machine->kernel_filename) { - uint64_t kernel_entry = load_kernel(machine->kernel_filename); + uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); if (machine->initrd_filename) { hwaddr start; - hwaddr end = load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); + hwaddr end = riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h new file mode 100644 index 000000000000..f84fd6c2df5e --- /dev/null +++ b/include/hw/riscv/boot.h @@ -0,0 +1,27 @@ +/* + * QEMU RISC-V Boot Helper + * + * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Alistair Francis + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef RISCV_BOOT_H +#define RISCV_BOOT_H + +target_ulong riscv_load_kernel(const char *kernel_filename); +hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, + uint64_t kernel_entry, hwaddr *start); + +#endif /* RISCV_BOOT_H */ From patchwork Thu Jun 27 15:20:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZPdF5jxdz9s3l for ; Fri, 28 Jun 2019 01:56:01 +1000 (AEST) Received: from localhost ([::1]:52002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWkh-0005lq-SR for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 11:55:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33519) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHz-0003Wn-Vc for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHy-0000dr-AT for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:19 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:38321) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHy-0007PP-0V for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:18 -0400 Received: by mail-pg1-f194.google.com with SMTP id z75so1179911pgz.5 for ; Thu, 27 Jun 2019 08:24:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=e4LpAArqCMZjxsWg9gz2sRwwsdArZOrpMF0nx0rvwxQ=; b=hKwRMwXQ6K7x5O/6qXj57wDLQFmE9RD9RjZZMOlKuoxLsTrM6dOX4lUGtJ80olMKPJ 0BXWSyc7b7m4wSRWKrnxXo0lra583P5jAjgqURoQkdfrUlDwm72ornCNarrUXtAT6dW9 o2UiD0Cl0fcjQEGAGNDsQ2yEjAZsAtz/JvKE7wRaZXpyteSk6Nj4xUgyIx8lH8EHmLYr 8USC9QwS4OfSYOhp2sNZforonZM1d+f/U+JJqj2ZHaqTqZEg6bjIhXamOWCCGsoag0Vt icXT+fgev/s5z21EFAIm9v5kVgnpsilAaYSu/ARHAy5KUCHZWbR7FifDP1btuvCyFrmA 70rQ== X-Gm-Message-State: APjAAAWxRHDeXRjwDgH/1TTWljWcmPzk5ewtjVlEU0BoBYA3vqRDI2eA Bd3nHuHdlumREQK+XLG8yxc3Fg== X-Google-Smtp-Source: APXvYqzS4fXuAQgiD1T2BKjob0CchJ7MTjj7R/cWlOqcHh/t9hXv3QHR5RyjcllMlQMX/RZlOKvK3Q== X-Received: by 2002:a63:e018:: with SMTP id e24mr4241570pgh.361.1561649079447; Thu, 27 Jun 2019 08:24:39 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id q3sm2364742pgv.21.2019.06.27.08.24.38 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:39 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:08 -0700 Message-Id: <20190627152011.18686-32-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.194 Subject: [Qemu-devel] [PULL 31/34] hw/riscv: Add support for loading a firmware X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Add support for loading a firmware file for the virt machine and the SiFive U. This can be run with the following command: qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel vmlinux Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c | 26 ++++++++++++++++++++++++++ hw/riscv/sifive_u.c | 4 ++++ hw/riscv/virt.c | 4 ++++ include/hw/riscv/boot.h | 2 ++ 4 files changed, 36 insertions(+) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0c8e72e455d7..883df49a0c65 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -23,8 +23,34 @@ #include "exec/cpu-defs.h" #include "hw/loader.h" #include "hw/riscv/boot.h" +#include "hw/boards.h" #include "elf.h" +#if defined(TARGET_RISCV32) +# define KERNEL_BOOT_ADDRESS 0x80400000 +#else +# define KERNEL_BOOT_ADDRESS 0x80200000 +#endif + +target_ulong riscv_load_firmware(const char *firmware_filename, + hwaddr firmware_load_addr) +{ + uint64_t firmware_entry, firmware_start, firmware_end; + + if (load_elf(firmware_filename, NULL, NULL, NULL, &firmware_entry, + &firmware_start, &firmware_end, 0, EM_RISCV, 1, 0) > 0) { + return firmware_entry; + } + + if (load_image_targphys_as(firmware_filename, firmware_load_addr, + ram_size, NULL) > 0) { + return firmware_load_addr; + } + + error_report("could not load firmware '%s'", firmware_filename); + exit(1); +} + target_ulong riscv_load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index f6b9c12e6094..420867155293 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -269,6 +269,10 @@ static void riscv_sifive_u_init(MachineState *machine) /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + if (machine->firmware) { + riscv_load_firmware(machine->firmware, memmap[SIFIVE_U_DRAM].base); + } + if (machine->kernel_filename) { riscv_load_kernel(machine->kernel_filename); } diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 485aefa99523..d8181a4ff18a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -398,6 +398,10 @@ static void riscv_virt_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, mask_rom); + if (machine->firmware) { + riscv_load_firmware(machine->firmware, memmap[VIRT_DRAM].base); + } + if (machine->kernel_filename) { uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f84fd6c2df5e..daa179b600f4 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -20,6 +20,8 @@ #ifndef RISCV_BOOT_H #define RISCV_BOOT_H +target_ulong riscv_load_firmware(const char *firmware_filename, + hwaddr firmware_load_addr); target_ulong riscv_load_kernel(const char *kernel_filename); hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); From patchwork Thu Jun 27 15:20:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id f88sm6614731pjg.5.2019.06.27.08.24.41 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:41 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:09 -0700 Message-Id: <20190627152011.18686-33-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.194 Subject: [Qemu-devel] [PULL 32/34] hw/riscv: Extend the kernel loading support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Extend the RISC-V kernel loader to support Image and uImage files. A Linux kernel can now be booted with: qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel Image Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 883df49a0c65..ff023f42d01d 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -56,12 +56,22 @@ target_ulong riscv_load_kernel(const char *kernel_filename) uint64_t kernel_entry, kernel_high; if (load_elf(kernel_filename, NULL, NULL, NULL, - &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) < 0) { - error_report("could not load kernel '%s'", kernel_filename); - exit(1); + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) > 0) { + return kernel_entry; } - return kernel_entry; + if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, + NULL, NULL, NULL) > 0) { + return kernel_entry; + } + + if (load_image_targphys_as(kernel_filename, KERNEL_BOOT_ADDRESS, + ram_size, NULL) > 0) { + return KERNEL_BOOT_ADDRESS; + } + + error_report("could not load kernel '%s'", kernel_filename); + exit(1); } hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, From patchwork Thu Jun 27 15:20:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123503 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZQ1P4wX5z9s4Y for ; Fri, 28 Jun 2019 02:13:29 +1000 (AEST) Received: from localhost ([::1]:52146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgX1b-0006bs-DP for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 12:13:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33109) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgWHa-0003Dl-Fk for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:26:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgWHP-0008R2-MI for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:52 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:45128) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgWHK-0007VB-Rn for qemu-devel@nongnu.org; Thu, 27 Jun 2019 11:25:42 -0400 Received: by mail-pl1-f196.google.com with SMTP id bi6so1473467plb.12 for ; Thu, 27 Jun 2019 08:24:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=/AbKC3W967glqX7fEHe6XFcDjjA19hTCDxxWC3KIo84=; b=hyggX91Bxba2Eq83vhqy+5sH5h4Q2tQ8GlOZYiD2hc8YCYvmMgos4eneSKF4sj2zbZ Sd0WB4RsSkpO3GzjQwDKcjPjbxjTzAU7Qvzv6836b2kZuQPmoNrZoVcwiq7lFU6JN3zp WRkocM2rZJCsPgPaZuiTEU/u4+v7G8hbraJPs5PFx48RF5QXE0UW+ZjLSMAnKqSOXNsY 9866IBcBHtORF+xEIlwrvSK0dLvKb1RDGwbGBsts+Iwr5AbfHnStwRVWLIIltvn6heHT G0XsQrMvkBFXpZkj4AfUgVs9dVGZCcLzMG65hYKpqqB8iU8bUI8MKUSEtlN4emp1c3JM dbBw== X-Gm-Message-State: APjAAAUqGsXCRqeKdDgF6TxAINcCsm7NdnHaMGGE3emmE73PHYcWwkln BipGca8bjFZ2PuLGOZDXulzA1w== X-Google-Smtp-Source: APXvYqzA9pWj78wRoOiqDJ5lddtK0V+UXYRWaSZ2zUHPswaCA7Aanjltftk1nNbz+Tuaei9GxlpKCw== X-Received: by 2002:a17:902:f81:: with SMTP id 1mr5267719plz.191.1561649084937; Thu, 27 Jun 2019 08:24:44 -0700 (PDT) Received: from localhost (220-132-236-182.HINET-IP.hinet.net. [220.132.236.182]) by smtp.gmail.com with ESMTPSA id t2sm2485179pgo.61.2019.06.27.08.24.43 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:44 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:10 -0700 Message-Id: <20190627152011.18686-34-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.196 Subject: [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Add OpenSBI version 0.3 as a git submodule and as a prebult binary. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- .gitmodules | 3 ++ Makefile | 5 +- pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 0 -> 28848 bytes pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 0 -> 28904 bytes pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin 0 -> 28904 bytes roms/Makefile | 48 ++++++++++++++----- roms/opensbi | 1 + 7 files changed, 44 insertions(+), 13 deletions(-) create mode 100644 pc-bios/opensbi-riscv32-virt-fw_jump.bin create mode 100644 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin create mode 100644 pc-bios/opensbi-riscv64-virt-fw_jump.bin create mode 160000 roms/opensbi diff --git a/.gitmodules b/.gitmodules index 2857eec76377..7a10e72e09cd 100644 --- a/.gitmodules +++ b/.gitmodules @@ -55,3 +55,6 @@ [submodule "slirp"] path = slirp url = https://git.qemu.org/git/libslirp.git +[submodule "roms/opensbi"] + path = roms/opensbi + url = https://github.com/riscv/opensbi.git diff --git a/Makefile b/Makefile index cfb18f152544..c74e5ba91402 100644 --- a/Makefile +++ b/Makefile @@ -761,7 +761,10 @@ palcode-clipper \ u-boot.e500 u-boot-sam460-20100605.bin \ qemu_vga.ndrv \ edk2-licenses.txt \ -hppa-firmware.img +hppa-firmware.img \ +opensbi-riscv32-virt-fw_jump.bin \ +opensbi-riscv64-sifive_u-fw_jump.bin opensbi-riscv64-virt-fw_jump.bin + DESCS=50-edk2-i386-secure.json 50-edk2-x86_64-secure.json \ 60-edk2-aarch64.json 60-edk2-arm.json 60-edk2-i386.json 60-edk2-x86_64.json diff --git a/pc-bios/opensbi-riscv32-virt-fw_jump.bin b/pc-bios/opensbi-riscv32-virt-fw_jump.bin new file mode 100644 index 0000000000000000000000000000000000000000..c3e2aaa5148930754d3f88dcc9c6efdb961774d8 GIT binary patch literal 28848 zcmeHv4OkRMwrF+tboUG@3^p)eG>eRYvWY=PCF;iIZy3Pn8Wjm{)L=UhcGV<~#+bw` zIP?sN{Fn}mcs1)!l<2#0v(D-yzH1Pa0Zk;v1W-2`BLXqIic$Gh;GLT85ionRd*A)u zd*Amy;j2Df)m3$V>QwcqbE?NQKI%t4360QL5#m^DzYU;hW&5>(Eb?ZXW_R}K6g0Bu z&}jV=I*LX*T7m3>0`Uq8*=Y)$s;pedvA4Y3wW7xjsYOzZ&h!pF`$7F-TWP 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zSe%_IF3nzXr_=o-iZnEohAV*qq##_@TMO@%=^qrjXNDa9M4`V|;*C(~tOWV}3kp>w Y%Heh;{l6>W+X_9d&~wWBcZbmb0Xhc<(f|Me literal 0 HcmV?d00001 diff --git a/roms/Makefile b/roms/Makefile index 078d3fb70563..562ed726fd6b 100644 --- a/roms/Makefile +++ b/roms/Makefile @@ -37,6 +37,8 @@ find-cross-prefix = $(subst gcc,,$(notdir $(call find-cross-gcc,$(1)))) powerpc64_cross_prefix := $(call find-cross-prefix,powerpc64) powerpc_cross_prefix := $(call find-cross-prefix,powerpc) x86_64_cross_prefix := $(call find-cross-prefix,x86_64) +riscv32_cross_prefix := $(call find-cross-prefix,riscv32) +riscv64_cross_prefix := $(call find-cross-prefix,riscv64) # tag our seabios builds SEABIOS_EXTRAVERSION="-prebuilt.qemu.org" @@ -52,18 +54,21 @@ EDK2_EFIROM = edk2/BaseTools/Source/C/bin/EfiRom default: @echo "nothing is build by default" @echo "available build targets:" - @echo " bios -- update bios.bin (seabios)" - @echo " vgabios -- update vgabios binaries (seabios)" - @echo " sgabios -- update sgabios binaries" - @echo " pxerom -- update nic roms (bios only)" - @echo " efirom -- update nic roms (bios+efi)" - @echo " slof -- update slof.bin" - @echo " skiboot -- update skiboot.lid" - @echo " u-boot.e500 -- update u-boot.e500" - @echo " u-boot.sam460 -- update u-boot.sam460" - @echo " efi -- update UEFI (edk2) platform firmware" - @echo " clean -- delete the files generated by the previous" \ - "build targets" + @echo " bios -- update bios.bin (seabios)" + @echo " vgabios -- update vgabios binaries (seabios)" + @echo " sgabios -- update sgabios binaries" + @echo " pxerom -- update nic roms (bios only)" + @echo " efirom -- update nic roms (bios+efi)" + @echo " slof -- update slof.bin" + @echo " skiboot -- update skiboot.lid" + @echo " u-boot.e500 -- update u-boot.e500" + @echo " u-boot.sam460 -- update u-boot.sam460" + @echo " efi -- update UEFI (edk2) platform firmware" + @echo " opensbi32-virt -- update OpenSBI for 32-bit virt machine" + @echo " opensbi64-virt -- update OpenSBI for 64-bit virt machine" + @echo " opensbi64-sifive_u -- update OpenSBI for 64-bit sifive_u machine" + @echo " clean -- delete the files generated by the previous" \ + "build targets" bios: build-seabios-config-seabios-128k build-seabios-config-seabios-256k cp seabios/builds/seabios-128k/bios.bin ../pc-bios/bios.bin @@ -162,6 +167,24 @@ skiboot: efi: edk2-basetools $(MAKE) -f Makefile.edk2 +opensbi32-virt: + $(MAKE) -C opensbi \ + CROSS_COMPILE=$(riscv32_cross_prefix) \ + PLATFORM="qemu/virt" + cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv32-virt-fw_jump.bin + +opensbi64-virt: + $(MAKE) -C opensbi \ + CROSS_COMPILE=$(riscv64_cross_prefix) \ + PLATFORM="qemu/virt" + cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-virt-fw_jump.bin + +opensbi64-virt: + $(MAKE) -C opensbi \ + CROSS_COMPILE=$(riscv64_cross_prefix) \ + PLATFORM="qemu/sifive_u" + cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin + clean: rm -rf seabios/.config seabios/out seabios/builds $(MAKE) -C sgabios clean @@ -173,3 +196,4 @@ clean: $(MAKE) -C u-boot-sam460ex distclean $(MAKE) -C skiboot clean $(MAKE) -f Makefile.edk2 clean + $(MAKE) -C opensbi clean diff --git a/roms/opensbi b/roms/opensbi new file mode 160000 index 000000000000..ca20ac0cd4c0 --- /dev/null +++ b/roms/opensbi @@ -0,0 +1 @@ +Subproject commit ca20ac0cd4c099006d4eea4d9ac7bd7b58e2ae0f From patchwork Thu Jun 27 15:20:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1123488 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) 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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id h129sm2370438pfb.110.2019.06.27.08.24.46 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 27 Jun 2019 08:24:46 -0700 (PDT) Date: Thu, 27 Jun 2019 08:20:11 -0700 Message-Id: <20190627152011.18686-35-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> References: <20190627152011.18686-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.193 Subject: [Qemu-devel] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis If the user hasn't specified a firmware to load (with -bios) or specified no bios (with -bios none) then load OpenSBI by default. This allows users to boot a RISC-V kernel with just -kernel. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c | 49 +++++++++++++++++++++++++++++++++++++++++ hw/riscv/sifive_u.c | 7 +++--- hw/riscv/virt.c | 11 ++++++--- include/hw/riscv/boot.h | 3 +++ qemu-deprecated.texi | 20 +++++++++++++++++ 5 files changed, 84 insertions(+), 6 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index ff023f42d01d..23397edc8f15 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu-common.h" #include "qemu/units.h" #include "qemu/error-report.h" #include "exec/cpu-defs.h" @@ -32,6 +33,54 @@ # define KERNEL_BOOT_ADDRESS 0x80200000 #endif +void riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firmware, + hwaddr firmware_load_addr) +{ + char *firmware_filename; + + if (!machine->firmware) { + /* + * The user didn't specify -bios. + * At the moment we default to loading nothing when this hapens. + * In the future this defaul will change to loading the prebuilt + * OpenSBI firmware. Let's warn the user and then continue. + */ + warn_report("No -bios option specified. Not loading a firmware."); + warn_report("This default will change in QEMU 4.3. Please use the " \ + "-bios option to aviod breakages when this happens."); + warn_report("See QEMU's deprecation documentation for details"); + return; + } + + if (!strcmp(machine->firmware, "default")) { + /* + * The user has specified "-bios default". That means we are going to + * load the OpenSBI binary included in the QEMU source. + * + * We can't load the binary by default as it will break existing users + * as users are already loading their own firmware. + * + * Let's try to get everyone to specify the -bios option at all times, + * so then in the future we can make "-bios default" the default option + * if no -bios option is set without breaking anything. + */ + firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, + default_machine_firmware); + } else { + firmware_filename = machine->firmware; + } + + if (strcmp(firmware_filename, "none")) { + /* If not "none" load the firmware */ + riscv_load_firmware(firmware_filename, firmware_load_addr); + } + + if (!strcmp(machine->firmware, "default")) { + g_free(firmware_filename); + } +} + target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 420867155293..49254b0c0f95 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -49,6 +49,8 @@ #include +#define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" + static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -269,9 +271,8 @@ static void riscv_sifive_u_init(MachineState *machine) /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); - if (machine->firmware) { - riscv_load_firmware(machine->firmware, memmap[SIFIVE_U_DRAM].base); - } + riscv_find_and_load_firmware(machine, BIOS_FILENAME, + memmap[SIFIVE_U_DRAM].base); if (machine->kernel_filename) { riscv_load_kernel(machine->kernel_filename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d8181a4ff18a..244019da9e72 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -44,6 +44,12 @@ #include +#if defined(TARGET_RISCV32) +# define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin" +#else +# define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin" +#endif + static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -398,9 +404,8 @@ static void riscv_virt_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, mask_rom); - if (machine->firmware) { - riscv_load_firmware(machine->firmware, memmap[VIRT_DRAM].base); - } + riscv_find_and_load_firmware(machine, BIOS_FILENAME, + memmap[VIRT_DRAM].base); if (machine->kernel_filename) { uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index daa179b600f4..d56f2ae3eb5d 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -20,6 +20,9 @@ #ifndef RISCV_BOOT_H #define RISCV_BOOT_H +void riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firmware, + hwaddr firmware_load_addr); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr); target_ulong riscv_load_kernel(const char *kernel_filename); diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi index 97ea4ef3001a..f33e6d1c80fb 100644 --- a/qemu-deprecated.texi +++ b/qemu-deprecated.texi @@ -88,6 +88,26 @@ The @code{-realtime mlock=on|off} argument has been replaced by the The ``-virtfs_synth'' argument is now deprecated. Please use ``-fsdev synth'' and ``-device virtio-9p-...'' instead. +@subsection RISC-V -bios (since 4.1) + +QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the +RISC-V virt machine and sifive_u machine. + +QEMU 4.1 has no changes to the default behaviour to avoid breakages. This +default will change in a future QEMU release, so please prepare now. All users +of the virt or sifive_u machine must change their command line usage. + +QEMU 4.1 has three options, please migrate to one of these three: + 1. ``-bios none`` - This is the current default behavior if no -bios option + is included. QEMU will not automatically load any firmware. It is up + to the user to load all the images they need. + 2. ``-bios default`` - In a future QEMU release this will become the default + behaviour if no -bios option is specified. This option will load the + default OpenSBI firmware automatically. The firmware is included with + the QEMU release and no user interaction is required. All a user needs + to do is specify the kernel they want to boot with the -kernel option + 3. ``-bios `` - Tells QEMU to load the specified file as the firmwrae. + @section QEMU Machine Protocol (QMP) commands @subsection block-dirty-bitmap-add "autoload" parameter (since 2.12.0)