From patchwork Thu Jun 27 12:18:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hesham Almatary X-Patchwork-Id: 1123325 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=cl.cam.ac.uk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZJrF6SCTz9sLt for ; Thu, 27 Jun 2019 22:20:10 +1000 (AEST) Received: from localhost ([::1]:50232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgTNo-0002uj-39 for incoming@patchwork.ozlabs.org; Thu, 27 Jun 2019 08:20:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46661) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgTMv-0002k5-7m for qemu-devel@nongnu.org; Thu, 27 Jun 2019 08:19:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgTMu-0000Hs-3g for qemu-devel@nongnu.org; Thu, 27 Jun 2019 08:19:13 -0400 Received: from mta2.cl.cam.ac.uk ([2001:630:212:200::25:2]:47513) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hgTMk-0008WD-L4; Thu, 27 Jun 2019 08:19:04 -0400 Received: from cassia.cl.cam.ac.uk ([2001:630:212:238:b26e:bfff:fe2f:c7d9]) by mta2.cl.cam.ac.uk with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.86_2) (envelope-from ) id 1hgTMZ-000Sdw-7c; Thu, 27 Jun 2019 13:18:51 +0100 Received: from hmka2 by cassia.cl.cam.ac.uk with local (Exim 4.90_1) (envelope-from ) id 1hgTMZ-0002Lk-61; Thu, 27 Jun 2019 13:18:51 +0100 From: Hesham Almatary To: qemu-riscv@nongnu.org Date: Thu, 27 Jun 2019 13:18:26 +0100 Message-Id: <20190627121828.8376-4-Hesham.Almatary@cl.cam.ac.uk> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190627121828.8376-1-Hesham.Almatary@cl.cam.ac.uk> References: <20190627121828.8376-1-Hesham.Almatary@cl.cam.ac.uk> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:630:212:200::25:2 Subject: [Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , qemu-devel@nongnu.org, Alistair Francis , Hesham Almatary Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The PMP should be checked when doing a page table walk, and report access fault exception if the to-be-read PTE failed the PMP check. Suggested-by: Jonathan Behrens Signed-off-by: Hesham Almatary Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c17184f4e4..ab3ba3f15a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -94,6 +94,7 @@ enum { #define PRIV_VERSION_1_09_1 0x00010901 #define PRIV_VERSION_1_10_0 0x00011000 +#define TRANSLATE_PMP_FAIL 2 #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 #define NB_MMU_MODES 4 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5a1cd7cf96..00bc4f1712 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -211,6 +211,12 @@ restart: /* check that physical address of PTE is legal */ target_ulong pte_addr = base + idx * ptesize; + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), + 1 << MMU_DATA_LOAD, PRV_S)) { + return TRANSLATE_PMP_FAIL; + } #if defined(TARGET_RISCV32) target_ulong pte = ldl_phys(cs->as, pte_addr); #elif defined(TARGET_RISCV64) @@ -413,8 +419,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, (ret == TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type, mode)) { + ret = TRANSLATE_PMP_FAIL; + } + if (ret == TRANSLATE_PMP_FAIL) { pmp_violation = true; - ret = TRANSLATE_FAIL; } if (ret == TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,