From patchwork Wed Jun 26 14:46:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122877 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="aTMI536E"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45YmBb0p53z9sPQ for ; Thu, 27 Jun 2019 00:49:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728277AbfFZOtH (ORCPT ); Wed, 26 Jun 2019 10:49:07 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:55301 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728229AbfFZOrW (ORCPT ); Wed, 26 Jun 2019 10:47:22 -0400 Received: by mail-wm1-f68.google.com with SMTP id a15so2399793wmj.5 for ; Wed, 26 Jun 2019 07:47:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pCTMtso5AmHagoM0kbPRWJWMA6Wb3OobegULM1kp5BM=; b=aTMI536Eim8TcauDkcrVaRm5YZ9JFMT4cTZJ2X0B45UB0iPzfxC9MpXor3iIIP6oJI p5QiNRqa0HSMBlBQo10RFmlCtC5oo7epSxMKNgAjS1shoeMzuAC+YTpl3ZbPFPefs590 TDP11d3vu1zDy4pOZxpVNcJLsgP+k1uxQ0l2rU7rjjc2cR3hH4MI1/nnzTNjWq7/fqu3 sf0z4YJT7d8dnWRnSfOqkwHsFOHArPIqxLvkQO4O39eP6nzLv1x4cuhldNohB3s6Qra6 NDjvVjlhqwMk9bJk1NqWhM3qqxf7/MOMsK1ho/zjX7llQQ01AyNXlL9dJ4NA4Aasojv5 2zLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pCTMtso5AmHagoM0kbPRWJWMA6Wb3OobegULM1kp5BM=; b=GHe5dWtVDkj8Ry7l0jlAZ+VTv5jG0RBwBO4CXXOCRlt/LJdYivXQqH8jeFZ58RHqpW +YgJ9S6rOhmdsLWOWF7aRPDkqoAMlQrFH7JKNfZwvH4okxcH6A2mIunomS9UX2VjlOQg e50lAJwsGBqArjyyWuLZxYc0k+bzxv/zta8enGPAf9Vi6JmdQ4jKPzHUvpzy7FKTzNc8 9ygquqWWV7yJLIjXoesbSfgJceErbDcy7w2JlUiyNv38qfGdIwt6+BCFgWzTJ3ojMV0L t/CGdmxUx1R0vtjxsV6a9SBR/+gw1zQU+ncjvo6jlO2eBgfUpS2M/R2YoWJYBZ+cBK1y 9VUQ== X-Gm-Message-State: APjAAAWGVgTZV7XawNZkBLrzWQGu3X7LRxdo+2mAWj46S5VenoFoGqKN IjxQ5Yi1CIENBG2et+6qL/XYvg== X-Google-Smtp-Source: APXvYqzJtLxMzasX4DvcArKJ1/ZEMlTvM8AryQ+14SrXPDW5dpSRolFHNBkYxA8xHDBzWrY5LQXFGA== X-Received: by 2002:a1c:6c08:: with SMTP id h8mr3190763wmc.62.1561560439887; Wed, 26 Jun 2019 07:47:19 -0700 (PDT) Received: from mai.imgcgcw.net (26.92.130.77.rev.sfr.net. [77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:19 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 05/25] clocksource/drivers/tegra: Support per-CPU timers on all Tegra's Date: Wed, 26 Jun 2019 16:46:31 +0200 Message-Id: <20190626144651.16742-5-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko Assign TMR1-4 per-CPU core on 32bit Tegra's in a way it is done for Tegra210. In a result each core can handle its own timer events, less code is unique to ARM64 and Tegra's clock events driver now has higher rating on all Tegra's, replacing the ARM's TWD timer which isn't very accurate due to the clock rate jitter caused by CPU frequency scaling. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 120 ++++++++++------------------ 1 file changed, 43 insertions(+), 77 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 1e7ece279730..4b30ba6228c1 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -40,13 +40,18 @@ #define TIMER_PCR_INTR_CLR BIT(30) #ifdef CONFIG_ARM -#define TIMER_CPU0 0x50 /* TIMER3 */ +#define TIMER_CPU0 0x00 /* TIMER1 */ +#define TIMER_CPU2 0x50 /* TIMER3 */ +#define TIMER1_IRQ_IDX 0 +#define IRQ_IDX_FOR_CPU(cpu) (TIMER1_IRQ_IDX + cpu) +#define TIMER_BASE_FOR_CPU(cpu) \ + (((cpu) & 1) * 8 + ((cpu) < 2 ? TIMER_CPU0 : TIMER_CPU2)) #else #define TIMER_CPU0 0x90 /* TIMER10 */ #define TIMER10_IRQ_IDX 10 #define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) -#endif #define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) +#endif static u32 usec_config; static void __iomem *timer_reg_base; @@ -109,7 +114,6 @@ static void tegra_timer_resume(struct clock_event_device *evt) writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); } -#ifdef CONFIG_ARM64 static DEFINE_PER_CPU(struct timer_of, tegra_to) = { .flags = TIMER_OF_CLOCK | TIMER_OF_BASE, @@ -150,33 +154,8 @@ static int tegra_timer_stop(unsigned int cpu) return 0; } -#else /* CONFIG_ARM */ -static struct timer_of tegra_to = { - .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ, - - .clkevt = { - .name = "tegra_timer", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_DYNIRQ, - .set_next_event = tegra_timer_set_next_event, - .set_state_shutdown = tegra_timer_shutdown, - .set_state_periodic = tegra_timer_set_periodic, - .set_state_oneshot = tegra_timer_shutdown, - .tick_resume = tegra_timer_shutdown, - .suspend = tegra_timer_suspend, - .resume = tegra_timer_resume, - .cpumask = cpu_possible_mask, - }, - - .of_irq = { - .index = 2, - .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, - .handler = tegra_timer_isr, - }, -}; +#ifdef CONFIG_ARM static u64 notrace tegra_read_sched_clock(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); @@ -213,10 +192,12 @@ static struct clocksource suspend_rtc_clocksource = { }; #endif -static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) +static int tegra_init_timer(struct device_node *np, bool tegra20) { - int ret = 0; + struct timer_of *to; + int cpu, ret; + to = this_cpu_ptr(&tegra_to); ret = timer_of_init(np, to); if (ret < 0) goto out; @@ -258,29 +239,19 @@ static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) goto out; } - writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG); - -out: - return ret; -} - -#ifdef CONFIG_ARM64 -static int __init tegra_init_timer(struct device_node *np) -{ - int cpu, ret = 0; - struct timer_of *to; - - to = this_cpu_ptr(&tegra_to); - ret = tegra_timer_common_init(np, to); - if (ret < 0) - goto out; + writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); for_each_possible_cpu(cpu) { - struct timer_of *cpu_to; + struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); + + /* + * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the + * parent clock. + */ + if (tegra20) + cpu_to->of_clk.rate = 1000000; - cpu_to = per_cpu_ptr(&tegra_to, cpu); cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu); - cpu_to->of_clk.rate = timer_of_rate(to); cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); @@ -322,43 +293,39 @@ static int __init tegra_init_timer(struct device_node *np) timer_of_cleanup(to); return ret; } + +#ifdef CONFIG_ARM64 +static int __init tegra210_init_timer(struct device_node *np) +{ + return tegra_init_timer(np, false); +} +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); #else /* CONFIG_ARM */ -static int __init tegra_init_timer(struct device_node *np) +static int __init tegra20_init_timer(struct device_node *np) { - int ret = 0; + struct timer_of *to; + int err; - ret = tegra_timer_common_init(np, &tegra_to); - if (ret < 0) - goto out; + err = tegra_init_timer(np, true); + if (err) + return err; - tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0); - tegra_to.of_clk.rate = 1000000; /* microsecond timer */ + to = this_cpu_ptr(&tegra_to); sched_clock_register(tegra_read_sched_clock, 32, - timer_of_rate(&tegra_to)); - ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", timer_of_rate(&tegra_to), + timer_of_rate(to)); + err = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", timer_of_rate(to), 300, 32, clocksource_mmio_readl_up); - if (ret) { - pr_err("Failed to register clocksource\n"); - goto out; - } + if (err) + pr_err("Failed to register clocksource: %d\n", err); tegra_delay_timer.read_current_timer = tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = timer_of_rate(&tegra_to); + tegra_delay_timer.freq = timer_of_rate(to); register_current_timer_delay(&tegra_delay_timer); - clockevents_config_and_register(&tegra_to.clkevt, - timer_of_rate(&tegra_to), - 0x1, - 0x1fffffff); - - return ret; -out: - timer_of_cleanup(&tegra_to); - - return ret; + return 0; } static int __init tegra20_init_rtc(struct device_node *np) @@ -374,6 +341,5 @@ static int __init tegra20_init_rtc(struct device_node *np) return 0; } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); #endif -TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer); -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer); From patchwork Wed Jun 26 14:46:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122876 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:20 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 06/25] clocksource/drivers/tegra: Unify timer code Date: Wed, 26 Jun 2019 16:46:32 +0200 Message-Id: <20190626144651.16742-6-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko Tegra132 is 64bit platform and it has the tegra20-timer hardware unit. Right now the corresponding timer code isn't compiled for ARM64, remove ifdef'iness from the code and compile tegra20-timer for both 32 and 64 bit platforms. Also note that like the older generations, Tegra210 has the microseconds counter, hence the timer_us clocksource is now made available for Tegra210 as well. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 111 +++++++++++++++------------- 1 file changed, 60 insertions(+), 51 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 4b30ba6228c1..acd68c77fa91 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -21,10 +21,6 @@ #include "timer-of.h" -#ifdef CONFIG_ARM -#include -#endif - #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c #define RTC_MILLISECONDS 0x10 @@ -39,25 +35,17 @@ #define TIMER_PCR 0x4 #define TIMER_PCR_INTR_CLR BIT(30) -#ifdef CONFIG_ARM -#define TIMER_CPU0 0x00 /* TIMER1 */ -#define TIMER_CPU2 0x50 /* TIMER3 */ +#define TIMER1_BASE 0x00 +#define TIMER2_BASE 0x08 +#define TIMER3_BASE 0x50 +#define TIMER4_BASE 0x58 +#define TIMER10_BASE 0x90 + #define TIMER1_IRQ_IDX 0 -#define IRQ_IDX_FOR_CPU(cpu) (TIMER1_IRQ_IDX + cpu) -#define TIMER_BASE_FOR_CPU(cpu) \ - (((cpu) & 1) * 8 + ((cpu) < 2 ? TIMER_CPU0 : TIMER_CPU2)) -#else -#define TIMER_CPU0 0x90 /* TIMER10 */ #define TIMER10_IRQ_IDX 10 -#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) -#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) -#endif static u32 usec_config; static void __iomem *timer_reg_base; -#ifdef CONFIG_ARM -static struct delay_timer tegra_delay_timer; -#endif static int tegra_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) @@ -155,17 +143,23 @@ static int tegra_timer_stop(unsigned int cpu) return 0; } -#ifdef CONFIG_ARM static u64 notrace tegra_read_sched_clock(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); } +#ifdef CONFIG_ARM static unsigned long tegra_delay_timer_read_counter_long(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); } +static struct delay_timer tegra_delay_timer = { + .read_current_timer = tegra_delay_timer_read_counter_long, + .freq = 1000000, +}; +#endif + static struct timer_of suspend_rtc_to = { .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, }; @@ -190,9 +184,34 @@ static struct clocksource suspend_rtc_clocksource = { .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, }; -#endif -static int tegra_init_timer(struct device_node *np, bool tegra20) +static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20) +{ + if (tegra20) { + switch (cpu) { + case 0: + return TIMER1_BASE; + case 1: + return TIMER2_BASE; + case 2: + return TIMER3_BASE; + default: + return TIMER4_BASE; + } + } + + return TIMER10_BASE + cpu * 8; +} + +static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) +{ + if (tegra20) + return TIMER1_IRQ_IDX + cpu; + + return TIMER10_IRQ_IDX + cpu; +} + +static int __init tegra_init_timer(struct device_node *np, bool tegra20) { struct timer_of *to; int cpu, ret; @@ -243,6 +262,8 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); + unsigned int base = tegra_base_for_cpu(cpu, tegra20); + unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20); /* * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the @@ -251,10 +272,10 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) if (tegra20) cpu_to->of_clk.rate = 1000000; - cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu); + cpu_to = per_cpu_ptr(&tegra_to, cpu); + cpu_to->of_base.base = timer_reg_base + base; cpu_to->clkevt.cpumask = cpumask_of(cpu); - cpu_to->clkevt.irq = - irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); + cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { pr_err("%s: can't map IRQ for CPU%d\n", __func__, cpu); @@ -274,6 +295,18 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) } } + sched_clock_register(tegra_read_sched_clock, 32, 1000000); + + ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", 1000000, + 300, 32, clocksource_mmio_readl_up); + if (ret) + pr_err("failed to register clocksource: %d\n", ret); + +#ifdef CONFIG_ARM + register_current_timer_delay(&tegra_delay_timer); +#endif + cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, tegra_timer_stop); @@ -294,39 +327,17 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) return ret; } -#ifdef CONFIG_ARM64 static int __init tegra210_init_timer(struct device_node *np) { return tegra_init_timer(np, false); } TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); -#else /* CONFIG_ARM */ + static int __init tegra20_init_timer(struct device_node *np) { - struct timer_of *to; - int err; - - err = tegra_init_timer(np, true); - if (err) - return err; - - to = this_cpu_ptr(&tegra_to); - - sched_clock_register(tegra_read_sched_clock, 32, - timer_of_rate(to)); - err = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", timer_of_rate(to), - 300, 32, clocksource_mmio_readl_up); - if (err) - pr_err("Failed to register clocksource: %d\n", err); - - tegra_delay_timer.read_current_timer = - tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = timer_of_rate(to); - register_current_timer_delay(&tegra_delay_timer); - - return 0; + return tegra_init_timer(np, true); } +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); static int __init tegra20_init_rtc(struct device_node *np) { @@ -341,5 +352,3 @@ static int __init tegra20_init_rtc(struct device_node *np) return 0; } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); -#endif From patchwork Wed Jun 26 14:46:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122875 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:23 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 07/25] clocksource/drivers/tegra: Reset hardware state on init Date: Wed, 26 Jun 2019 16:46:33 +0200 Message-Id: <20190626144651.16742-7-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko Reset timer's hardware state to ensure that initially it is in a predictable state. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index acd68c77fa91..3e4f12aee8df 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -123,6 +123,9 @@ static int tegra_timer_setup(unsigned int cpu) { struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + writel(0, timer_of_base(to) + TIMER_PTV); + writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); + irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); From patchwork Wed Jun 26 14:46:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122861 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UVaPVeuQ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Ym8d6Vghz9sNT for ; Thu, 27 Jun 2019 00:47:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728267AbfFZOr3 (ORCPT ); Wed, 26 Jun 2019 10:47:29 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:45198 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728255AbfFZOr2 (ORCPT ); Wed, 26 Jun 2019 10:47:28 -0400 Received: by mail-wr1-f68.google.com with SMTP id f9so3031309wre.12 for ; Wed, 26 Jun 2019 07:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g8xq5QdzKn63u1M0EUnZlEgWbt3e6x6fUijd7UtCicQ=; b=UVaPVeuQL6Wc9Py2t8mm/2Sqx0/xqytMEuZ4gtH5Uh7kOTYK0ol8zsgRZh+504UrYO GJxKBEjY5aQTdN9GlYKH3nkRyWNYr5YgIbk/Q0jcSJ2MN5cY/XeFinwe+22WI9BD4f5z 999N71NEIhsSUkRfSopXvhtlPaNTZE/ULLcEauAkXC6fjRyoCjT7xR2gia5sSBefbzBc C/6onK+VPidlHO1dG/zOXeE9sTxRCe3wq0dEH1cyUhFhZd20fdz0i+XS7elAMKBUExP2 kVPdj48uvdazjg0WNJEW8rVG545qgpBx0UKso71Hg2Q8ZTQKbkeTZMwtmNfxogOGV/hy CSQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g8xq5QdzKn63u1M0EUnZlEgWbt3e6x6fUijd7UtCicQ=; b=i95PkqYVoSrj20sUqQdBbUnFNK7BtJp6FfhsWM6VDzpBIh2pa+lmxhEPSCtqB2d1OX N5Wgxy68YRmGq4O2OcAXrFj6580sNOGQc/FzlQkSe5lRR+2nTwYR1QG/0nsXmlvyfh/C 8Tmjp0ORWW50rJgZuDfRRDbawS/+rai8og9E3ALg33/YYUh5SWvvd+q8WWXqubztIDbp AaFG2yUC+gBbwJ9czDVVmWRApg6NtjqcE+utWNzVecNKcCU0MpkKxZuBF+L9T0Jd9ad4 fDjHdGXNKKK4lSD1DJRrrgbYfpfXVsrlZXY9sv09bNj6bqg9hzOCsoS73rGE1Cuo7boL 6Ctw== X-Gm-Message-State: APjAAAX300aW/UswrZ8faegxClah8WktBTsWUmDxtLvQy2hbFvWnb33U Qn0j6J5A9wgxOZknRmJQinlkhUI4cO4= X-Google-Smtp-Source: APXvYqzkT+OD/a1AlvyTUKp+2Nk3TRMNEmWs/yHGic5euOd1lxXOeIUul01n7Y+jwIDrIydsJaPPTw== X-Received: by 2002:a5d:4087:: with SMTP id o7mr3997035wrp.277.1561560445192; Wed, 26 Jun 2019 07:47:25 -0700 (PDT) Received: from mai.imgcgcw.net (26.92.130.77.rev.sfr.net. [77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:24 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 08/25] clocksource/drivers/tegra: Replace readl/writel with relaxed versions Date: Wed, 26 Jun 2019 16:46:34 +0200 Message-Id: <20190626144651.16742-8-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko The readl/writel functions are inserting memory barrier to ensure that outstanding memory writes are completed, this results in L2 cache syncing being done on Tegra20 and Tegra30 which isn't a very cheap operation. Replace all readl/writel occurrences in the code with the relaxed versions since there is no need for the memory-access syncing. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 35 +++++++++++++++-------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 3e4f12aee8df..276b55f6ada0 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -52,9 +52,9 @@ static int tegra_timer_set_next_event(unsigned long cycles, { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PTV_EN | - ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ - reg_base + TIMER_PTV); + writel_relaxed(TIMER_PTV_EN | + ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ + reg_base + TIMER_PTV); return 0; } @@ -63,7 +63,7 @@ static int tegra_timer_shutdown(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(0, reg_base + TIMER_PTV); + writel_relaxed(0, reg_base + TIMER_PTV); return 0; } @@ -72,9 +72,9 @@ static int tegra_timer_set_periodic(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PTV_EN | TIMER_PTV_PER | - ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), - reg_base + TIMER_PTV); + writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | + ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), + reg_base + TIMER_PTV); return 0; } @@ -84,7 +84,7 @@ static irqreturn_t tegra_timer_isr(int irq, void *dev_id) struct clock_event_device *evt = (struct clock_event_device *)dev_id; void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); evt->event_handler(evt); return IRQ_HANDLED; @@ -94,12 +94,12 @@ static void tegra_timer_suspend(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); } static void tegra_timer_resume(struct clock_event_device *evt) { - writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); + writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); } static DEFINE_PER_CPU(struct timer_of, tegra_to) = { @@ -123,8 +123,8 @@ static int tegra_timer_setup(unsigned int cpu) { struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); - writel(0, timer_of_base(to) + TIMER_PTV); - writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); + writel_relaxed(0, timer_of_base(to) + TIMER_PTV); + writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); @@ -148,13 +148,13 @@ static int tegra_timer_stop(unsigned int cpu) static u64 notrace tegra_read_sched_clock(void) { - return readl(timer_reg_base + TIMERUS_CNTR_1US); + return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); } #ifdef CONFIG_ARM static unsigned long tegra_delay_timer_read_counter_long(void) { - return readl(timer_reg_base + TIMERUS_CNTR_1US); + return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); } static struct delay_timer tegra_delay_timer = { @@ -175,8 +175,9 @@ static struct timer_of suspend_rtc_to = { */ static u64 tegra_rtc_read_ms(struct clocksource *cs) { - u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS); - u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS); + void __iomem *reg_base = timer_of_base(&suspend_rtc_to); + u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); + u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); return (u64)s * MSEC_PER_SEC + ms; } @@ -261,7 +262,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) goto out; } - writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); + writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:26 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 09/25] clocksource/drivers/tegra: Release all IRQ's on request_irq() error Date: Wed, 26 Jun 2019 16:46:35 +0200 Message-Id: <20190626144651.16742-9-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko Release all requested IRQ's on the request error to properly clean up allocated resources. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 276b55f6ada0..e2ef6b8211a5 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -284,7 +284,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) pr_err("%s: can't map IRQ for CPU%d\n", __func__, cpu); ret = -EINVAL; - goto out; + goto out_irq; } irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); @@ -294,7 +294,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) if (ret) { pr_err("%s: cannot setup irq %d for CPU%d\n", __func__, cpu_to->clkevt.irq, cpu); - ret = -EINVAL; + irq_dispose_mapping(cpu_to->clkevt.irq); + cpu_to->clkevt.irq = 0; goto out_irq; } } From patchwork Wed Jun 26 14:46:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122863 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="zCRa4KiG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Ym8l6qV5z9sNT for ; Thu, 27 Jun 2019 00:47:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728293AbfFZOrf (ORCPT ); Wed, 26 Jun 2019 10:47:35 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:39179 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728269AbfFZOra (ORCPT ); Wed, 26 Jun 2019 10:47:30 -0400 Received: by mail-wr1-f67.google.com with SMTP id x4so3064218wrt.6 for ; Wed, 26 Jun 2019 07:47:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y/jkAn3vCT4++dqCh3VgpJih6azC2n9WMcpnAYjdo7g=; b=zCRa4KiGwJg3QYoLLuG4sg/cwzELVE1W9AdFPLYWqf58c2G9eBPP6k1fhC5QL3HePt NpSQzTw2sNBsZaQ9hHadaGUDhCFa0UYWILqelTzNejqzsMNGOO1bgWKRZbLRCB1xU5p1 DUAHACuOvIui7p+sojRs7xQaMbN6b4teAHpJ81Ewji4F6oER3YeB8uqEAtZPb7ZiVn1a nnh3SeFzvIZSIZnytnRywS5RXNRct3E0MXR24xXzbBjk+lmG9eX/Diwjp2966XFuaLyx XZhjyqY3NCTub2mcttaig1fD3wW9bC2RLaS5lDdd5O7Vtc5LJNIskGkOBnWIIhaTrszi 9CJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y/jkAn3vCT4++dqCh3VgpJih6azC2n9WMcpnAYjdo7g=; b=A41NlbdsSktScAAUzpZCIW+bThkNf2k1RYI9Ng83oPnwRIvZsB4G4JWVNs5K98bsar 8PB/dJqM5PY/vNFzMxxOOcEuP7JGDwxUB1fe8k3GT4a7DgNESQoUmGhA1j9/EIp8JR7e nL4HkkATfDKb+6cMyp0H8JudI9JL1IL5fXWW5IyfX36X0NI9SHBlebGGuO6OZBBxXE0+ sAAqkRj6xLnnGD9PuzsT17odKIF3mMee+YJ0JQJ74+rUigF/u5l/6YK7ho8X13AEFpLU v3Q0tozjrH4tnW8hIL+aQ1cZkESo7l+QqBGz63ccV+9C4QD5a3FF4Fp3jdoGyhbZ59C1 Wj3w== X-Gm-Message-State: APjAAAVuPbCiadFZKRt8fWtIUAZMqCoCOp2ez/TuBo9CTyYuNdT/kCmM zveB1npkT1HpNzLH8lwJUUsC3TFznRA= X-Google-Smtp-Source: APXvYqzsT+EllwSjAVLW5u50pIj2VwYxnsGDw07MjWP59b86AMovA52i7jADVBHYVrr3A7ZkyzE2tw== X-Received: by 2002:adf:ce88:: with SMTP id r8mr4325686wrn.42.1561560448173; Wed, 26 Jun 2019 07:47:28 -0700 (PDT) Received: from mai.imgcgcw.net (26.92.130.77.rev.sfr.net. [77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:27 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 10/25] clocksource/drivers/tegra: Minor code clean up Date: Wed, 26 Jun 2019 16:46:36 +0200 Message-Id: <20190626144651.16742-10-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko Correct typo and use proper upper casing for acronyms in the comments, use common style for error messages, prepend error messages with "tegra-timer:", add error message for cpuhp_setup_state() failure and clean up whitespaces in the code to fix checkpatch warnings. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 43 ++++++++++++++++------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index e2ef6b8211a5..6a3704142f31 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -6,6 +6,8 @@ * Colin Cross */ +#define pr_fmt(fmt) "tegra-timer: " fmt + #include #include #include @@ -21,13 +23,13 @@ #include "timer-of.h" -#define RTC_SECONDS 0x08 -#define RTC_SHADOW_SECONDS 0x0c -#define RTC_MILLISECONDS 0x10 +#define RTC_SECONDS 0x08 +#define RTC_SHADOW_SECONDS 0x0c +#define RTC_MILLISECONDS 0x10 -#define TIMERUS_CNTR_1US 0x10 -#define TIMERUS_USEC_CFG 0x14 -#define TIMERUS_CNTR_FREEZE 0x4c +#define TIMERUS_CNTR_1US 0x10 +#define TIMERUS_USEC_CFG 0x14 +#define TIMERUS_CNTR_FREEZE 0x4c #define TIMER_PTV 0x0 #define TIMER_PTV_EN BIT(31) @@ -48,7 +50,7 @@ static u32 usec_config; static void __iomem *timer_reg_base; static int tegra_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) + struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); @@ -169,15 +171,17 @@ static struct timer_of suspend_rtc_to = { /* * tegra_rtc_read - Reads the Tegra RTC registers - * Care must be taken that this funciton is not called while the + * Care must be taken that this function is not called while the * tegra_rtc driver could be executing to avoid race conditions * on the RTC shadow register */ static u64 tegra_rtc_read_ms(struct clocksource *cs) { void __iomem *reg_base = timer_of_base(&suspend_rtc_to); + u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); + return (u64)s * MSEC_PER_SEC + ms; } @@ -222,7 +226,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) to = this_cpu_ptr(&tegra_to); ret = timer_of_init(np, to); - if (ret < 0) + if (ret) goto out; timer_reg_base = timer_of_base(to); @@ -281,8 +285,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { - pr_err("%s: can't map IRQ for CPU%d\n", - __func__, cpu); + pr_err("failed to map irq for cpu%d\n", cpu); ret = -EINVAL; goto out_irq; } @@ -292,8 +295,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) IRQF_TIMER | IRQF_NOBALANCING, cpu_to->clkevt.name, &cpu_to->clkevt); if (ret) { - pr_err("%s: cannot setup irq %d for CPU%d\n", - __func__, cpu_to->clkevt.irq, cpu); + pr_err("failed to set up irq for cpu%d: %d\n", + cpu, ret); irq_dispose_mapping(cpu_to->clkevt.irq); cpu_to->clkevt.irq = 0; goto out_irq; @@ -312,11 +315,14 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) register_current_timer_delay(&tegra_delay_timer); #endif - cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, - "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, - tegra_timer_stop); + ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, + "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, + tegra_timer_stop); + if (ret) + pr_err("failed to set up cpu hp state: %d\n", ret); return ret; + out_irq: for_each_possible_cpu(cpu) { struct timer_of *cpu_to; @@ -329,6 +335,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) } out: timer_of_cleanup(to); + return ret; } @@ -352,8 +359,6 @@ static int __init tegra20_init_rtc(struct device_node *np) if (ret) return ret; - clocksource_register_hz(&suspend_rtc_clocksource, 1000); - - return 0; + return clocksource_register_hz(&suspend_rtc_clocksource, 1000); } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); From patchwork Wed Jun 26 14:46:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122862 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:30 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 12/25] clocksource/drivers/tegra: Lower clocksource rating for some Tegra's Date: Wed, 26 Jun 2019 16:46:38 +0200 Message-Id: <20190626144651.16742-12-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko Arch-timer is more preferable for a range of Tegra SoC generations as it has higher precision and is not affect by any kind of problems. Pointed-out-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 30 +++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 6a3704142f31..ed1454000ea9 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -109,7 +109,6 @@ static DEFINE_PER_CPU(struct timer_of, tegra_to) = { .clkevt = { .name = "tegra_timer", - .rating = 460, .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, .set_next_event = tegra_timer_set_next_event, .set_state_shutdown = tegra_timer_shutdown, @@ -219,7 +218,8 @@ static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) return TIMER10_IRQ_IDX + cpu; } -static int __init tegra_init_timer(struct device_node *np, bool tegra20) +static int __init tegra_init_timer(struct device_node *np, bool tegra20, + int rating) { struct timer_of *to; int cpu, ret; @@ -282,6 +282,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) cpu_to = per_cpu_ptr(&tegra_to, cpu); cpu_to->of_base.base = timer_reg_base + base; + cpu_to->clkevt.rating = rating; cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { @@ -341,13 +342,34 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) static int __init tegra210_init_timer(struct device_node *np) { - return tegra_init_timer(np, false); + /* + * Arch-timer can't survive across power cycle of CPU core and + * after CPUPORESET signal due to a system design shortcoming, + * hence tegra-timer is more preferable on Tegra210. + */ + return tegra_init_timer(np, false, 460); } TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); static int __init tegra20_init_timer(struct device_node *np) { - return tegra_init_timer(np, true); + int rating; + + /* + * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer, + * that timer runs off the CPU clock and hence is subjected to + * a jitter caused by DVFS clock rate changes. Tegra-timer is + * more preferable for older Tegra's, while later SoC generations + * have arch-timer as a main per-CPU timer and it is not affected + * by DVFS changes. + */ + if (of_machine_is_compatible("nvidia,tegra20") || + of_machine_is_compatible("nvidia,tegra30")) + rating = 460; + else + rating = 330; + + return tegra_init_timer(np, true, rating); } TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); From patchwork Wed Jun 26 14:46:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="mCICVFSv"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45YmB421WNz9sPG for ; Thu, 27 Jun 2019 00:48:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728332AbfFZOrm (ORCPT ); Wed, 26 Jun 2019 10:47:42 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:45228 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728323AbfFZOrl (ORCPT ); Wed, 26 Jun 2019 10:47:41 -0400 Received: by mail-wr1-f67.google.com with SMTP id f9so3032201wre.12 for ; Wed, 26 Jun 2019 07:47:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OvrcN7nx43BK8pLnR/sB9l6LAwke86j5KsajSpQYjKA=; b=mCICVFSvfWhpDZ5YmmaELz/zznaIpGcdfs8FZgdT3WtG7W8KAiTfLtZ9jZdOgrISVo 06sq+INZVl02rS6ESmHNfcVirq9QXHHBsVLAt9ufDEuMGzWjJdMooqDDjF+oP1nLwNvc df99uupjlfwafO/77yL7yLRY+3lDXv4ow/Y4Y+nrLLT1cAr1jkRedOXcaDEDLXnzamnQ inQuHVSlrvWYANKddsP7msozwi04FuIDExLqKpZOaNVCfOZ11oNAUlQVNQZa/tUX9ohm 1Xek+XJ5eNxXbPec6qESpuHBIak//k3MfxyIXVczUbtMVIkOFV/bdE3i2sY3Jx+56+7N 1aBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OvrcN7nx43BK8pLnR/sB9l6LAwke86j5KsajSpQYjKA=; b=ikkeSonK6DSV2CVcZpDltfinFXjpRSKbb74VVj4R3FuZHdd/Ucio01erogy8VG/aYN fs5DqjpzvfBC7zaXf9BBdC8dl//OkBBOqdBoIxDAzfmZF+PXQrhxAWKLtf57l1YjJW0p AlyTZMJT9Xe/+IFGtnQrF7YkkYx+1ABDThpfFnxgEt9vz0yw/VTRLsgbIDEj7RRocr7a 9QDONCheOm4i1YAFWIWNoin0YYWrrgSiTyxx5H/Vd87T/dOkf5+ChnxhoQ4UjdoiNwMl /gHk4DYKRGCzVw6lWE9eExEpxwaHq3J3y1G06elyGJDCyvmzWMvGBKXB+/aadRSz3ATV x8sQ== X-Gm-Message-State: APjAAAUva/SIFlMMbvgqb89Ry9fuuQpJMwNPZmNl36bIiO2y2faZti1l zFd6LrfoTa0egHE7ZDS+CUGaAw== X-Google-Smtp-Source: APXvYqzAMPf/Y0b4yUB24DbJ/f5dxbPWkjooxapqlMqClQ6g7CntGHvU80e36lkwFCfqVGx0lfzGNw== X-Received: by 2002:adf:e3cc:: with SMTP id k12mr3845577wrm.159.1561560459691; Wed, 26 Jun 2019 07:47:39 -0700 (PDT) Received: from mai.imgcgcw.net (26.92.130.77.rev.sfr.net. [77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:39 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 16/25] clocksource/drivers/tegra: Restore timer rate on Tegra210 Date: Wed, 26 Jun 2019 16:46:42 +0200 Message-Id: <20190626144651.16742-16-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko The clocksource rate is initialized only for the first per-CPU clocksource and then that rate shall be replicated for the rest of clocksource's because they are initialized manually in the code. Fixes: 3be2a85a0b61 ("clocksource/drivers/tegra: Support per-CPU timers on all Tegra's") Acked-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index ed1454000ea9..880ba67ca7ee 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -279,6 +279,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, */ if (tegra20) cpu_to->of_clk.rate = 1000000; + else + cpu_to->of_clk.rate = timer_of_rate(to); cpu_to = per_cpu_ptr(&tegra_to, cpu); cpu_to->of_base.base = timer_reg_base + base; From patchwork Wed Jun 26 14:46:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122871 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="a71rNY30"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45YmB317P4z9sNt for ; Thu, 27 Jun 2019 00:48:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728285AbfFZOro (ORCPT ); Wed, 26 Jun 2019 10:47:44 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:33951 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727957AbfFZOrn (ORCPT ); Wed, 26 Jun 2019 10:47:43 -0400 Received: by mail-wr1-f67.google.com with SMTP id k11so3097667wrl.1 for ; Wed, 26 Jun 2019 07:47:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yqfHGm0TnB/EluOWXQT4ZbDAqP2xMCI6PrNJ2MlYeVk=; b=a71rNY30tMc88OSz/m3t84f2lUVWT7mZhl/MxOCDBStOMFmcmyp+0EeBl0cq5GewFx VUaTobcEMFxs9V5fU+/dfPBCEVA3H39ox6+4QXJDvLk2FzCwVdIe/oKS7NXNgU70uEcB JbJNTzlwSOxEQlywVhrYG4TZaipPcxo0eTTIsoSXbepbQkzyYCc62cVLAJSZXgRmT7qj lGn7oceuBdOThW6CENUrTrjdjj576c4AQv2Puhoqm1u2vM2lDtTo1F8QdoMQ68ovHssX KNaXaXJ2WH6YTa+jMkqI/RdqOV+m/HHrJbuCtSGPfAWFXvN+Qpk3UgZNQ5qGLlCjHuh1 8zBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yqfHGm0TnB/EluOWXQT4ZbDAqP2xMCI6PrNJ2MlYeVk=; b=Ltd5JrtNeSBH1H0sF7RSeM8a9Nihh3mRMysxPJ/qIA4glwHvh8Wlxhxe73Y3LXSgD1 uE78rusABzvsdH1E0ILourtF2YC3szTh2PPVH5hY3pBkpBi3/7kGLuHkITMVYjD0pgG8 NwB1QlNwz2DG0QYc4ILDoIsUPb9mm0TaP9h5CNweh28SGLhzM7o5sJpWM7GgJ0vkBfCw ZFjy8FO9aNJ9Bcify9xOxIcl7f8RUAIyA/tTJOic28N+M1tEiJ0CvYGfpvQTt6oD9C7o hTY0SFdEKVgiuOiSMK6Ve/Ypnd8GxfwCtb8CNmaFWKowPe1Dcl9nfow+6WBGvqOzH5c1 6PoQ== X-Gm-Message-State: APjAAAV4N+R0b8FxPMgu268r02r6FhShENkXmeV16QuGE/Md53k3cUCb uqccQodKbmue8e1pkVhlsEfQpw== X-Google-Smtp-Source: APXvYqwiZIlhM0IIhYBQ3uOr0VubIIIk4zq48f0S/j2B8N8PPz8mVyq7XGXacPm5ZFILJYSrbtW2pw== X-Received: by 2002:a5d:53d2:: with SMTP id a18mr4156921wrw.98.1561560461122; Wed, 26 Jun 2019 07:47:41 -0700 (PDT) Received: from mai.imgcgcw.net (26.92.130.77.rev.sfr.net. [77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:40 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 17/25] clocksource/drivers/tegra: Remove duplicated use of per_cpu_ptr Date: Wed, 26 Jun 2019 16:46:43 +0200 Message-Id: <20190626144651.16742-17-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko It was left unnoticed by accident, which means that the code could be cleaned up a tad more. Acked-by: Jon Hunter Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 42 ++++++++++++++++++------------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index 880ba67ca7ee..f172a57cc5fe 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -218,6 +218,19 @@ static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) return TIMER10_IRQ_IDX + cpu; } +static inline unsigned long tegra_rate_for_timer(struct timer_of *to, + bool tegra20) +{ + /* + * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the + * parent clock. + */ + if (tegra20) + return 1000000; + + return timer_of_rate(to); +} + static int __init tegra_init_timer(struct device_node *np, bool tegra20, int rating) { @@ -270,32 +283,27 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); + unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING; + unsigned long rate = tegra_rate_for_timer(to, tegra20); unsigned int base = tegra_base_for_cpu(cpu, tegra20); unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20); + unsigned int irq = irq_of_parse_and_map(np, idx); - /* - * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the - * parent clock. - */ - if (tegra20) - cpu_to->of_clk.rate = 1000000; - else - cpu_to->of_clk.rate = timer_of_rate(to); - - cpu_to = per_cpu_ptr(&tegra_to, cpu); - cpu_to->of_base.base = timer_reg_base + base; - cpu_to->clkevt.rating = rating; - cpu_to->clkevt.cpumask = cpumask_of(cpu); - cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); - if (!cpu_to->clkevt.irq) { + if (!irq) { pr_err("failed to map irq for cpu%d\n", cpu); ret = -EINVAL; goto out_irq; } + cpu_to->clkevt.irq = irq; + cpu_to->clkevt.rating = rating; + cpu_to->clkevt.cpumask = cpumask_of(cpu); + cpu_to->of_base.base = timer_reg_base + base; + cpu_to->of_clk.rate = rate; + irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); - ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, - IRQF_TIMER | IRQF_NOBALANCING, + + ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags, cpu_to->clkevt.name, &cpu_to->clkevt); if (ret) { pr_err("failed to set up irq for cpu%d: %d\n", From patchwork Wed Jun 26 14:46:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="DxmMYVPx"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45YmB35h8Fz9sP8 for ; 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:41 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 18/25] clocksource/drivers/tegra: Set and use timer's period Date: Wed, 26 Jun 2019 16:46:44 +0200 Message-Id: <20190626144651.16742-18-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko The of_clk structure has a period field that is set up initially by timer_of_clk_init(), that period value need to be adjusted for a case of TIMER1-9 that are running at a fixed rate that doesn't match the clock's rate. Note that the period value is currently used only by some of the clocksource drivers internally and hence this is just a minor cleanup change that doesn't fix anything. Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index f172a57cc5fe..41257f89a216 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -73,9 +73,9 @@ static int tegra_timer_shutdown(struct clock_event_device *evt) static int tegra_timer_set_periodic(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + unsigned long period = timer_of_period(to_timer_of(evt)); - writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | - ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), + writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1), reg_base + TIMER_PTV); return 0; @@ -299,6 +299,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, cpu_to->clkevt.rating = rating; cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->of_base.base = timer_reg_base + base; + cpu_to->of_clk.period = rate / HZ; cpu_to->of_clk.rate = rate; irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); From patchwork Wed Jun 26 14:46:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122870 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="xiqkyqpU"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Ym9w5Hnsz9sP8 for ; Thu, 27 Jun 2019 00:48:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728358AbfFZOrq (ORCPT ); Wed, 26 Jun 2019 10:47:46 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:50715 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728350AbfFZOrq (ORCPT ); Wed, 26 Jun 2019 10:47:46 -0400 Received: by mail-wm1-f67.google.com with SMTP id c66so2416269wmf.0 for ; Wed, 26 Jun 2019 07:47:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DAchjLoGp53ThJdxxXYtoXfJ80Q4DYb4SAa6+caQEjY=; b=xiqkyqpUMCyhR970FBfcZF49AhwK/SFedKuJ5FRBVxNPZjGphDLf8ZqY5lwbop6ozN oY3nkTgayC/91n0TSa61b4ZfKWmnist6N8thv5t4eXM1AEpYGTyiyCdsizlz4O9VBAS+ Hj+B1iw81OiFPzqLulhTnWzCm3f/PCMn+18KJzjQ3Y635qkmdvYgUEgG76MGg5Y7n4hS T0XeUfLyfUCYeVnDa9QlbkB8aoQVnDUmm+p36MizQpshTQBEQqDBozwd1wJMErJlIIba ozkF63/2/PzsdhCQQw0UGUPLWt51AWcYhblfhm90HgYMIcB5bv+AhXd+OMCfcE5I5UW0 hJlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DAchjLoGp53ThJdxxXYtoXfJ80Q4DYb4SAa6+caQEjY=; b=aol0/4VipllausrnxPkqm2vYlytaFZRLYIgGf5TIJnR8etdNAH/JOVVuuZ0hI1bUiZ hT6V8/7A3YYohPXzZfpiI90j8I/YQWJKgmTVEpF5m8MQRUOiqHFBMhdIRUVkjv7+2f0r 9NTYfxQP2MelUi2yE40BM6R6JZ39kDZlyhmBpLj9bdIegBh7iW3meP96rcvXnGbcWWue KXLRLWoSJQ6zQn/oek3xgKMNBE8Y/6nrSGXegHoY38K9didbJz8ga9790cIQxB53s3BL J/LevhrHYEgRZeh4k7ZgOKhljLLYF2olchsty9Ye7gL2pDyRfZPtcLILk5XtEhJzqUV2 YeFA== X-Gm-Message-State: APjAAAURRCdvmtci82HAEEPS/Rr2gBzRyLtlypivw2bLDCGSCMQhQbOa DMXa/nkvR08usKYcLbEvSbduWg== X-Google-Smtp-Source: APXvYqz6sc/3QmZZznQnarPJoaco5wIiNAyu1Ktb9fX4GSZIy5IQZ+V+MKhTTcgjM221UKbgx9UA1A== X-Received: by 2002:a05:600c:2388:: with SMTP id m8mr2884140wma.23.1561560464072; Wed, 26 Jun 2019 07:47:44 -0700 (PDT) Received: from mai.imgcgcw.net (26.92.130.77.rev.sfr.net. [77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:43 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 19/25] clocksource/drivers/tegra: Drop unneeded typecasting in one place Date: Wed, 26 Jun 2019 16:46:45 +0200 Message-Id: <20190626144651.16742-19-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko There is no need to cast void because kernel allows to do that without a warning message from a compiler. Acked-by: Jon Hunter Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index 41257f89a216..f7a09d88dacb 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -83,7 +83,7 @@ static int tegra_timer_set_periodic(struct clock_event_device *evt) static irqreturn_t tegra_timer_isr(int irq, void *dev_id) { - struct clock_event_device *evt = (struct clock_event_device *)dev_id; + struct clock_event_device *evt = dev_id; void __iomem *reg_base = timer_of_base(to_timer_of(evt)); writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); From patchwork Wed Jun 26 14:46:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122865 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Nqrwya3T"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Ym915M33z9sLt for ; Thu, 27 Jun 2019 00:47:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728350AbfFZOrs (ORCPT ); Wed, 26 Jun 2019 10:47:48 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:53195 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728360AbfFZOrs (ORCPT ); Wed, 26 Jun 2019 10:47:48 -0400 Received: by mail-wm1-f66.google.com with SMTP id s3so2402923wms.2 for ; Wed, 26 Jun 2019 07:47:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v71fsQ7QyhP31JuRKVVsI8LiqKCJEYn7OMik1mGoLt0=; b=Nqrwya3TRyYnvJF3BQnilU92ZO48VVczT3CW9qcki1wMMC070R130zAjj4vWi72UUA aF6EIxrsr6nTpaGj2OQnsR9EC3Fg1DkCqBbRXNqDeiBtef+8IqQHuFV0FRLYuozla0dD +DgdswZjhqmGsad9IhlqOoJGbaG96atZOLESva79eNieLVNyUtW48IWgy9pw1ob7viTf 4gTZj1d2C0Rv/gikCOyGn/0Ckx6311/9a+h3HrnQ4xoUQUtrbOTydqtg/bXtOJu82oNu 7o7DE3NGslZ47KvK/yKDfRfxVcTXlYzBMRvCfODSU+TIDXTV8jWrXM0z5WlEVyhM/DtU wCLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v71fsQ7QyhP31JuRKVVsI8LiqKCJEYn7OMik1mGoLt0=; b=p4jD5sXOAzGbt73NENarYTlP4E7xzhNOY/hkCMKqTG2chAi4wWUrwqpqipj8sadmDk L5VFdj4qKXHqam/JWGbcjGD3DIYXRklXK81XuIo8/HdP6npUKnbJksqXG7gYooTd7UBx hcc1TcDL4fWQyrlU+C0839NsJ4FlJma+HsxnR3HYqwbLYSStJZ5RU5d1utq8cQLJBO/x TL5Vz8ZNUGMYRYpCO5/QUala3V0UP3M9R+3C7ZDDgEt2HbsyY0DqMPWYsfreDEyVeCQk DUu0OqH9n802OGiOG28GgPcUYT8+X5I6VxqxGKkmF8rWvNTWSkecdeFpK/3SxAuV/iRG a4Vg== X-Gm-Message-State: APjAAAWZBtyrjGldl2CEgF/07c1muxxspV88GjhZdld6B6YJMpgjHwGR j6qNxBakFy3UqNL47l2OqW7R5w== X-Google-Smtp-Source: APXvYqynXaSxwzqZFYAA9jYXWlOtz58xh3TiXT9jAlfRs+jFVS5cBmnHG9QBgPNkMiFQIpEZ5XKzAw== X-Received: by 2002:a05:600c:228b:: with SMTP id 11mr3103332wmf.26.1561560465957; Wed, 26 Jun 2019 07:47:45 -0700 (PDT) Received: from mai.imgcgcw.net (26.92.130.77.rev.sfr.net. [77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:44 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 20/25] clocksource/drivers/tegra: Add verbose definition for 1MHz constant Date: Wed, 26 Jun 2019 16:46:46 +0200 Message-Id: <20190626144651.16742-20-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko Convert all 1MHz literals to a verbose constant for better readability. Suggested-by: Daniel Lezcano Acked-by: Jon Hunter Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index f7a09d88dacb..cc90f22c559b 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -46,6 +46,8 @@ #define TIMER1_IRQ_IDX 0 #define TIMER10_IRQ_IDX 10 +#define TIMER_1MHz 1000000 + static u32 usec_config; static void __iomem *timer_reg_base; @@ -160,7 +162,7 @@ static unsigned long tegra_delay_timer_read_counter_long(void) static struct delay_timer tegra_delay_timer = { .read_current_timer = tegra_delay_timer_read_counter_long, - .freq = 1000000, + .freq = TIMER_1MHz, }; #endif @@ -226,7 +228,7 @@ static inline unsigned long tegra_rate_for_timer(struct timer_of *to, * parent clock. */ if (tegra20) - return 1000000; + return TIMER_1MHz; return timer_of_rate(to); } @@ -315,11 +317,11 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, } } - sched_clock_register(tegra_read_sched_clock, 32, 1000000); + sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz); ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", 1000000, - 300, 32, clocksource_mmio_readl_up); + "timer_us", TIMER_1MHz, 300, 32, + clocksource_mmio_readl_up); if (ret) pr_err("failed to register clocksource: %d\n", ret); From patchwork Wed Jun 26 14:46:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122869 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="SE0BjstO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Ym9q3ZkHz9sNl for ; Thu, 27 Jun 2019 00:48:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728137AbfFZOsa (ORCPT ); Wed, 26 Jun 2019 10:48:30 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:39964 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728368AbfFZOrt (ORCPT ); Wed, 26 Jun 2019 10:47:49 -0400 Received: by mail-wr1-f68.google.com with SMTP id p11so3065697wre.7 for ; Wed, 26 Jun 2019 07:47:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JJjc1JQr3nhAuAaXUtH5dZp0geSFnyJ4aiNQzKjFRos=; b=SE0BjstOMK/odoLOHXMPQOO9gdXALfQsZWWqOLTLPHSVLSuGlYwN1oKzgxTyxImX5j d2xbYIRU58sAKJJ9lyP6oYLymRwHdnvCm8j1JjmUKESOLfHST5IrxCIKDJl2UieHTunP PRlvQJUSIZbCwWwwuDoJ9+NLBhQ1p/d1Pl2w+oNTBBJZQ6x8Ys/qlsv+qDeTJ/uQk7KB GOyOZv7c7MOnVo+4f8cFPLLD1G5PIXlDI56a+MQduJEb2gMFs5yFfyOeqCTCq76CDxcI jhHf6Ery9blBEbtUxXdBpUuIjyXW/kCuvxE6DiHVioqlZamtBcXpzJ7zlwHGos/xH5A1 xS8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JJjc1JQr3nhAuAaXUtH5dZp0geSFnyJ4aiNQzKjFRos=; b=DDW2J9BrjQSNBne0snbiLQoDS6twJmZ+qIreOy4MONEAoIPyIN3cKk+5vO8CBDet6l q68k0ZclKN6Lcj74eQCa61qUW/wyGYZQLUj7mgRSyAIxeDDeBCLHILHCJNH8KopdUpBS 2kKpqHOa9neRam3ic9dtoYuI6FK5lzxhPmsk5HnoNcFDVUMUnap0kG8yROrvBTxHdIOV QJJBjYRRa97z6XBJ0kxjhqbKqbqB5J7vh6g2yOBIDmCTYk/qT4mx/vXBy2V1ZGOWYd7D 87clftvx7OASV+11EcboOd7c2QV2qRQWa8k+WnPv8s2kcN+JfR60fKKKZy569g18XVWE qsFA== X-Gm-Message-State: APjAAAVyGKfa5TEx253D63H6Qrfzzi8QZTXoGaMMSQkomRo64tCvMNjY ZgrFbNNETzJxnw/mfPHWoJ/VAA== X-Google-Smtp-Source: APXvYqyxEgDaR8PechUZppgNIlEgcO4mmIWW8DDVfGD7qzqiOIaUPSy/TqVv7qajfeQPaYi9BFKBJQ== X-Received: by 2002:a5d:4a43:: with SMTP id v3mr4116991wrs.151.1561560467437; Wed, 26 Jun 2019 07:47:47 -0700 (PDT) Received: from mai.imgcgcw.net (26.92.130.77.rev.sfr.net. [77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:46 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 21/25] clocksource/drivers/tegra: Restore base address before cleanup Date: Wed, 26 Jun 2019 16:46:47 +0200 Message-Id: <20190626144651.16742-21-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko We're adjusting the timer's base for each per-CPU timer to point to the actual start of the timer since device-tree defines a compound registers range that includes all of the timers. In this case the original base need to be restore before calling iounmap to unmap the proper address. Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index cc90f22c559b..8e70f38f1898 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -347,6 +347,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, irq_dispose_mapping(cpu_to->clkevt.irq); } } + + to->of_base.base = timer_reg_base; out: timer_of_cleanup(to); From patchwork Wed Jun 26 14:46:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122866 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="h57Q8Ma7"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Ym955P6xz9s8m for ; Thu, 27 Jun 2019 00:47:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728385AbfFZOrv (ORCPT ); Wed, 26 Jun 2019 10:47:51 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:39232 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728377AbfFZOrv (ORCPT ); Wed, 26 Jun 2019 10:47:51 -0400 Received: by mail-wr1-f68.google.com with SMTP id x4so3065546wrt.6 for ; Wed, 26 Jun 2019 07:47:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NrTLjCEQJCPZZPBocCnR2gGFul+oEek89zztJZXdth0=; b=h57Q8Ma7QA2S62Pumxd4IWE4LAB/INnqTPU1uEJawVth6Pq50X9neJBTKuh6OyAZ7m oY3MP7K3tFa4H34C2hQwW9heisfx5XMpEMRhGyeR6xv9XEtdpCjzwnZkDMKjAMHr50s5 WhjUdPc/yoUIEzD9s2ev5j9N+GANAzVh/MIDS4H2+R3BV6OCwYfyeoqwESRKPE6ZouHu r1qBBrTd9t1rw6QjMR0EzjZAQhCKmpfvg8D1oNWDXqOFAAj7mdPB0dxCkHsI6ihhN6Uv Fda5MbwzojrblJOZCWTkiT5quzNRRxJQx6RGumw/5Ji06gyUmki+3DefjcMtveHEDNf7 p7pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NrTLjCEQJCPZZPBocCnR2gGFul+oEek89zztJZXdth0=; b=IiB2ALsPG1Y6PZiAXk9M8nzGNSF7yy1AVbQ7vzvf+i1ozKbaesdcKnLJv9Gozh/YZT YLxRj7TUhUE/RPt48/NzR+qjzb5QR5r6+KX/ILc/qh8DD6gvMIrLkDvwobAP7CG4t6Vb ZevBEFEDN4D8wtxuVq1PTxQSODFZ26YgoZB+nyzMAzphqy/pjWV9x6FX9cOfdkEJByq0 2onY5g5Nx0782UP4pLbNHqRhTXxbGjJpocJOIJDuqGb2cb8Ddr5vn0zMDOS9iUiWQIJ4 2eai6zjnGYRrLjYAqNm0b3fok88SU+q0aldy1IUJnU98fW34D7ojOdTF3ApiTRbt8ffp NUPg== X-Gm-Message-State: APjAAAWXUOwSWWECADObcARJOu/Yw5DC0AW1jNMOttRPk0isjnAT2MRz HkpQXZy3uJ9JW72b+k/yB7YDWQ== X-Google-Smtp-Source: APXvYqxGpQiv5E4WGjCIQKYH9Y+gRBsbnKqD8dw94pr4vFwmPC93zjhp1ZIbYHoWZw3keMJc9Bn4Yg== X-Received: by 2002:a5d:5112:: with SMTP id s18mr3803585wrt.111.1561560468935; Wed, 26 Jun 2019 07:47:48 -0700 (PDT) Received: from mai.imgcgcw.net (26.92.130.77.rev.sfr.net. [77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:48 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 22/25] clocksource/drivers/tegra: Cycles can't be 0 Date: Wed, 26 Jun 2019 16:46:48 +0200 Message-Id: <20190626144651.16742-22-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko Tegra's timer uses n+1 scheme for the counter, i.e. timer will fire after one tick if 0 is loaded. The minimum and maximum numbers of oneshot ticks are defined by clockevents_config_and_register(min, max) invocation and the min value is set to 1 tick. Hence "cycles" value can't ever be 0, unless it's a bug in clocksource core. Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index 8e70f38f1898..a907e71065bd 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -56,9 +56,16 @@ static int tegra_timer_set_next_event(unsigned long cycles, { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel_relaxed(TIMER_PTV_EN | - ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ - reg_base + TIMER_PTV); + /* + * Tegra's timer uses n+1 scheme for the counter, i.e. timer will + * fire after one tick if 0 is loaded. + * + * The minimum and maximum numbers of oneshot ticks are defined + * by clockevents_config_and_register(1, 0x1fffffff + 1) invocation + * below in the code. Hence the cycles (ticks) can't be outside of + * a range supportable by hardware. + */ + writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV); return 0; } From patchwork Wed Jun 26 14:46:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1122867 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="hjvzg9a9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Ym962kt8z9sNm for ; Thu, 27 Jun 2019 00:47:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728388AbfFZOrx (ORCPT ); Wed, 26 Jun 2019 10:47:53 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:54839 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728383AbfFZOrw (ORCPT ); Wed, 26 Jun 2019 10:47:52 -0400 Received: by mail-wm1-f65.google.com with SMTP id g135so2403182wme.4 for ; Wed, 26 Jun 2019 07:47:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nq1XbTkt1vTkv4HhT7D+cz8CUmDBD84eY2DPwK+R49I=; b=hjvzg9a9a0GenL06gSEprpW5hS+B+44Q/gkHp+AUPMnoLW1Bd05iBosXOcZ1GGfuxp WPTDCKLDCOMesFSuks/dgz8jra2jLk7kiD4Vqen8neczpsp4q6FrKNyFeEp0C+uTAe6j 2Zi52MITdf4b6wUq2zeEwfI7dzy4PAlW9qpYa15Wi9tH5qfIyIukx8f2t/+fJhmAPMsM 6wT5N8qDxTetD43SLjJFvuWQsIjygRQ/9UJw6v/8UKz8lWKvxNj4F3/h1nckZ4BKKSAj W3JEHme142is+z+CQzKpOiD25ypNIxDrQI5UPw5rjI3dNkDUzuK0SixBohvRtoeffTm8 yYnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nq1XbTkt1vTkv4HhT7D+cz8CUmDBD84eY2DPwK+R49I=; b=uFaTSRY9o6POs/ksbZGGpqlmjtwvzMDp4HCov/cwWfXoMqcmo7OD6FDg+zPaLqrhs9 UAdCrIH08hZJzVHcdqdbyjIUU8f8K58/gIbhSYMFB/0zGAEh/qzInRmd/KHJ9Dkt9nC7 /+SK/HlsnSUOqUWlDlKO5AqboF+J0Rp87TR9lk811DvHgouB8m9uoBplSWoN3mdayauQ 9YhML6DUTr6lkS/oez7msUz5KrJ1L9dgCIsaN0s/nzlu1q8811djM+18jNBJcbpj8pMN n1bdFMAGVdwKaLrhempEDKfXkXyWwxCdvWc/zGBAIPaqA8odPDpiWu/lGniJHxVZunDU B6Cg== X-Gm-Message-State: APjAAAX/F42S/CGVkAbDLVZu2DomdO6TErTIQqB9nwAkWaNPubL7sn7A zkbPVnVEPsZ+MsMxZCbb53bg3Q== X-Google-Smtp-Source: APXvYqy/gyXrr5TSHewUeTIot1Go2roqfk1bh0jcUiD6g99PjFboR54K2WyI/H9X9RIhFOcEYYsI4w== X-Received: by 2002:a1c:1d83:: with SMTP id d125mr2999871wmd.63.1561560470791; Wed, 26 Jun 2019 07:47:50 -0700 (PDT) Received: from mai.imgcgcw.net (26.92.130.77.rev.sfr.net. [77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:50 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 23/25] clocksource/drivers/tegra: Set up maximum-ticks limit properly Date: Wed, 26 Jun 2019 16:46:49 +0200 Message-Id: <20190626144651.16742-23-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Dmitry Osipenko Tegra's timer has 29 bits for the counter and for the "load" register which sets counter to a load-value. The counter's value is lower than the actual value by 1 because it starts to decrement after one tick, hence the maximum number of ticks that hardware can handle equals to 29 bits + 1. Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index a907e71065bd..e9635c25eef4 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -139,9 +139,17 @@ static int tegra_timer_setup(unsigned int cpu) irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); + /* + * Tegra's timer uses n+1 scheme for the counter, i.e. timer will + * fire after one tick if 0 is loaded and thus minimum number of + * ticks is 1. In result both of the clocksource's tick limits are + * higher than a minimum and maximum that hardware register can + * take by 1, this is then taken into account by set_next_event + * callback. + */ clockevents_config_and_register(&to->clkevt, timer_of_rate(to), 1, /* min */ - 0x1fffffff); /* 29 bits */ + 0x1fffffff + 1); /* max 29 bits + 1 */ return 0; }