From patchwork Tue Jun 18 14:53:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1118003 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-503183-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="L4qT69dn"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45Srg16mL2z9sDX for ; Wed, 19 Jun 2019 00:53:17 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=SrQZqVSi/4pSovkGJYI0r+0FfgafBm425OPPS3vMONYyZL5F5TNln Nyq/kALrbnOptBr1ksjFNHCk3csPRhIFfxsEAYoP7jmX1pjOTy63cXGm6wqJYhGo BvOKWCEli2iaLEXwBPwSdwsL8dSillsSk/uJk//T0nCXXPi3+xJKuI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=XO7XrH6ihdlhNrPvm35X4j8iUzw=; b=L4qT69dnO+dtYKgOSSsM u9Strj8Yl0QHxrCgRjqewB7GA7HboBaM6+PhY5KEfH+IpQkHD2v/JS11drJCWk83 c83ibZkfqeb0jTfELbn641K9iaP++wu8/TJkoMZQ4hnCpoYKfhBp81GBIKLdA8ku wLBZpFAtMEQNHtrDjdGnNoA= Received: (qmail 99531 invoked by alias); 18 Jun 2019 14:53:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 99520 invoked by uid 89); 18 Jun 2019 14:53:10 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-5.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, MEDICAL_SUBJECT autolearn=ham version=3.3.1 spammy=zip, REV X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 18 Jun 2019 14:53:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 553E92B for ; Tue, 18 Jun 2019 07:53:07 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F10563F718 for ; Tue, 18 Jun 2019 07:53:06 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Tabify aarch64-sve.md Date: Tue, 18 Jun 2019 15:53:05 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Tested on aarch64-linux-gnu (with and without SVE). Applied as r272426. Richard 2019-06-18 Richard Sandiford gcc/ * config/aarch64/aarch64-sve.md: Tabify file. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-06-18 15:42:40.859631868 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-06-18 15:43:09.591393527 +0100 @@ -72,7 +72,7 @@ (define_expand "mov" head of the file) and increases the addressing choices for little-endian. */ if ((MEM_P (operands[0]) || MEM_P (operands[1])) - && can_create_pseudo_p ()) + && can_create_pseudo_p ()) { aarch64_expand_sve_mem_move (operands[0], operands[1], mode); DONE; @@ -88,7 +88,7 @@ (define_expand "mov" /* Optimize subregs on big-endian targets: we can use REV[BHW] instead of going through memory. */ if (BYTES_BIG_ENDIAN - && aarch64_maybe_expand_sve_subreg_move (operands[0], operands[1])) + && aarch64_maybe_expand_sve_subreg_move (operands[0], operands[1])) DONE; } ) @@ -100,7 +100,7 @@ (define_expand "mov" (define_insn_and_split "*aarch64_sve_mov_subreg_be" [(set (match_operand:SVE_ALL 0 "aarch64_sve_nonimmediate_operand" "=w") (unspec:SVE_ALL - [(match_operand:VNx16BI 1 "register_operand" "Upl") + [(match_operand:VNx16BI 1 "register_operand" "Upl") (match_operand 2 "aarch64_any_register_operand" "w")] UNSPEC_REV_SUBREG))] "TARGET_SVE && BYTES_BIG_ENDIAN" @@ -147,7 +147,7 @@ (define_insn "*aarch64_sve_mov_be" (define_expand "aarch64_sve_reload_be" [(parallel [(set (match_operand 0) - (match_operand 1)) + (match_operand 1)) (clobber (match_operand:VNx16BI 2 "register_operand" "=Upl"))])] "TARGET_SVE && BYTES_BIG_ENDIAN" { @@ -1442,24 +1442,24 @@ (define_insn "*cmp_cc" (define_insn_and_split "*pred_cmp_combine" [(set (match_operand: 0 "register_operand" "=Upa, Upa") (and: - (unspec: - [(match_operand: 1) - (SVE_INT_CMP: - (match_operand:SVE_I 2 "register_operand" "w, w") - (match_operand:SVE_I 3 "aarch64_sve_cmp__operand" ", w"))] - UNSPEC_MERGE_PTRUE) - (match_operand: 4 "register_operand" "Upl, Upl"))) + (unspec: + [(match_operand: 1) + (SVE_INT_CMP: + (match_operand:SVE_I 2 "register_operand" "w, w") + (match_operand:SVE_I 3 "aarch64_sve_cmp__operand" ", w"))] + UNSPEC_MERGE_PTRUE) + (match_operand: 4 "register_operand" "Upl, Upl"))) (clobber (reg:CC CC_REGNUM))] "TARGET_SVE" "#" "&& 1" [(parallel [(set (match_dup 0) - (and: - (SVE_INT_CMP: - (match_dup 2) - (match_dup 3)) - (match_dup 4))) + (and: + (SVE_INT_CMP: + (match_dup 2) + (match_dup 3)) + (match_dup 4))) (clobber (reg:CC CC_REGNUM))])] ) @@ -2730,8 +2730,8 @@ (define_expand "vec_unpack_flo a ZIP whose first operand is zero. */ rtx temp = gen_reg_rtx (VNx4SImode); emit_insn (( - ? gen_aarch64_sve_zip2vnx4si - : gen_aarch64_sve_zip1vnx4si) + ? gen_aarch64_sve_zip2vnx4si + : gen_aarch64_sve_zip1vnx4si) (temp, operands[1], operands[1])); rtx ptrue = aarch64_ptrue_reg (VNx2BImode); emit_insn (gen_aarch64_sve_vnx4sivnx2df2 (operands[0],