From patchwork Tue Jun 18 14:51:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1118000 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-503182-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ovUT5EEg"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45SrdW38R6z9sBp for ; Wed, 19 Jun 2019 00:51:58 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=tm+nJfnNoWkyq/4TZOyJVjANbrbaiZpBJysu9W50y20xTEpjn2kXi MKaEfy5qo/B8J96T9UHwMbcPp/6ztcbD6Lo/zOavBrMv7Ob3Rhv1tEf8TuN96wat cc565e/Plp4rdZkTd4SXZnICB+aXbPLEdYskrcim6XLcbNpWmhECPU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=TCWivuIAsmBMYiIloKUCCpro6ag=; b=ovUT5EEgAwNOULme4RCr BlEZPqUl2+Dxt3YweYvAO3JggPF4GCGP+pk0RBRuLNPi47K+pMqZrUdLdl14eSXt gjVm2nTuJTDQbQ+t2jLE6LvHi/aDSIL5df7ujgtEyCw6gW4pTp8iQFLXE4DSTpTN KwGGi6fn7dSm7ilVJDzifCE= Received: (qmail 94390 invoked by alias); 18 Jun 2019 14:51:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 94304 invoked by uid 89); 18 Jun 2019 14:51:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-7.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 18 Jun 2019 14:51:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 97BD72B for ; Tue, 18 Jun 2019 07:51:35 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3E60C3F718 for ; Tue, 18 Jun 2019 07:51:35 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [AArch64] Factor out pfalse predicate creation Date: Tue, 18 Jun 2019 15:51:34 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Following on from the previous ptrue patch. Tested on aarch64-linux-gnu (with and without SVE). Applied as r272425. Richard 2019-06-18 Richard Sandiford gcc/ * config/aarch64/aarch64-protos.h (aarch64_pfalse_reg): Declare. * config/aarch64/aarch64.c (aarch64_pfalse_reg): New function. * config/aarch64/aarch64-sve.md: Use it. Index: gcc/config/aarch64/aarch64-protos.h =================================================================== --- gcc/config/aarch64/aarch64-protos.h 2019-06-18 15:42:18.535817057 +0100 +++ gcc/config/aarch64/aarch64-protos.h 2019-06-18 15:42:40.859631868 +0100 @@ -521,6 +521,7 @@ void aarch64_err_no_fpadvsimd (machine_m void aarch64_expand_epilogue (bool); void aarch64_expand_mov_immediate (rtx, rtx, rtx (*) (rtx, rtx) = 0); rtx aarch64_ptrue_reg (machine_mode); +rtx aarch64_pfalse_reg (machine_mode); void aarch64_emit_sve_pred_move (rtx, rtx, rtx); void aarch64_expand_sve_mem_move (rtx, rtx, machine_mode); bool aarch64_maybe_expand_sve_subreg_move (rtx, rtx); Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2019-06-18 15:42:18.539817024 +0100 +++ gcc/config/aarch64/aarch64.c 2019-06-18 15:42:40.863631835 +0100 @@ -2467,6 +2467,15 @@ aarch64_ptrue_reg (machine_mode mode) return force_reg (mode, CONSTM1_RTX (mode)); } +/* Return an all-false predicate register of mode MODE. */ + +rtx +aarch64_pfalse_reg (machine_mode mode) +{ + gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL); + return force_reg (mode, CONST0_RTX (mode)); +} + /* Return true if we can move VALUE into a register using a single CNT[BHWD] instruction. */ Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-06-18 15:42:18.535817057 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-06-18 15:42:40.859631868 +0100 @@ -488,7 +488,7 @@ (define_expand "vec_extract" { /* The last element can be extracted with a LASTB and a false predicate. */ - rtx sel = force_reg (mode, CONST0_RTX (mode)); + rtx sel = aarch64_pfalse_reg (mode); emit_insn (gen_extract_last_ (operands[0], sel, operands[1])); DONE; }