From patchwork Tue Jun 18 09:17:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1117751 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="oPh831at"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="CoPtXR9J"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45SjCq5zMjz9s7h for ; Tue, 18 Jun 2019 19:17:43 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 80F8DC21F68; Tue, 18 Jun 2019 09:17:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BE07CC21E6A; Tue, 18 Jun 2019 09:17:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1B716C21E6A; Tue, 18 Jun 2019 09:17:38 +0000 (UTC) Received: from esa6.hgst.iphmx.com (esa6.hgst.iphmx.com [216.71.154.45]) by lists.denx.de (Postfix) with ESMTPS id 03E22C21E2B for ; Tue, 18 Jun 2019 09:17:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1560849458; x=1592385458; h=from:to:cc:subject:date:message-id: content-transfer-encoding:mime-version; bh=Ze35jeN4sEjfKGRjYXZPP4wOi4kbo9GsewglvBgGzmY=; b=oPh831atnXNNP5ddC17bUJIJtxh1KPebXeZyfdlylpVa8N1w4NIL3DQa a6U/1GYwQ1Hj8JLtfr7J44/micTInS9/xgms8ZMv3rgnwGPLR3W/jZDgC xJK4eOUMN8wlaDh6ddxnZIc2r/odmZAyrC/V3XKnY2ZwNknsOhtDosQYb slFl/ZTSfP0BWrkp2tcramDwWdm7ceD2MwMv4Nox9/o8ANhvHrWmjboPK 4maIVXUa7ITAGGnCdWhqHRdE966giJcS0pskB80+W7Bwn+tH/IerGcywU Ns+zjL8AXK4FcJ1B16tAyXSRaAN8zLQJYhOcLhlip8xoZxwf3uVshMOas g==; X-IronPort-AV: E=Sophos;i="5.63,388,1557158400"; d="scan'208";a="112489755" Received: from mail-co1nam04lp2058.outbound.protection.outlook.com (HELO NAM04-CO1-obe.outbound.protection.outlook.com) ([104.47.45.58]) by ob1.hgst.iphmx.com with ESMTP; 18 Jun 2019 17:17:21 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Ze35jeN4sEjfKGRjYXZPP4wOi4kbo9GsewglvBgGzmY=; b=CoPtXR9JGGdww/FfYhVOz52OE7HnDwWXdwGeoQzhkn128YI9SKreMcgEP0hPA8M7mF1xQq9wHvIfiO8uJ9lms7W8hfhC1aFyiR45IFd83naYQNeBHW6zzo0mZuSyVow957hSW6Vcdq8NbkhvOk+Roowc3ZjH7W0uQKEwSG51cq0= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB5485.namprd04.prod.outlook.com (20.178.248.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1987.15; Tue, 18 Jun 2019 09:17:19 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::98ab:5e60:9c5c:4e0e]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::98ab:5e60:9c5c:4e0e%7]) with mapi id 15.20.1965.017; Tue, 18 Jun 2019 09:17:19 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Thread-Topic: [PATCH] platform: sifive: Embed unleashed DTS due to broken DT bindings Thread-Index: AQHVJbahcjQTO8zjVkC5S/qK717+MQ== Date: Tue, 18 Jun 2019 09:17:19 +0000 Message-ID: <20190618091649.3022-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR0101CA0062.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::24) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [129.253.179.161] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e6e3452e-2d1d-43a8-f0e3-08d6f3cdc33a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020); SRVR:MN2PR04MB5485; x-ms-traffictypediagnostic: MN2PR04MB5485: wdcipoutbound: EOP-TRUE x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:569; x-forefront-prvs: 007271867D x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(396003)(366004)(376002)(346002)(39860400002)(136003)(199004)(189003)(7736002)(4326008)(8936002)(1076003)(2906002)(14454004)(72206003)(68736007)(478600001)(66066001)(476003)(50226002)(44832011)(486006)(2616005)(316002)(54906003)(110136005)(71190400001)(71200400001)(6116002)(3846002)(52116002)(186003)(99286004)(26005)(6436002)(36756003)(102836004)(6486002)(53936002)(6512007)(81166006)(6506007)(386003)(8676002)(6636002)(81156014)(14444005)(256004)(25786009)(19627235002)(305945005)(66446008)(64756008)(66556008)(66476007)(66946007)(86362001)(5660300002)(73956011); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB5485; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: hp61zUpXW70iqGuiu+72utmpMjm2GeA1fXf2blt2RoMmNlSnGe8DINte9a4yCtk5TaQ12iRtszMzRxoJkxGPCYM90WVHPC73xmcFebaIgL9WNKI9DjJSuY3sTX53GtcyQW6INAmEnZkfYnSNMy5RSayATALxgbQYncr6E3ir8Bln1rBcvBLeu19thbAQB052NSAiiZmIW5QL46d4ARSS8bvtn4d1ah5s5m2SUeqg8xVlPyZKNqDNc2SEWqdweTosxnXu8Ko4zOJFCbLQpc74c4shJHx/eLu72Wt2ODBOwK3QNMO7ES/RSP2JBSUykrePw2rK+Vf3T93AY2SabgnoMANJTwO9H5gHjeIs9y+Da0GdbY9mLrwn/s82tPNv84jwyoliQK/hZyYOGRWPoE4/7bwvXKF3tRYKnQtAgt4TzLQ= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: e6e3452e-2d1d-43a8-f0e3-08d6f3cdc33a X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Jun 2019 09:17:19.4615 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Anup.Patel@wdc.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5485 Cc: Damien Le Moal , Palmer Dabbelt , U-Boot Mailing List Subject: [U-Boot] [PATCH] platform: sifive: Embed unleashed DTS due to broken DT bindings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The DT bindings of upstream linux kernel have diverged and are not backward compatible so we embed a DTB in FW_PAYLOAD which follows upstream linux kernel DT bindings. The U-Boot drivers will also be fixed to use the updated DT bindings as-per upstream Linux kernel. By embedding updated DTS in FW_PAYLOAD, we allow users to easily migrate to update DT bindings using OpenSBI+U-Boot. Signed-off-by: Anup Patel --- platform/sifive/fu540/HiFiveUnleashed.dts | 269 ++++++++++++++++++++++ platform/sifive/fu540/config.mk | 1 + 2 files changed, 270 insertions(+) create mode 100644 platform/sifive/fu540/HiFiveUnleashed.dts diff --git a/platform/sifive/fu540/HiFiveUnleashed.dts b/platform/sifive/fu540/HiFiveUnleashed.dts new file mode 100644 index 0000000..13ea412 --- /dev/null +++ b/platform/sifive/fu540/HiFiveUnleashed.dts @@ -0,0 +1,269 @@ +/dts-v1/; + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "/soc/serial@10010000:115200"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0", "riscv,plic0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + gemgxlclk: cadence-gemgxl-mgmt@100a0000 { + compatible = "sifive,cadencegemgxlmgmt0"; + reg = <0x0 0x100a0000 0x0 0x1000>; + #clock-cells = <0x0>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci 3>; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci 3>; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci 3>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; + }; + ethernet@10090000 { + compatible = "cdns,macb"; + interrupt-parent = <&plic0>; + interrupts = <0x35>; + reg = <0x0 0x10090000 0x0 0x2000>; + reg-names = "control"; + local-mac-address = [70 b3 d5 92 f0 1f]; + phy-mode = "gmii"; + clock-names = "pclk", "hclk", "tx_clk"; + clocks = <&prci 0x1 &prci 0x1 &gemgxlclk>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + ethernet-phy@0 { + reg = <0x0>; + }; + }; + }; +}; diff --git a/platform/sifive/fu540/config.mk b/platform/sifive/fu540/config.mk index fbb5db8..0e02d69 100644 --- a/platform/sifive/fu540/config.mk +++ b/platform/sifive/fu540/config.mk @@ -27,6 +27,7 @@ FW_JUMP_FDT_ADDR=0x82200000 FW_PAYLOAD=y FW_PAYLOAD_OFFSET=0x200000 FW_PAYLOAD_FDT_ADDR=0x82200000 +FW_PAYLOAD_FDT=HiFiveUnleashed.dtb # External Libraries to include PLATFORM_INCLUDE_LIBFDT=y