From patchwork Tue Jun 18 07:56:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yash Shah X-Patchwork-Id: 1117713 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="MND8vxaD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgT04RTjz9s9y for ; Tue, 18 Jun 2019 17:59:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728765AbfFRH67 (ORCPT ); Tue, 18 Jun 2019 03:58:59 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:41271 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726007AbfFRH67 (ORCPT ); Tue, 18 Jun 2019 03:58:59 -0400 Received: by mail-pf1-f195.google.com with SMTP id m30so7171209pff.8 for ; Tue, 18 Jun 2019 00:58:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KNKUdapm3qNhe7MOmKoE4hXvbJ/LomCozufosFqpC3o=; b=MND8vxaDJbYE1BrCgIXbMpEu9+Rt1KUTQ5E7VltY+/32k2ApcT4xKFQEjjrMzz8z9d 6/kd8Ykct6sP4CnWhstkw0+maJmuiwXA/qbVuFUQDVoQgKR9kMcsuhyjnZX6o5sKf1Lo CR01oHYMybhZcfIHN8YqUs3xGAmjnIFIoWPvMudHOUwR7XNDRGB4sj7DNMFN0V2fwhg5 76D8Mnip0gAVdxVXdwnNQagborQ7lvU+c4XFtPfHJbIUcpRJ/j5deqKg1/NgfQumZI3r Al4Hm3kyD8l8eJt0u6r+LujqQWAWgMi6GJzXqyvI7R1gUsufdzDHj1hcEU4XDEwTdLfU 7IRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KNKUdapm3qNhe7MOmKoE4hXvbJ/LomCozufosFqpC3o=; b=YxK3+JNf7zUv9NOl6UpvMo6s678CzeQ2w9zl+5+b0+tZCPJFBmPh+c0+UgKKWj2FPO FqBvCYBK2SxmTUwPe2Z7685ffNbUEJg+UfnMhTdOzZLKTUj7Zq/GqoNKI+mI1PdyYM8c JemGJsr5ZafJ7+7/5n6G+8hm9bXoOKb/Jyl2Bc0T813lEDXEsoF6t1C1tkIrRDzMf3Gg fZPfLYcwHr76QZes9MRXdsxJhrscrLBQm2GCLSp7AFFFTSxZd3CN9WxPZBRFR0r1y6YO 4yApmUw+8bUhBZpmBHdQ2F+M/yV58mZOJGdpN8ONYP+SFozDw8EkNqLUhEhRJxeMekZR LDEg== X-Gm-Message-State: APjAAAVrT7e0cB0KPm0B/cOBFTQJmciRNJAq656zCBZ2Re0xBoL/KgpO 9Q7F/0FgcvRrane8ReOe9FMywOTrUqg= X-Google-Smtp-Source: APXvYqzcXM1piGFfZULbOjP6OTb3aCFfIxUeCDqceRMd3JQYSPXGy8BeEYnBvuiaVYY8kAyDUUZbeg== X-Received: by 2002:a17:90a:228b:: with SMTP id s11mr3597672pjc.23.1560844738927; Tue, 18 Jun 2019 00:58:58 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id b23sm15780499pfi.6.2019.06.18.00.58.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jun 2019 00:58:58 -0700 (PDT) From: Yash Shah To: davem@davemloft.net, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: robh+dt@kernel.org, mark.rutland@arm.com, nicolas.ferre@microchip.com, palmer@sifive.com, aou@eecs.berkeley.edu, paul.walmsley@sifive.com, ynezz@true.cz, sachin.ghadi@sifive.com, Yash Shah Subject: [PATCH v3 1/2] macb: bindings doc: add sifive fu540-c000 binding Date: Tue, 18 Jun 2019 13:26:07 +0530 Message-Id: <1560844568-4746-2-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1560844568-4746-1-git-send-email-yash.shah@sifive.com> References: <1560844568-4746-1-git-send-email-yash.shah@sifive.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add the compatibility string documentation for SiFive FU540-C0000 interface. On the FU540, this driver also needs to read and write registers in a management IP block that monitors or drives boundary signals for the GEMGXL IP block that are not directly mapped to GEMGXL registers. Therefore, add additional range to "reg" property for SiFive GEMGXL management IP registers. Signed-off-by: Yash Shah Reviewed-by: Paul Walmsley --- Documentation/devicetree/bindings/net/macb.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 9c5e944..63c73fa 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -15,8 +15,11 @@ Required properties: Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. + Use "sifive,fu540-macb" for SiFive FU540-C000 SoC. Or the generic form: "cdns,emac". - reg: Address and length of the register set for the device + For "sifive,fu540-macb", second range is required to specify the + address and length of the registers for GEMGXL Management block. - interrupts: Should contain macb interrupt - phy-mode: See ethernet.txt file in the same directory. - clock-names: Tuple listing input clock names. From patchwork Tue Jun 18 07:56:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yash Shah X-Patchwork-Id: 1117715 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="CpITDJOS"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SgTJ5j1mz9s4V for ; Tue, 18 Jun 2019 17:59:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728941AbfFRH7N (ORCPT ); Tue, 18 Jun 2019 03:59:13 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:43653 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726088AbfFRH7M (ORCPT ); Tue, 18 Jun 2019 03:59:12 -0400 Received: by mail-pl1-f195.google.com with SMTP id cl9so5352381plb.10 for ; Tue, 18 Jun 2019 00:59:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/jrd3s/iKTX2c/I3SubHklOtN5DS54hMul2SnpAlB8Y=; b=CpITDJOSYm8RcIGbV1tYVFtlDFEv32tHKsJO71gM2XD1Ys6kayjWp+xR8uThOV72SD IWoejCZR1yHV5DVapi5t5TG3QCHGCyvUag29VsirsRp9vPO2BoZZhvyqlMVKHNCTQp0D RdAG5YDXDlADm7qSNCLviKiFxPbZYSJbs85tSCHFr2QKvEvlMPWa6NQia/0YkeiUtxAP vDqOdkYrGjDezUpHVAILrhil/WXaiKwipKMvpQN/NySixhO44eHmzINme3W3x0Rr9ruL c1uELLhzg3exZZtWjwf8nc3d+QjnJ1JNNlFe79yV+LPJLrCiG36U2zC9GpdNClMge9pY rIsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/jrd3s/iKTX2c/I3SubHklOtN5DS54hMul2SnpAlB8Y=; b=n4UGAM4YaGY1/T77kZyCe4qUttFNqdoM7p3Y+yt+BBMBUtIwV+DAEFvMPk7iX9dYn4 vIzRbSBaUcryWVg0RJ7YW10NCGdZj+gOJfy/bWSeTWihltOIR86fL3fcAqs9usg6DLcS oj7INIlBVjJGxz88NgRBX7PO1z+Q6Onhel7fHdy9lgqsTmK2Bamlb9ZqxkskxWjHnj/M bZ6bZwkO0+gAeIc7kuqcv98dItSkywCB979yCSAPKntYXXtuqEV2AT+DVuBTaCYfrf4n vHkgWbeE89dkzy0xpCoQUJERKGVFW42pmNd50HVAWse5WJAHfHbn4RidavYzurCqVDVS yiCA== X-Gm-Message-State: APjAAAUOiOZ5pYSYO4Ons/Rfh9gEaHppR1zhAkRALRqkX1SYshHJEKGn c6Z4zZf88LUxMfMUO5L8mW6wVw== X-Google-Smtp-Source: APXvYqwCZBCZ0J2MB1oUE5IUA2MNsP43+KtavPEOD4A6TJBDqkdMtiy6p9u1gvTaF6f0IJXEgecvWA== X-Received: by 2002:a17:902:9a42:: with SMTP id x2mr96706221plv.106.1560844752166; Tue, 18 Jun 2019 00:59:12 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id b23sm15780499pfi.6.2019.06.18.00.59.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jun 2019 00:59:11 -0700 (PDT) From: Yash Shah To: davem@davemloft.net, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: robh+dt@kernel.org, mark.rutland@arm.com, nicolas.ferre@microchip.com, palmer@sifive.com, aou@eecs.berkeley.edu, paul.walmsley@sifive.com, ynezz@true.cz, sachin.ghadi@sifive.com, Yash Shah Subject: [PATCH v3 2/2] macb: Add support for SiFive FU540-C000 Date: Tue, 18 Jun 2019 13:26:08 +0530 Message-Id: <1560844568-4746-3-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1560844568-4746-1-git-send-email-yash.shah@sifive.com> References: <1560844568-4746-1-git-send-email-yash.shah@sifive.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The management IP block is tightly coupled with the Cadence MACB IP block on the FU540, and manages many of the boundary signals from the MACB IP. This patch only controls the tx_clk input signal to the MACB IP. Future patches may add support for monitoring or controlling other IP boundary signals. Signed-off-by: Yash Shah --- drivers/net/ethernet/cadence/macb_main.c | 123 +++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index c049410..15d0737 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include @@ -40,6 +41,15 @@ #include #include "macb.h" +/* This structure is only used for MACB on SiFive FU540 devices */ +struct sifive_fu540_macb_mgmt { + void __iomem *reg; + unsigned long rate; + struct clk_hw hw; +}; + +static struct sifive_fu540_macb_mgmt *mgmt; + #define MACB_RX_BUFFER_SIZE 128 #define RX_BUFFER_MULTIPLE 64 /* bytes */ @@ -3903,6 +3913,116 @@ static int at91ether_init(struct platform_device *pdev) return 0; } +static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return mgmt->rate; +} + +static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + if (WARN_ON(rate < 2500000)) + return 2500000; + else if (rate == 2500000) + return 2500000; + else if (WARN_ON(rate < 13750000)) + return 2500000; + else if (WARN_ON(rate < 25000000)) + return 25000000; + else if (rate == 25000000) + return 25000000; + else if (WARN_ON(rate < 75000000)) + return 25000000; + else if (WARN_ON(rate < 125000000)) + return 125000000; + else if (rate == 125000000) + return 125000000; + + WARN_ON(rate > 125000000); + + return 125000000; +} + +static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate); + if (rate != 125000000) + iowrite32(1, mgmt->reg); + else + iowrite32(0, mgmt->reg); + mgmt->rate = rate; + + return 0; +} + +static const struct clk_ops fu540_c000_ops = { + .recalc_rate = fu540_macb_tx_recalc_rate, + .round_rate = fu540_macb_tx_round_rate, + .set_rate = fu540_macb_tx_set_rate, +}; + +static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk, + struct clk **hclk, struct clk **tx_clk, + struct clk **rx_clk, struct clk **tsu_clk) +{ + struct clk_init_data init; + int err = 0; + + err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk); + if (err) + return err; + + mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL); + if (!mgmt) + return -ENOMEM; + + init.name = "sifive-gemgxl-mgmt"; + init.ops = &fu540_c000_ops; + init.flags = 0; + init.num_parents = 0; + + mgmt->rate = 0; + mgmt->hw.init = &init; + + *tx_clk = clk_register(NULL, &mgmt->hw); + if (IS_ERR(*tx_clk)) + return PTR_ERR(*tx_clk); + + err = clk_prepare_enable(*tx_clk); + if (err) + dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); + else + dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name); + + return 0; +} + +static int fu540_c000_init(struct platform_device *pdev) +{ + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return -ENODEV; + + mgmt->reg = ioremap(res->start, resource_size(res)); + if (!mgmt->reg) + return -ENOMEM; + + return macb_init(pdev); +} + +static const struct macb_config fu540_c000_config = { + .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | + MACB_CAPS_GEM_HAS_PTP, + .dma_burst_length = 16, + .clk_init = fu540_c000_clk_init, + .init = fu540_c000_init, + .jumbo_max_len = 10240, +}; + static const struct macb_config at91sam9260_config = { .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, .clk_init = macb_clk_init, @@ -3992,6 +4112,7 @@ static int at91ether_init(struct platform_device *pdev) { .compatible = "cdns,emac", .data = &emac_config }, { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, { .compatible = "cdns,zynq-gem", .data = &zynq_config }, + { .compatible = "sifive,fu540-macb", .data = &fu540_c000_config }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, macb_dt_ids); @@ -4199,6 +4320,7 @@ static int macb_probe(struct platform_device *pdev) err_disable_clocks: clk_disable_unprepare(tx_clk); + clk_unregister(tx_clk); clk_disable_unprepare(hclk); clk_disable_unprepare(pclk); clk_disable_unprepare(rx_clk); @@ -4233,6 +4355,7 @@ static int macb_remove(struct platform_device *pdev) pm_runtime_dont_use_autosuspend(&pdev->dev); if (!pm_runtime_suspended(&pdev->dev)) { clk_disable_unprepare(bp->tx_clk); + clk_unregister(bp->tx_clk); clk_disable_unprepare(bp->hclk); clk_disable_unprepare(bp->pclk); clk_disable_unprepare(bp->rx_clk);