From patchwork Thu Jun 13 16:04:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Hutton X-Patchwork-Id: 1115258 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-502913-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="TGvz4mzf"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="zRRR3Zls"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45PpT94KFXz9sNm for ; Fri, 14 Jun 2019 02:04:13 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; q=dns; s=default; b=cEfCkIr6+TjdXzfxMDfC9LsStfIxLyaAx2Ux/bqeQ6K3l46XwE rcmaEZtpKZld8qC6Z71k4eNquWPo22k1L4kDHUhfDd4UUa/deS1pyqrd7BUdg0kl 8PqLQESKV8jwmagUwFWEKPGyv9ubg8aN3exQNy+23FiBokC0EbgECnR6A= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; s= default; bh=TC4kOwima63o5iSh+N15s3p+8kI=; b=TGvz4mzfFWT7eC843mka S2eNMJgdxgHu6fFZxlJfZTQx1ZtflrDL5rC1g/D1z4kvaxxw9S5xMhHbC1dhWz6p 0OYUdz7wmmV/GJ0JVxxwBHYRQLDofG4HCLRG1sXJ/kmpWlnxkW4I0/3d4n/iU3uI Mgr9op9LihR6/SCTmoFcYF4= Received: (qmail 9595 invoked by alias); 13 Jun 2019 16:04:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9585 invoked by uid 89); 13 Jun 2019 16:04:06 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: EUR03-DB5-obe.outbound.protection.outlook.com Received: from mail-eopbgr40079.outbound.protection.outlook.com (HELO EUR03-DB5-obe.outbound.protection.outlook.com) (40.107.4.79) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 13 Jun 2019 16:04:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=muKg8vppo2/aBpKGE/QZOBlPDqA/jfrM+3rzHJoBTjE=; b=zRRR3ZlszJE3CBV+1ZKEX5ZhGJONSlRfdQm5kS9+DzwJXHryFjlov/I++k6o0cHLM3zUsv5mkPbcsz4mzNwEWVLMZ4WLoIJ0vUquq/zgWeYqLrxQF5TVSnaomyLJfeXnCua2q7TYATDn1Ez7jHWV1zDM7dOZ+eH/o9JhRAhSgNo= Received: from DB6PR0801MB2054.eurprd08.prod.outlook.com (10.168.86.135) by DB6PR0801MB1925.eurprd08.prod.outlook.com (10.168.85.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1987.12; Thu, 13 Jun 2019 16:04:00 +0000 Received: from DB6PR0801MB2054.eurprd08.prod.outlook.com ([fe80::c95f:673d:46cd:2ca3]) by DB6PR0801MB2054.eurprd08.prod.outlook.com ([fe80::c95f:673d:46cd:2ca3%10]) with mapi id 15.20.1987.010; Thu, 13 Jun 2019 16:04:00 +0000 From: Joel Hutton To: GCC Patches CC: nd Subject: [AArch64] Use scvtf fbits option where appropriate Date: Thu, 13 Jun 2019 16:04:00 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Joel.Hutton@arm.com; x-ms-oob-tlc-oobclassifiers: OLM:1360; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 MIME-Version: 1.0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Joel.Hutton@arm.com X-IsSubscribed: yes Hi all, There was previously no backend pattern to utilise the scvtf fbits option. Where a fixed point is converted to a float, and divided by a power of 2, (or multiplied by the reciprocal of a power of 2), this can be combined into a single scvtf with fbits operation. This patch adds a pattern to combine these instructions, and adds a helper function. For the following test case: float f(int a) { return ((float) a) / 65536.0; } double g(int a) { return ((double) a) / 4096.0; } the output generated is currently: f: scvtf s1, w0 // 6 [c=8 l=4] floatsisf2/1 mov w1, 931135488 // 17 [c=4 l=4] *movsi_aarch64/3 fmov s0, w1 // 18 [c=4 l=4] *movsf_aarch64/1 fmul s0, s1, s0 // 13 [c=8 l=4] mulsf3 ret // 24 [c=0 l=4] *do_return g: scvtf d1, w0 // 6 [c=8 l=4] floatsidf2 mov x1, 4553139223271571456 // 17 [c=4 l=4] *movdi_aarch64/3 fmov d0, x1 // 18 [c=4 l=4] *movdf_aarch64/1 fmul d0, d1, d0 // 13 [c=8 l=4] muldf3 ret // 24 [c=0 l=4] *do_return The output with this patch applied is: f: scvtf s0, w0, #16 // 13 [c=24 l=4] *combine_scvtf_SI_sf3/1 ret // 22 [c=0 l=4] *do_return g: scvtf d0, w0, #12 // 13 [c=24 l=4] *combine_scvtf_SI_df3 ret // 22 [c=0 l=4] *do_return gcc/ChangeLog: 2019-06-12 Joel Hutton * config/aarch64/aarch64-protos.h (aarch64_fpconst_pow2_recip): New prototype * config/aarch64/aarch64.c (aarch64_fpconst_pow2_recip): New function * config/aarch64/aarch64.md (*aarch64_cvtf__2_mult): New pattern (aarch64_cvtf__2_mult): New pattern * config/aarch64/constraints.md (Dt): New constraint * config/aarch64/predicates.md (aarch64_fpconst_pow2_recip): New predicate gcc/testsuite/ChangeLog: 2019-06-12 Joel Hutton * gcc.target/aarch64/fmul_scvtf.c: New test. Bootstrapped and regression tested on aarch64-linux-none target. From 6aac0d56dc7d34e7a6fcabc1e8b0c7c291c0d51a Mon Sep 17 00:00:00 2001 From: Joel Hutton Date: Thu, 13 Jun 2019 11:08:56 +0100 Subject: [PATCH] SCVTF fbits --- gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64.c | 30 ++++ gcc/config/aarch64/aarch64.md | 34 +++++ gcc/config/aarch64/constraints.md | 7 + gcc/config/aarch64/predicates.md | 4 + gcc/testsuite/gcc.target/aarch64/fmul_scvtf.c | 140 ++++++++++++++++++ 6 files changed, 216 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/fmul_scvtf.c diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 1e3b1c91db1..ad1ba458a3f 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -494,6 +494,7 @@ enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx); enum reg_class aarch64_regno_regclass (unsigned); int aarch64_asm_preferred_eh_data_format (int, int); int aarch64_fpconst_pow_of_2 (rtx); +int aarch64_fpconst_pow2_recip (rtx); machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned, machine_mode); int aarch64_uxt_size (int, HOST_WIDE_INT); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 9a035dd9ed8..49a7d9256cf 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -18707,6 +18707,36 @@ aarch64_fpconst_pow_of_2 (rtx x) return exact_log2 (real_to_integer (r)); } +/* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a + power of 2 (i.e 1/2^n) return the number of float bits. e.g. for x==(1/2^n) + return log2 (n). Otherwise return 0. */ +int +aarch64_fpconst_pow2_recip (rtx x) +{ + REAL_VALUE_TYPE r0; + + if (!CONST_DOUBLE_P (x)) + return 0; + + r0 = *CONST_DOUBLE_REAL_VALUE (x); + if (exact_real_inverse (DFmode, &r0) + && !REAL_VALUE_NEGATIVE (r0)) + { + if (exact_real_truncate (DFmode, &r0)) + { + HOST_WIDE_INT value = real_to_integer (&r0); + value = value & 0xffffffff; + if ((value != 0) && ( (value & (value - 1)) == 0)) + { + int ret = exact_log2 (value); + gcc_assert (IN_RANGE (ret, 0, 31)); + return ret; + } + } + } + return 0; +} + /* If X is a vector of equal CONST_DOUBLE values and that value is Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 526c7fb0dab..60bcf1bc8d9 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -6016,6 +6016,40 @@ [(set_attr "type" "f_cvtf2i")] ) +(define_insn "*aarch64_cvtf__2_mult" + [(set (match_operand:GPF 0 "register_operand" "=w,w") + (mult:GPF (FLOATUORS:GPF + (match_operand: 1 "register_operand" "w,?r")) + (match_operand 2 "aarch64_fp_pow2_recip""Dt,Dt")))] + "TARGET_FLOAT" + { + operands[2] = GEN_INT (aarch64_fpconst_pow2_recip (operands[2])); + switch (which_alternative) + { + case 0: + return "cvtf\t%0, %1, #%2"; + case 1: + return "cvtf\t%0, %1, #%2"; + } + return ""; + } + [(set_attr "type" "neon_int_to_fp_,f_cvti2f") + (set_attr "arch" "simd,fp")] +) + +(define_insn "*aarch64_cvtf__2_mult" + [(set (match_operand:GPF 0 "register_operand" "=w") + (mult:GPF (FLOATUORS:GPF + (match_operand: 1 "register_operand" "r")) + (match_operand 2 "aarch64_fp_pow2_recip" "Dt")))] + "TARGET_FLOAT" + { + operands[2] = GEN_INT (aarch64_fpconst_pow2_recip (operands[2])); + return "cvtf\t%0, %1, #%2"; + } + [(set_attr "type" "f_cvti2f")] +) + (define_insn "2" [(set (match_operand:GPF 0 "register_operand" "=w,w") (FLOATUORS:GPF (match_operand: 1 "register_operand" "w,?r")))] diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 21f9549e660..a7731a033ea 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -329,6 +329,13 @@ (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, QImode)"))) +(define_constraint "Dt" + "@internal + A const_double which is the reciprocal of an exact power of two, can be + used in an scvtf with fract bits operation" + (and (match_code "const_double") + (match_test "aarch64_fpconst_pow2_recip (op)"))) + (define_constraint "Dl" "@internal A constraint that matches vector of immediates for left shifts." diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 10100ca830a..993289014f0 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -98,6 +98,10 @@ (and (match_code "const_double") (match_test "aarch64_fpconst_pow_of_2 (op) > 0"))) +(define_predicate "aarch64_fp_pow2_recip" + (and (match_code "const_double") + (match_test "aarch64_fpconst_pow2_recip (op)"))) + (define_predicate "aarch64_fp_vec_pow2" (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0")) diff --git a/gcc/testsuite/gcc.target/aarch64/fmul_scvtf.c b/gcc/testsuite/gcc.target/aarch64/fmul_scvtf.c new file mode 100644 index 00000000000..e8d1de6279b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmul_scvtf.c @@ -0,0 +1,140 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -O2 -fno-inline" } */ + +#define FUNC_DEFS(__a) \ + float \ +fsfoo##__a (int x) \ +{ \ + return ((float) x)/(1u << __a); \ +} \ +float \ +fusfoo##__a (unsigned int x) \ +{ \ + return ((float) x)/(1u << __a); \ +} \ +float \ +fslfoo##__a (long x) \ +{ \ + return ((float) x)/(1u << __a); \ +} \ +float \ +fulfoo##__a (unsigned long x) \ +{ \ + return ((float) x)/(1u << __a); \ +} \ + +#define FUNC_DEFD(__a) \ +double \ +dsfoo##__a (int x) \ +{ \ + return ((double) x)/(1u << __a);\ +} \ +double \ +dusfoo##__a (unsigned int x) \ +{ \ + return ((double) x)/(1u << __a);\ +} \ +double \ +dslfoo##__a (long x) \ +{ \ + return ((double) x)/(1u << __a);\ +} \ +double \ +dulfoo##__a (unsigned long x) \ +{ \ + return ((double) x)/(1u << __a);\ +} + +FUNC_DEFS (4) + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#4" 1 } } */ + +FUNC_DEFD (4) + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#4" 1 } } */ + +FUNC_DEFS (8) + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#8" 1 } } */ + +FUNC_DEFD (8) + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#8" 1 } } */ + +FUNC_DEFS (16) + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#16" 1 } } */ + +FUNC_DEFD (16) + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#16" 1 } } */ + +FUNC_DEFS (31) + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#31" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#31" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#31" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#31" 1 } } */ + +FUNC_DEFD (31) + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#31" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#31" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#31" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#31" 1 } } */ + +#define FUNC_TESTS(__a, __b) \ +do \ +{ \ + if (fsfoo##__a (__b) != ((int) i) * (1.0f/(1u << __a)) ) \ + __builtin_abort (); \ + if (fusfoo##__a (__b) != ((int) i) * (1.0f/(1u << __a)) ) \ + __builtin_abort (); \ + if (fslfoo##__a (__b) != ((int) i) * (1.0f/(1u << __a)) ) \ + __builtin_abort (); \ + if (fulfoo##__a (__b) != ((int) i) * (1.0f/(1u << __a)) ) \ + __builtin_abort (); \ +} while (0) + +#define FUNC_TESTD(__a, __b) \ +do \ +{ \ + if (fsfoo##__a (__b) != ((int) i) * (1.0d/(1u << __a)) ) \ + __builtin_abort (); \ + if (fusfoo##__a (__b) != ((int) i) * (1.0d/(1u << __a)) ) \ + __builtin_abort (); \ + if (fslfoo##__a (__b) != ((int) i) * (1.0d/(1u << __a)) ) \ + __builtin_abort (); \ + if (fulfoo##__a (__b) != ((int) i) * (1.0d/(1u << __a)) ) \ + __builtin_abort (); \ +} while (0) + + int +main (void) +{ + int i; + + for (i = 0; i < 32; i ++) + { + FUNC_TESTS (4, i); + FUNC_TESTS (8, i); + FUNC_TESTS (16, i); + FUNC_TESTS (31, i); + + FUNC_TESTD (4, i); + FUNC_TESTD (8, i); + FUNC_TESTD (16, i); + FUNC_TESTD (31, i); + } + return 0; +} -- 2.17.1