From patchwork Tue Jun 4 13:07:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jozef Lawrynowicz X-Patchwork-Id: 1109842 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-502297-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mittosystems.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ukDlq+QZ"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=mittosystems.com header.i=@mittosystems.com header.b="nceRajew"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45JBzD56KGz9s6w for ; Tue, 4 Jun 2019 23:07:20 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=ssG8DLwnp63t/nzA fi8xSV2N1QVCnEF+f+s2pDuAZsQpNgc6zcAc9GfCb9dFpuKSHB1RMx4W4EW+lYhI WKom1soNkTdyg1J/vqk0qZrFRSl83RloSUTJbntOM9Gh4o11Vn/dxYjqHV/j3VLB mN0CtQajFUJNh8Eqd0RSjDoEieA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=olOERof56c4ORJTRiwIi8k tEKWY=; b=ukDlq+QZObAE+kREFkKZajLtBO1gzG9sG1s8Hipabj3UmBhBdGg1Ap LN1IAjyjcaq3dqaunZoXNSbdB4c1VLIzhS6lvq5rSfC7pNtUNT8sw8bOm+T8bPT4 ZU1I0BZ6U2FmfwwGdSxm+oYRwHQVwbGHQmSj1WGzcd9mJe3Sra+H0= Received: (qmail 121756 invoked by alias); 4 Jun 2019 13:07:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 121743 invoked by uid 89); 4 Jun 2019 13:07:13 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=a.out, aout, UD:a.out X-HELO: mail-wr1-f41.google.com Received: from mail-wr1-f41.google.com (HELO mail-wr1-f41.google.com) (209.85.221.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 04 Jun 2019 13:07:11 +0000 Received: by mail-wr1-f41.google.com with SMTP id n4so12714995wrs.3 for ; Tue, 04 Jun 2019 06:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mittosystems.com; s=google; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version; bh=XjWztqmmgYcRbGBeoP9c97iWR/8P6/SjGOG1MbzOOEQ=; b=nceRajew6NTuy0MyzZO6uIfs0lGwho0gIMXAgM3Iovbb6B8ohflIdwto/Zwqf/a9Fu l9x3JsJEk/ilWswKLUwArrtfKXwNVN3GwnFVkcDAqzfIDaODLeDQCVmPOBMIops2aJOu MWiKqGHAvWDZJ0kOwD+Z628/BXEQoZFNUVU5M3Pj5ZFOJNv6gGeO7VqJPoSrk+ATrjWS LEcyuUz18JB5j5FRslrMbBn0BUViIq3EHb8eBRRBve+0UCv6gW6XserEO8XXN0HQurMr NNJXsZi4XPBCPHoYzxNMyUlUtightEwUCp4/gX8nYzHoWOIyqZt7yTBkrDn+Zlajca4v yGRQ== Received: from jozef-kubuntu ([2a01:4b00:87fd:900:5c4d:209e:5b9a:8189]) by smtp.gmail.com with ESMTPSA id g5sm20898759wrp.29.2019.06.04.06.07.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jun 2019 06:07:09 -0700 (PDT) Date: Tue, 4 Jun 2019 14:07:07 +0100 From: Jozef Lawrynowicz To: gcc-patches@gcc.gnu.org Cc: "nickc@redhat.com" Subject: [PATCH][MSP430][1/4] Put libgcc shift functions in their own sections Message-ID: <20190604140707.7b1f0df3@jozef-kubuntu> In-Reply-To: <20190604140329.5c4e1629@jozef-kubuntu> References: <20190604140329.5c4e1629@jozef-kubuntu> MIME-Version: 1.0 X-IsSubscribed: yes This patch reduces code size by putting each of the shift library functions from libgcc in their own section. This means that, for example, a 16-bit logical left shift does not result in code to perform a 32-bit logical left shift being included in the final executable, as the linker can now garbage collect unused sections. For the following program, the below code size reduction is observed: int a, b; int main (void) { a = a << b; return 0; } Current trunk: text data bss dec hex filename 572 12 22 606 25e a.out With patch: text data bss dec hex filename 466 12 22 500 1f4 a.out Ok for trunk? From 8017a4b453ae1b07bbeb75f7f7613a5bc5605159 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Mon, 13 May 2019 17:42:08 +0100 Subject: [PATCH 1/4] MSP430: Put the library functions for bitwise shifts in their own sections libgcc/ChangeLog 2019-06-04 Jozef Lawrynowicz * config/msp430/slli.S (__mspabi_slli_n): Put function in its own section. (__mspabi_slli): Likewise. (__mspabi_slll_n): Likewise. (__mspabi_slll): Likewise. * config/msp430/srai.S (__mspabi_srai_n): Likewise. (__mspabi_srai): Likewise. (__mspabi_sral_n): Likewise. (__mspabi_sral): Likewise. * config/msp430/srli.S (__mspabi_srli_n): Likewise. (__mspabi_srli): Likewise. (__mspabi_srll_n): Likewise. (__mspabi_srll): Likewise. --- libgcc/config/msp430/slli.S | 8 ++++++-- libgcc/config/msp430/srai.S | 8 ++++++-- libgcc/config/msp430/srli.S | 8 ++++++-- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/libgcc/config/msp430/slli.S b/libgcc/config/msp430/slli.S index 9d151a97f5d..89ca35a9304 100644 --- a/libgcc/config/msp430/slli.S +++ b/libgcc/config/msp430/slli.S @@ -22,8 +22,9 @@ .text -/* Logical Left Shift - R12 -> R12 */ +/* Logical Left Shift - R12 -> R12. */ + .section .text.__mspabi_slli_n .macro _slli n .global __mspabi_slli_\n __mspabi_slli_\n: @@ -51,6 +52,7 @@ __mspabi_slli_\n: RET #endif + .section .text.__mspabi_slli 1: ADD.W #-1,R13 ADD.W R12,R12 .global __mspabi_slli @@ -63,8 +65,9 @@ __mspabi_slli: RET #endif -/* Logical Left Shift - R12:R13 -> R12:R13 */ +/* Logical Left Shift - R12:R13 -> R12:R13. */ + .section .text.__mspabi_slll_n .macro _slll n .global __mspabi_slll_\n __mspabi_slll_\n: @@ -93,6 +96,7 @@ __mspabi_slll_\n: RET #endif + .section .text.__mspabi_slll 1: ADD.W #-1,R14 ADD.W R12,R12 ADDC.W R13,R13 diff --git a/libgcc/config/msp430/srai.S b/libgcc/config/msp430/srai.S index 33c9b5ee62d..564f7989a8c 100644 --- a/libgcc/config/msp430/srai.S +++ b/libgcc/config/msp430/srai.S @@ -22,13 +22,14 @@ .text + .section .text.__mspabi_srai_n .macro _srai n .global __mspabi_srai_\n __mspabi_srai_\n: RRA.W R12 .endm -/* Logical Right Shift - R12 -> R12 */ +/* Arithmetic Right Shift - R12 -> R12. */ _srai 15 _srai 14 _srai 13 @@ -50,6 +51,7 @@ __mspabi_srai_\n: RET #endif + .section .text.__mspabi_srai 1: ADD.W #-1,R13 RRA.W R12,R12 .global __mspabi_srai @@ -62,8 +64,9 @@ __mspabi_srai: RET #endif -/* Logical Right Shift - R12:R13 -> R12:R13 */ +/* Arithmetic Right Shift - R12:R13 -> R12:R13. */ + .section .text.__mspabi_sral_n .macro _sral n .global __mspabi_sral_\n __mspabi_sral_\n: @@ -92,6 +95,7 @@ __mspabi_sral_\n: RET #endif + .section .text.__mspabi_sral 1: ADD.W #-1,R14 RRA.W R13 RRC.W R12 diff --git a/libgcc/config/msp430/srli.S b/libgcc/config/msp430/srli.S index dbe37f67a7d..4dd32ea4002 100644 --- a/libgcc/config/msp430/srli.S +++ b/libgcc/config/msp430/srli.S @@ -22,6 +22,7 @@ .text + .section .text.__mspabi_srli_n .macro _srli n .global __mspabi_srli_\n __mspabi_srli_\n: @@ -29,7 +30,7 @@ __mspabi_srli_\n: RRC.W R12 .endm -/* Logical Right Shift - R12 -> R12 */ +/* Logical Right Shift - R12 -> R12. */ _srli 15 _srli 14 _srli 13 @@ -51,6 +52,7 @@ __mspabi_srli_\n: RET #endif + .section .text.__mspabi_srli 1: ADD.W #-1,R13 CLRC RRC.W R12,R12 @@ -64,8 +66,9 @@ __mspabi_srli: RET #endif -/* Logical Right Shift - R12:R13 -> R12:R13 */ +/* Logical Right Shift - R12:R13 -> R12:R13. */ + .section .text.__mspabi_srll_n .macro _srll n .global __mspabi_srll_\n __mspabi_srll_\n: @@ -95,6 +98,7 @@ __mspabi_srll_\n: RET #endif + .section .text.__mspabi_srll 1: ADD.W #-1,R14 CLRC RRC.W R13 -- 2.17.1 From patchwork Tue Jun 4 13:11:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jozef Lawrynowicz X-Patchwork-Id: 1109844 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-502298-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mittosystems.com Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45JC4T3Wwsz9s6w for ; Tue, 4 Jun 2019 23:11:51 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type; 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Tue, 04 Jun 2019 06:11:40 -0700 (PDT) Date: Tue, 4 Jun 2019 14:11:38 +0100 From: Jozef Lawrynowicz To: gcc-patches@gcc.gnu.org Cc: "nickc@redhat.com" Subject: [PATCH][MSP430][2/4] Emulate 16-bit shifts with rotate insn when src operand is originally in memory Message-ID: <20190604141138.061f7e8f@jozef-kubuntu> In-Reply-To: <20190604140329.5c4e1629@jozef-kubuntu> References: <20190604140329.5c4e1629@jozef-kubuntu> MIME-Version: 1.0 X-IsSubscribed: yes This patch reduces code size by enabling the emulation of some 16-bit shift instructions with the native rotate instructions, when the source operand is in memory. This is achieved by forcing the source operand into a register. For the following program, the below code size reduction is observed: int a; int main (void) { a = a << 4; return 0; } With shift patch 1: text data bss dec hex filename 484 12 20 516 204 a.out With new patch: text data bss dec hex filename 452 12 20 484 1e4 a.out Ok for trunk? From e609f63d49227ce385316896dde6a476f5f27db7 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Mon, 13 May 2019 17:48:00 +0100 Subject: [PATCH 2/4] MSP430: Force the src operand of a HImode shift into a register if it is in memory gcc/ChangeLog 2019-06-04 Jozef Lawrynowicz * config/msp430/msp430.md (ashlhi3): Force shift src operand into a register if it is in memory, so the shift can be emulated with a rotate instruction. (ashrhi3): Likewise. (lshrhi3): Likewise. gcc/testsuite/ChangeLog 2019-06-04 Jozef Lawrynowicz * gcc.target/msp430/emulate-slli.c: New test. * gcc.target/msp430/emulate-srai.c: New test. * gcc.target/msp430/emulate-srli.c: New test. --- gcc/config/msp430/msp430.md | 15 +++++++++------ gcc/testsuite/gcc.target/msp430/emulate-slli.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/msp430/emulate-srai.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/msp430/emulate-srli.c | 15 +++++++++++++++ 4 files changed, 54 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/msp430/emulate-slli.c create mode 100644 gcc/testsuite/gcc.target/msp430/emulate-srai.c create mode 100644 gcc/testsuite/gcc.target/msp430/emulate-srli.c diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index 344d21d9378..58c1f4edc9c 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -756,8 +756,9 @@ (match_operand:HI 2 "general_operand")))] "" { - if (GET_CODE (operands[1]) == SUBREG - && REG_P (XEXP (operands[1], 0))) + if ((GET_CODE (operands[1]) == SUBREG + && REG_P (XEXP (operands[1], 0))) + || MEM_P (operands[1])) operands[1] = force_reg (HImode, operands[1]); if (msp430x && REG_P (operands[0]) @@ -828,8 +829,9 @@ (match_operand:HI 2 "general_operand")))] "" { - if (GET_CODE (operands[1]) == SUBREG - && REG_P (XEXP (operands[1], 0))) + if ((GET_CODE (operands[1]) == SUBREG + && REG_P (XEXP (operands[1], 0))) + || MEM_P (operands[1])) operands[1] = force_reg (HImode, operands[1]); if (msp430x && REG_P (operands[0]) @@ -916,8 +918,9 @@ (match_operand:HI 2 "general_operand")))] "" { - if (GET_CODE (operands[1]) == SUBREG - && REG_P (XEXP (operands[1], 0))) + if ((GET_CODE (operands[1]) == SUBREG + && REG_P (XEXP (operands[1], 0))) + || MEM_P (operands[1])) operands[1] = force_reg (HImode, operands[1]); if (msp430x && REG_P (operands[0]) diff --git a/gcc/testsuite/gcc.target/msp430/emulate-slli.c b/gcc/testsuite/gcc.target/msp430/emulate-slli.c new file mode 100644 index 00000000000..0ed09d55d8c --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/emulate-slli.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-final { scan-assembler-not "mspabi_slli" } } */ +/* { dg-final { scan-assembler "rlax" } } */ + +/* Ensure that HImode shifts with source operand in memory are emulated with a + rotate instructions. */ + +int a; + +void +foo (void) +{ + a = a << 4; +} diff --git a/gcc/testsuite/gcc.target/msp430/emulate-srai.c b/gcc/testsuite/gcc.target/msp430/emulate-srai.c new file mode 100644 index 00000000000..66291717a02 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/emulate-srai.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-final { scan-assembler-not "mspabi_srai" } } */ +/* { dg-final { scan-assembler "rrax" } } */ + +/* Ensure that HImode shifts with source operand in memory are emulated with a + rotate instructions. */ + +int a; + +void +foo (void) +{ + a = a >> 4; +} diff --git a/gcc/testsuite/gcc.target/msp430/emulate-srli.c b/gcc/testsuite/gcc.target/msp430/emulate-srli.c new file mode 100644 index 00000000000..c10f30b2779 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/emulate-srli.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-final { scan-assembler-not "mspabi_srli" } } */ +/* { dg-final { scan-assembler "rrum" } } */ + +/* Ensure that HImode shifts with source operand in memory are emulated with a + rotate instructions. */ + +unsigned int a; + +void +foo (void) +{ + a = a >> 4; +} -- 2.17.1 From patchwork Tue Jun 4 13:14:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jozef Lawrynowicz X-Patchwork-Id: 1109845 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-502299-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mittosystems.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="TwmCGsDO"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=mittosystems.com header.i=@mittosystems.com header.b="P7aPXu5i"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45JC7g2kkwz9s3Z for ; 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For the following program, the below code size reduction is observed: long a; int main (void) { a = a >> 4; return 0; } With shift patch 2: text data bss dec hex filename 522 12 22 556 22c a.out New patch: text data bss dec hex filename 474 12 22 508 1fc a.out Ok for trunk? From 894b6809822ba3a3a1bab3750abe29e03f2a3ad6 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Mon, 13 May 2019 17:52:19 +0100 Subject: [PATCH 3/4] MSP430: Do not use the performance optimized variant of a shift by constant amount when optimizing for size gcc/ChangeLog 2019-06-04 Jozef Lawrynowicz * config/msp430/msp430.md (ashlhi3): Use the const_variant of shift library functions only when not optimizing for size. (ashlsi3): Likewise. (ashrhi3): Likewise. (ashrsi3): Likewise. (lshrhi3): Likewise. (lshrsi3): Likewise. gcc/testsuite/ChangeLog 2019-06-04 Jozef Lawrynowicz * gcc.target/msp430/size-optimized-shifts.c: New test. --- gcc/config/msp430/msp430.md | 15 ++++++----- .../gcc.target/msp430/size-optimized-shifts.c | 26 +++++++++++++++++++ 2 files changed, 35 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/msp430/size-optimized-shifts.c diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index 58c1f4edc9c..76296a2f317 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -769,7 +769,10 @@ && INTVAL (operands[2]) == 1) emit_insn (gen_slli_1 (operands[0], operands[1])); else - msp430_expand_helper (operands, \"__mspabi_slli\", true); + /* The const variants of mspabi shifts have larger code size than the + generic version, so use the generic version if optimizing for + size. */ + msp430_expand_helper (operands, \"__mspabi_slli\", !optimize_size); DONE; } ) @@ -815,7 +818,7 @@ (ashift:SI (match_operand:SI 1 "general_operand") (match_operand:SI 2 "general_operand")))] "" - "msp430_expand_helper (operands, \"__mspabi_slll\", true); + "msp430_expand_helper (operands, \"__mspabi_slll\", !optimize_size); DONE;" ) @@ -842,7 +845,7 @@ && INTVAL (operands[2]) == 1) emit_insn (gen_srai_1 (operands[0], operands[1])); else - msp430_expand_helper (operands, \"__mspabi_srai\", true); + msp430_expand_helper (operands, \"__mspabi_srai\", !optimize_size); DONE; } ) @@ -904,7 +907,7 @@ (ashiftrt:SI (match_operand:SI 1 "general_operand") (match_operand:SI 2 "general_operand")))] "" - "msp430_expand_helper (operands, \"__mspabi_sral\", true); + "msp430_expand_helper (operands, \"__mspabi_sral\", !optimize_size); DONE;" ) @@ -931,7 +934,7 @@ && INTVAL (operands[2]) == 1) emit_insn (gen_srli_1 (operands[0], operands[1])); else - msp430_expand_helper (operands, \"__mspabi_srli\", true); + msp430_expand_helper (operands, \"__mspabi_srli\", !optimize_size); DONE; } ) @@ -983,7 +986,7 @@ (lshiftrt:SI (match_operand:SI 1 "general_operand") (match_operand:SI 2 "general_operand")))] "" - "msp430_expand_helper (operands, \"__mspabi_srll\", true); + "msp430_expand_helper (operands, \"__mspabi_srll\", !optimize_size); DONE;" ) diff --git a/gcc/testsuite/gcc.target/msp430/size-optimized-shifts.c b/gcc/testsuite/gcc.target/msp430/size-optimized-shifts.c new file mode 100644 index 00000000000..be9509b86cc --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/size-optimized-shifts.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-final { scan-assembler-not "__mspabi_sral_4" } } */ +/* { dg-final { scan-assembler-not "__mspabi_srll_4" } } */ +/* { dg-final { scan-assembler-not "__mspabi_slll_4" } } */ +/* { dg-final { scan-assembler "__mspabi_sral" } } */ +/* { dg-final { scan-assembler "__mspabi_srll" } } */ +/* { dg-final { scan-assembler "__mspabi_slll" } } */ + +/* Ensure that SImode shifts by a constant amount do not use the const_variant + of the shift library code when optimizing for size. */ + +long a; +long b; +long c; +long d; +unsigned long e; +unsigned long f; + +void +foo (void) +{ + a = b >> 4; + c = d << 4; + e = f >> 4; +} -- 2.17.1 From patchwork Tue Jun 4 13:17:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jozef Lawrynowicz X-Patchwork-Id: 1109866 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-502300-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mittosystems.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="N1RLvIUu"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=mittosystems.com header.i=@mittosystems.com header.b="OTFyMZJD"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45JCCf0VwFz9sPG for ; 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b=OTFyMZJD6bc66mgzEIVgs76a8iQaUHxMcGLVDZ8e0YK0YqmsxxyN1YFl0NCsumXjqU 2SOtLPQJgZ9lbpLA3e4pg+phA9vlS5KGTh+N2xDyyDVcj6F4678WOrrWHEyyeBGTFgnB qe4cTWzSXMQaUDahEUrnV/Y0JTl1QP1LS9HyQ5DEoom/ljyzKCynIAazBa76BM4why/a 3q053zT1e2WfIGD6za58ruv1DyA3a9h4F1GqWv4gkPgSpqybcfGlnFtP9RvHpOUBJJvy kfnn/knoLI+6l/PnQM+ddb1hdFq7ubFBWqTGP/wIShmYGslv4AyuROLkEf+uQNMkBWpW l9Nw== Received: from jozef-kubuntu ([2a01:4b00:87fd:900:5c4d:209e:5b9a:8189]) by smtp.gmail.com with ESMTPSA id w3sm12489588wmc.8.2019.06.04.06.17.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jun 2019 06:17:52 -0700 (PDT) Date: Tue, 4 Jun 2019 14:17:50 +0100 From: Jozef Lawrynowicz To: gcc-patches@gcc.gnu.org Cc: "nickc@redhat.com" Subject: [PATCH][MSP430][4/4] Implement 64-bit shifts in assembly code Message-ID: <20190604141750.42210082@jozef-kubuntu> In-Reply-To: <20190604140329.5c4e1629@jozef-kubuntu> References: <20190604140329.5c4e1629@jozef-kubuntu> MIME-Version: 1.0 X-IsSubscribed: yes This patch implements 64-bit shifts in assembly code. Previously, generic C library code from libgcc would be used to perform the shifts, which was much more costly in terms of code size. I observed 700 PASS->FAIL regressions from the GCC testsuite alone when these 64-bit shifts were implemented incorrectly, hence I've assumed there is already adequate test coverage that shifts operate correctly, and I have not added new tests to verify their correct execution. For the following program, the below code size reduction is observed: long long a; int main (void) { a = a >> 4; return 0; } With shift patch 3: text data bss dec hex filename 670 12 26 708 2c4 a.out With new patch: text data bss dec hex filename 512 12 26 550 226 a.out Ok for trunk? From 3b34b3d005ea63b37cf6a277395a048e55d854b2 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Mon, 13 May 2019 17:55:27 +0100 Subject: [PATCH 4/4] MSP430: Implement 64-bit shifts in assembly code gcc/ChangeLog 2019-06-04 Jozef Lawrynowicz * config/msp430/msp430.c (msp430_expand_helper): Setup arguments which describe how to perform MSPABI compliant 64-bit shift. * config/msp430/msp430.md (ashldi3): New define_expand. (ashrdi3): New define_expand. (lshrdi3): New define_expand. libgcc/ChangeLog 2019-06-04 Jozef Lawrynowicz * config/msp430/slli.S (__mspabi_sllll): New library function for performing a logical left shift of a 64-bit value. (__mspabi_srall): New library function for performing a arithmetic right shift of a 64-bit value. (__mspabi_srlll): New library function for performing a logical right shift of a 64-bit value. gcc/testsuite/ChangeLog 2019-06-04 Jozef Lawrynowicz * gcc.target/msp430/mspabi_sllll.c: New test. * gcc.target/msp430/mspabi_srall.c: New test. * gcc.target/msp430/mspabi_srlll.c: New test. --- gcc/config/msp430/msp430.c | 13 +++++-- gcc/config/msp430/msp430.md | 36 +++++++++++++++++++ .../gcc.target/msp430/mspabi_sllll.c | 10 ++++++ .../gcc.target/msp430/mspabi_srall.c | 10 ++++++ .../gcc.target/msp430/mspabi_srlll.c | 10 ++++++ libgcc/config/msp430/slli.S | 33 +++++++++++++++++ libgcc/config/msp430/srai.S | 34 ++++++++++++++++++ libgcc/config/msp430/srli.S | 35 ++++++++++++++++++ 8 files changed, 179 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/msp430/mspabi_sllll.c create mode 100644 gcc/testsuite/gcc.target/msp430/mspabi_srall.c create mode 100644 gcc/testsuite/gcc.target/msp430/mspabi_srlll.c diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c index 020e980b8cc..365e9eba747 100644 --- a/gcc/config/msp430/msp430.c +++ b/gcc/config/msp430/msp430.c @@ -3046,6 +3046,7 @@ msp430_expand_helper (rtx *operands, const char *helper_name, bool const_variant { rtx c, f; char *helper_const = NULL; + int arg1 = 12; int arg2 = 13; int arg1sz = 1; machine_mode arg0mode = GET_MODE (operands[0]); @@ -3079,6 +3080,13 @@ msp430_expand_helper (rtx *operands, const char *helper_name, bool const_variant arg2 = 14; arg1sz = 2; } + else if (arg1mode == DImode) + { + /* Shift value in R8:R11, shift amount in R12. */ + arg1 = 8; + arg1sz = 4; + arg2 = 12; + } if (const_variants && CONST_INT_P (operands[2]) @@ -3091,7 +3099,7 @@ msp430_expand_helper (rtx *operands, const char *helper_name, bool const_variant snprintf (helper_const, len, "%s_%d", helper_name, (int) INTVAL (operands[2])); } - emit_move_insn (gen_rtx_REG (arg1mode, 12), + emit_move_insn (gen_rtx_REG (arg1mode, arg1), operands[1]); if (!helper_const) emit_move_insn (gen_rtx_REG (arg2mode, arg2), @@ -3104,12 +3112,13 @@ msp430_expand_helper (rtx *operands, const char *helper_name, bool const_variant RTL_CONST_CALL_P (c) = 1; f = 0; - use_regs (&f, 12, arg1sz); + use_regs (&f, arg1, arg1sz); if (!helper_const) use_regs (&f, arg2, 1); add_function_usage_to (c, f); emit_move_insn (operands[0], + /* Return value will always start in R12. */ gen_rtx_REG (arg0mode, 12)); } diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index 76296a2f317..f6d688950cb 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -822,6 +822,18 @@ DONE;" ) +(define_expand "ashldi3" + [(set (match_operand:DI 0 "nonimmediate_operand") + (ashift:DI (match_operand:DI 1 "general_operand") + (match_operand:DI 2 "general_operand")))] + "" + { + /* No const_variant for 64-bit shifts. */ + msp430_expand_helper (operands, \"__mspabi_sllll\", false); + DONE; + } +) + ;;---------- ;; signed A >> C @@ -911,6 +923,18 @@ DONE;" ) +(define_expand "ashrdi3" + [(set (match_operand:DI 0 "nonimmediate_operand") + (ashift:DI (match_operand:DI 1 "general_operand") + (match_operand:DI 2 "general_operand")))] + "" + { + /* No const_variant for 64-bit shifts. */ + msp430_expand_helper (operands, \"__mspabi_srall\", false); + DONE; + } +) + ;;---------- ;; unsigned A >> C @@ -990,6 +1014,18 @@ DONE;" ) +(define_expand "lshrdi3" + [(set (match_operand:DI 0 "nonimmediate_operand") + (ashift:DI (match_operand:DI 1 "general_operand") + (match_operand:DI 2 "general_operand")))] + "" + { + /* No const_variant for 64-bit shifts. */ + msp430_expand_helper (operands, \"__mspabi_srlll\", false); + DONE; + } +) + ;;------------------------------------------------------------ ;; Function Entry/Exit diff --git a/gcc/testsuite/gcc.target/msp430/mspabi_sllll.c b/gcc/testsuite/gcc.target/msp430/mspabi_sllll.c new file mode 100644 index 00000000000..b88a8be73ff --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/mspabi_sllll.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler-not "ashldi3" } } */ +/* { dg-final { scan-assembler "__mspabi_sllll" } } */ + +long long +foo (long long a) +{ + return a << 4; +} + diff --git a/gcc/testsuite/gcc.target/msp430/mspabi_srall.c b/gcc/testsuite/gcc.target/msp430/mspabi_srall.c new file mode 100644 index 00000000000..a0aba3d43d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/mspabi_srall.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler-not "ashrdi3" } } */ +/* { dg-final { scan-assembler "__mspabi_srall" } } */ + +long long +foo (long long a) +{ + return a >> 4; +} + diff --git a/gcc/testsuite/gcc.target/msp430/mspabi_srlll.c b/gcc/testsuite/gcc.target/msp430/mspabi_srlll.c new file mode 100644 index 00000000000..cb9a3744b77 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/mspabi_srlll.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler-not "lshrdi3" } } */ +/* { dg-final { scan-assembler "__mspabi_srlll" } } */ + +unsigned long long +foo (unsigned long long a) +{ + return a >> 4; +} + diff --git a/libgcc/config/msp430/slli.S b/libgcc/config/msp430/slli.S index 89ca35a9304..9210fe6e934 100644 --- a/libgcc/config/msp430/slli.S +++ b/libgcc/config/msp430/slli.S @@ -110,3 +110,36 @@ __mspabi_slll: RET #endif +/* Logical Left Shift - R8:R11 -> R12:R15 + A 64-bit argument would normally be passed in R12:R15, but __mspabi_sllll has + special conventions, so the 64-bit value to shift is passed in R8:R11. + According to the MSPABI, the shift amount is a 64-bit value in R12:R15, but + we only use the low word in R12. */ + + .section .text.__mspabi_sllll + .global __mspabi_sllll +__mspabi_sllll: + MOV R11, R15 ; Free up R11 first + MOV R12, R11 ; Save the shift amount in R11 + MOV R10, R14 + MOV R9, R13 + MOV R8, R12 + CMP #0,R11 + JNZ 1f +#ifdef __MSP430X_LARGE__ + RETA +#else + RET +#endif +1: + RLA R12 + RLC R13 + RLC R14 + RLC R15 + ADD #-1,R11 + JNZ 1b +#ifdef __MSP430X_LARGE__ + RETA +#else + RET +#endif diff --git a/libgcc/config/msp430/srai.S b/libgcc/config/msp430/srai.S index 564f7989a8c..ed5c6a5ad7c 100644 --- a/libgcc/config/msp430/srai.S +++ b/libgcc/config/msp430/srai.S @@ -108,3 +108,37 @@ __mspabi_sral: #else RET #endif + +/* Arithmetic Right Shift - R8:R11 -> R12:R15 + A 64-bit argument would normally be passed in R12:R15, but __mspabi_srall has + special conventions, so the 64-bit value to shift is passed in R8:R11. + According to the MSPABI, the shift amount is a 64-bit value in R12:R15, but + we only use the low word in R12. */ + + .section .text.__mspabi_srall + .global __mspabi_srall +__mspabi_srall: + MOV R11, R15 ; Free up R11 first + MOV R12, R11 ; Save the shift amount in R11 + MOV R10, R14 + MOV R9, R13 + MOV R8, R12 + CMP #0, R11 + JNZ 1f +#ifdef __MSP430X_LARGE__ + RETA +#else + RET +#endif +1: + RRA R15 + RRC R14 + RRC R13 + RRC R12 + ADD #-1,R11 + JNZ 1b +#ifdef __MSP430X_LARGE__ + RETA +#else + RET +#endif diff --git a/libgcc/config/msp430/srli.S b/libgcc/config/msp430/srli.S index 4dd32ea4002..bc1b034e4b9 100644 --- a/libgcc/config/msp430/srli.S +++ b/libgcc/config/msp430/srli.S @@ -112,3 +112,38 @@ __mspabi_srll: #else RET #endif + +/* Logical Right Shift - R8:R11 -> R12:R15 + A 64-bit argument would normally be passed in R12:R15, but __mspabi_srlll has + special conventions, so the 64-bit value to shift is passed in R8:R11. + According to the MSPABI, the shift amount is a 64-bit value in R12:R15, but + we only use the low word in R12. */ + + .section .text.__mspabi_srlll + .global __mspabi_srlll +__mspabi_srlll: + MOV R11, R15 ; Free up R11 first + MOV R12, R11 ; Save the shift amount in R11 + MOV R10, R14 + MOV R9, R13 + MOV R8, R12 + CMP #0,R11 + JNZ 1f +#ifdef __MSP430X_LARGE__ + RETA +#else + RET +#endif +1: + CLRC + RRC R15 + RRC R14 + RRC R13 + RRC R12 + ADD #-1,R11 + JNZ 1b +#ifdef __MSP430X_LARGE__ + RETA +#else + RET +#endif -- 2.17.1