From patchwork Tue Jun 4 12:46:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Marginean X-Patchwork-Id: 1109830 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Z3VSYu+V"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45JBWR708Tz9s6w for ; Tue, 4 Jun 2019 22:46:43 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 6D8E6C21D8E; Tue, 4 Jun 2019 12:46:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C782EC21C50; Tue, 4 Jun 2019 12:46:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0F631C21C50; Tue, 4 Jun 2019 12:46:37 +0000 (UTC) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by lists.denx.de (Postfix) with ESMTPS id B9AFDC21BE5 for ; Tue, 4 Jun 2019 12:46:36 +0000 (UTC) Received: by mail-wm1-f68.google.com with SMTP id 16so10297017wmg.5 for ; Tue, 04 Jun 2019 05:46:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hPF02d7XDMt/3dY17CUSBjnv60cGAtZEmsl6hmOsUA4=; b=Z3VSYu+VKCA0AWGjBefkFPX9Mt5zcHz8XUjrNVBFLvdL59iLqKovbwFJG4HBRRMfDv 8RY1toETD+o7aeU0Nmvai27+6tLwTSdEKRQ5SxRSaMt993ubv94MmqYLQ1Jrbppann/W c2fe50cqdLJqRcO9JllU98r9PEG5eztHtB4P+h6j7Yps0Y9drpVycdWDmlfbLUa+HGJQ ngkOFIrPz78lOrCs/RM13fkfOJmA6ZmScZEZ8pR7zz/paBz19Rhpji2r3+e/FJc4UWRs s8OQ/wO4ki1UPk5sa2Y30cOxlxYRjjcWewkaA2mPEeLt0wair934ay28JBz9/d2cT/8J jWHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hPF02d7XDMt/3dY17CUSBjnv60cGAtZEmsl6hmOsUA4=; b=QjpATDySxJn6QRbQ1Ng27BJ4TDK7E4/Z3Lj9oxrmkUJOAqusHX87y5AD46wmMXHJ7/ h1qvO3CGL9Xnyb1hK7WxzHaWAEqLgghB37IJwYwjx9hiK/ASSjvquV4adLTJcp9edfMk XbScPuzT4SIcY9tV6Pnh+yY6SMfA3xOqDQEkwTE2UR5I9ElSCM8Ok/aZO0yxGqlcRAwL +AqpT6CBqDrX5MyH4eVmtk7clQAb+XmEM4Fx5+FECJL47k+/j0khNAk71DOET4TdOhfE 7dRcIcK746fG+Fi1WSdYxftLRaAeJOTW8V3JTDUkvvfvaTb6PRv+o3LS+FrQQlBZia5a 6dGg== X-Gm-Message-State: APjAAAXw/olTmKvCXr0FhfZqiA8YarPvRqk6vRQLry3Ww4bw5seer4mQ AGDp/Rbh2XyadWg+PKBMAbuyTuIk X-Google-Smtp-Source: APXvYqyJOKKUZ3kcSmQKUBolzAAm3CpzGvis/5xxh4Xc99/fOKC02jl6gXeAIYd5D1Q0wadpqbJ82w== X-Received: by 2002:a1c:9c03:: with SMTP id f3mr16758382wme.87.1559652396207; Tue, 04 Jun 2019 05:46:36 -0700 (PDT) Received: from fsr-ub1864-115.ea.freescale.net ([213.233.110.96]) by smtp.gmail.com with ESMTPSA id k125sm35024339wmb.34.2019.06.04.05.46.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 05:46:35 -0700 (PDT) From: Alex Marginean To: u-boot@lists.denx.de Date: Tue, 4 Jun 2019 15:46:25 +0300 Message-Id: <20190604124628.31882-1-alexm.osslist@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Cc: Mingkai Hu , York Sun , Stefan Roese Subject: [U-Boot] [PATCH 1/4 v2] pci: fixed dm_pci_map_bar comment X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean Reviewed-by: Bin Meng --- Changes in v2: - new patch include/pci.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/include/pci.h b/include/pci.h index 508f7bca81..40c7751acf 100644 --- a/include/pci.h +++ b/include/pci.h @@ -1309,12 +1309,14 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, * dm_pci_map_bar() - get a virtual address associated with a BAR region * * Looks up a base address register and finds the physical memory address - * that corresponds to it + * that corresponds to it. + * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on + * type 1 functions. * * @dev: Device to check - * @bar: Bar number to read (numbered from 0) + * @bar: Bar register offset (PCI_BASE_ADDRESS_...) * @flags: Flags for the region type (PCI_REGION_...) - * @return: pointer to the virtual address to use + * @return: pointer to the virtual address to use or 0 on error */ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); From patchwork Tue Jun 4 12:46:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Marginean X-Patchwork-Id: 1109831 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tduFnZgQ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45JBXH3kKrz9s9y for ; Tue, 4 Jun 2019 22:47:27 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3D05AC21D8A; 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Tue, 04 Jun 2019 05:46:37 -0700 (PDT) Received: from fsr-ub1864-115.ea.freescale.net ([213.233.110.96]) by smtp.gmail.com with ESMTPSA id k125sm35024339wmb.34.2019.06.04.05.46.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 05:46:37 -0700 (PDT) From: Alex Marginean To: u-boot@lists.denx.de Date: Tue, 4 Jun 2019 15:46:26 +0300 Message-Id: <20190604124628.31882-2-alexm.osslist@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604124628.31882-1-alexm.osslist@gmail.com> References: <20190604124628.31882-1-alexm.osslist@gmail.com> Cc: Mingkai Hu , York Sun , Stefan Roese Subject: [U-Boot] [PATCH 2/4 v2] drivers: pci: add map_bar support for Enhanced Allocation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean Reviewed-by: Bin Meng --- Changes in v2: - fixed parsing for BAR1+ - fixed an issue with EA entry size - don't look up EA capability structure twice - use phys_addr_t for EA addresses - use kernel MACROS for EA registers drivers/pci/pci-uclass.c | 46 ++++++++++++++++++++++++++++++++++++++++ include/pci.h | 13 ++++++++++++ 2 files changed, 59 insertions(+) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index cf1e7617ae..389aec15ce 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1341,10 +1341,56 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, return bus_addr; } +static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, + int ea_off) +{ + int ea_cnt, i, entry_size; + int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2; + u32 ea_entry; + phys_addr_t addr; + + /* EA capability structure header */ + dm_pci_read_config32(dev, ea_off, &ea_entry); + ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK; + ea_off += PCI_EA_FIRST_ENT; + + for (i = 0; i < ea_cnt; i++, ea_off += entry_size) { + /* Entry header */ + dm_pci_read_config32(dev, ea_off, &ea_entry); + entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2; + + if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id) + continue; + + /* Base address, 1st DW */ + dm_pci_read_config32(dev, ea_off + 4, &ea_entry); + addr = ea_entry & PCI_EA_FIELD_MASK; + if (ea_entry & PCI_EA_IS_64) { + /* Base address, 2nd DW, skip over 4B MaxOffset */ + dm_pci_read_config32(dev, ea_off + 12, &ea_entry); + addr |= ((u64)ea_entry) << 32; + } + + /* size ignored for now */ + return map_physmem(addr, flags, 0); + } + + return 0; +} + void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) { pci_addr_t pci_bus_addr; u32 bar_response; + int ea_off; + + /* + * if the function supports Enhanced Allocation use that instead of + * BARs + */ + ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA); + if (ea_off) + return dm_pci_map_ea_bar(dev, bar, flags, ea_off); /* read BAR address */ dm_pci_read_config32(dev, bar, &bar_response); diff --git a/include/pci.h b/include/pci.h index 40c7751acf..0aab438159 100644 --- a/include/pci.h +++ b/include/pci.h @@ -455,6 +455,17 @@ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM +/* Enhanced Allocation Registers */ +#define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */ +#define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ +#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ +#define PCI_EA_ES 0x00000007 /* Entry Size */ +#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ +/* Base, MaxOffset registers */ +/* bit 0 is reserved */ +#define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ +#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ + /* Include the ID list */ #include @@ -1312,6 +1323,8 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, * that corresponds to it. * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on * type 1 functions. + * Can also be used on type 0 functions that support Enhanced Allocation for + * 32b/64b BARs. Note that duplicate BEI entries are not supported. * * @dev: Device to check * @bar: Bar register offset (PCI_BASE_ADDRESS_...) From patchwork Tue Jun 4 12:46:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Marginean X-Patchwork-Id: 1109832 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="l1eZ+jo9"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45JBXR37cGz9s6w for ; Tue, 4 Jun 2019 22:47:34 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 87B67C21D8E; Tue, 4 Jun 2019 12:47:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B3F7AC21DFA; Tue, 4 Jun 2019 12:46:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DA2FDC21D9A; Tue, 4 Jun 2019 12:46:43 +0000 (UTC) Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by lists.denx.de (Postfix) with ESMTPS id 256C3C21DAF for ; Tue, 4 Jun 2019 12:46:40 +0000 (UTC) Received: by mail-wr1-f66.google.com with SMTP id h1so15688104wro.4 for ; Tue, 04 Jun 2019 05:46:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OReyztix4/+Q/Pv3GhYNA0ZWhwFMfZ6yj4yvLdUryKc=; b=l1eZ+jo9nRVraFGYK+ib0foyv4ED6G/4IJsdAcTTlBDbRlgq84bYAyHb1uUtT5uGKd e38A5wzP1f3p35cZODsUUopyPukRD+QlYKZtW5HKW7XP+EH5exDgcksjG/BnUDUn/ImQ if1tg495yf2P2Xi7P6fA74lh4uqGxUfhrbQhzC5z06hgOYmfVKSvKnRO7NUXswQiurLa odY2dXAh08AOBXx3tVaDwi6QOg0TT2dfaEu88BFdQkHSKoz1C/EaGQ1oLxPFmpM1o1Dx +pcdmjB1OgFJnxeCy1ffMsRH6Y7iTb6i4XnBlutKhc4kyRC937YuKG1Z5pV+V1SzaMZ1 i7nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OReyztix4/+Q/Pv3GhYNA0ZWhwFMfZ6yj4yvLdUryKc=; b=S5KQYYgjf0uF/zmHnZ1/SFNEIKdxc1Z/JPpR9ntZgFAHBw41JFOm8jaOO1NIIMaz// 19mU72B97NHHgB9UdEvE0v6eXqANqk8e5RVSr6Rzc+65HZmdyXaBXLztOBaquV+elayR yYFrWpH2ENHUR9TwyP40E/SWvZhghwOiktqOq10DNbCnV2NtKQsk1IsipF/ZnI9d9rKx ODIXWZ1GUHZqNiQoJ8YFgmnLY4+SVAX95TWHVdCWAXv00jrDKPGxZH5XNDOt+3TMs0m/ bvRRvdy9Wuk97O7HigLpNm7E3x7ogrvSkLBnu0ICNitZgC1bnUJ908lMLmn8ej/mpy37 +EvQ== X-Gm-Message-State: APjAAAVRzFPxLoEEQI34kQpDGaux1jmjL68qHSWvTgBWcpQ1NRHB/d7v 0s6ACjmmZ310B99+qKb5JIUwcQe7 X-Google-Smtp-Source: APXvYqy2fKt0LIXJTIatTZk/OimEGBusWXff5xii+h5xMiDY9SmZ7u9JZbLrHE8tonIa9/0tDMvNxA== X-Received: by 2002:a5d:5607:: with SMTP id l7mr16524429wrv.228.1559652399504; Tue, 04 Jun 2019 05:46:39 -0700 (PDT) Received: from fsr-ub1864-115.ea.freescale.net ([213.233.110.96]) by smtp.gmail.com with ESMTPSA id k125sm35024339wmb.34.2019.06.04.05.46.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 05:46:39 -0700 (PDT) From: Alex Marginean To: u-boot@lists.denx.de Date: Tue, 4 Jun 2019 15:46:27 +0300 Message-Id: <20190604124628.31882-3-alexm.osslist@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604124628.31882-1-alexm.osslist@gmail.com> References: <20190604124628.31882-1-alexm.osslist@gmail.com> Cc: Mingkai Hu , York Sun , Stefan Roese Subject: [U-Boot] [PATCH 3/4 v2] test: dm: Add a test for PCI Enhanced Allocation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This test is built on top of the existing swap_case driver. It adds EA capability structure support to swap_case and uses that to map BARs. BAR1 works as it used to, swapping upper/lower case. BARs 2,4 map to a couple of magic values. Signed-off-by: Alex Marginean Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: - new patch, v1 didn't have a test arch/sandbox/dts/test.dts | 8 +++ arch/sandbox/include/asm/test.h | 13 ++++ drivers/misc/swap_case.c | 102 +++++++++++++++++++++++++++++++- test/dm/pci.c | 50 ++++++++++++++++ 4 files changed, 172 insertions(+), 1 deletion(-) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 46d8a56d0f..dd50a951a8 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -434,6 +434,14 @@ compatible = "sandbox,swap-case"; }; }; + pci@1,0 { + compatible = "pci-generic"; + reg = <0x0800 0 0 0 0>; + emul@0,0 { + compatible = "sandbox,swap-case"; + use-ea; + }; + }; pci@1f,0 { compatible = "pci-generic"; reg = <0xf800 0 0 0 0>; diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index e956a05262..32125f3037 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -19,6 +19,7 @@ #define PCI_CAP_ID_PM_OFFSET 0x50 #define PCI_CAP_ID_EXP_OFFSET 0x60 #define PCI_CAP_ID_MSIX_OFFSET 0x70 +#define PCI_CAP_ID_EA_OFFSET 0x80 #define PCI_EXT_CAP_ID_ERR_OFFSET 0x100 #define PCI_EXT_CAP_ID_VC_OFFSET 0x200 @@ -30,6 +31,18 @@ #define SANDBOX_CLK_RATE 32768 +/* Macros used to test PCI EA capability structure */ +#define PCI_CAP_EA_BASE_LO0 0x00100000 +#define PCI_CAP_EA_BASE_LO1 0x00110000 +#define PCI_CAP_EA_BASE_LO2 0x00120000 +#define PCI_CAP_EA_BASE_LO4 0x00140000 +#define PCI_CAP_EA_BASE_HI2 0x00020000ULL +#define PCI_CAP_EA_BASE_HI4 0x00040000ULL +#define PCI_CAP_EA_SIZE_LO 0x0000ffff +#define PCI_CAP_EA_SIZE_HI 0x00000010ULL +#define PCI_EA_BAR2_MAGIC 0x72727272 +#define PCI_EA_BAR4_MAGIC 0x74747474 + /* System controller driver data */ enum { SYSCON0 = 32, diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c index fa608cec1b..949ef0fdd7 100644 --- a/drivers/misc/swap_case.c +++ b/drivers/misc/swap_case.c @@ -61,11 +61,63 @@ static int sandbox_swap_case_get_devfn(struct udevice *dev) return plat->devfn; } +static int sandbox_swap_use_ea(struct udevice *dev) +{ + return !!ofnode_get_property(dev->node, "use-ea", NULL); +} + +/* Please keep these macros in sync with ea_regs below */ +#define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4) +#define PCI_CAP_ID_EA_ENTRY_CNT 4 +/* Hardcoded EA structure, excluding 1st DW. */ +static const u32 ea_regs[] = { + /* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */ + (2 << 8) | 2, + PCI_CAP_EA_BASE_LO0, + 0, + /* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */ + (1 << 4) | 2, + PCI_CAP_EA_BASE_LO1, + MEM_TEXT_SIZE - 1, + /* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */ + (2 << 4) | 3, + PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64, + PCI_CAP_EA_SIZE_LO, + PCI_CAP_EA_BASE_HI2, + /* BEI=4, ES=4, BAR4 63b Base + 64b MaxOffset */ + (4 << 4) | 4, + PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64, + PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64, + PCI_CAP_EA_BASE_HI4, + PCI_CAP_EA_SIZE_HI, +}; + +static int sandbox_swap_case_read_ea(struct udevice *emul, uint offset, + ulong *valuep, enum pci_size_t size) +{ + u32 reg; + + offset = offset - PCI_CAP_ID_EA_OFFSET - 4; + reg = ea_regs[offset >> 2]; + reg >>= (offset % 4) * 8; + + *valuep = reg; + return 0; +} + static int sandbox_swap_case_read_config(struct udevice *emul, uint offset, ulong *valuep, enum pci_size_t size) { struct swap_case_platdata *plat = dev_get_platdata(emul); + /* + * The content of the EA capability structure is handled elseware to + * keep the switch/case below sane + */ + if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT && + offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE) + return sandbox_swap_case_read_ea(emul, offset, valuep, size); + switch (offset) { case PCI_COMMAND: *valuep = plat->command; @@ -134,9 +186,21 @@ static int sandbox_swap_case_read_config(struct udevice *emul, uint offset, *valuep = PCI_CAP_ID_MSIX_OFFSET; break; case PCI_CAP_ID_MSIX_OFFSET: - *valuep = PCI_CAP_ID_MSIX; + if (sandbox_swap_use_ea(emul)) + *valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX; + else + *valuep = PCI_CAP_ID_MSIX; break; case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT: + if (sandbox_swap_use_ea(emul)) + *valuep = PCI_CAP_ID_EA_OFFSET; + else + *valuep = 0; + break; + case PCI_CAP_ID_EA_OFFSET: + *valuep = (PCI_CAP_ID_EA_ENTRY_CNT << 16) | PCI_CAP_ID_EA; + break; + case PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT: *valuep = 0; break; case PCI_EXT_CAP_ID_ERR_OFFSET: @@ -257,6 +321,9 @@ int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr, return 0; } +static int pci_ea_bar2_magic = PCI_EA_BAR2_MAGIC; +static int pci_ea_bar4_magic = PCI_EA_BAR4_MAGIC; + static int sandbox_swap_case_map_physmem(struct udevice *dev, phys_addr_t addr, unsigned long *lenp, void **ptrp) { @@ -265,9 +332,42 @@ static int sandbox_swap_case_map_physmem(struct udevice *dev, int barnum; int ret; + if (sandbox_swap_use_ea(dev)) { + /* + * only support mapping base address in EA test for now, we + * don't handle mapping an offset inside a BAR. Seems good + * enough for the current test. + */ + switch (addr) { + case (phys_addr_t)PCI_CAP_EA_BASE_LO0: + *ptrp = &priv->op; + *lenp = 4; + break; + case (phys_addr_t)PCI_CAP_EA_BASE_LO1: + *ptrp = priv->mem_text; + *lenp = barinfo[1].size - 1; + break; + case (phys_addr_t)((PCI_CAP_EA_BASE_HI2 << 32) | + PCI_CAP_EA_BASE_LO2): + *ptrp = &pci_ea_bar2_magic; + *lenp = PCI_CAP_EA_SIZE_LO; + break; + case (phys_addr_t)((PCI_CAP_EA_BASE_HI4 << 32) | + PCI_CAP_EA_BASE_LO4): + *ptrp = &pci_ea_bar4_magic; + *lenp = (PCI_CAP_EA_SIZE_HI << 32) | + PCI_CAP_EA_SIZE_LO; + break; + default: + return -ENOENT; + } + return 0; + } + ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset); if (ret) return ret; + if (barnum == 1) { *ptrp = priv->mem_text + offset; avail = barinfo[1].size - offset; diff --git a/test/dm/pci.c b/test/dm/pci.c index a1febd54b7..4657f5d68d 100644 --- a/test/dm/pci.c +++ b/test/dm/pci.c @@ -245,3 +245,53 @@ static int dm_test_pci_cap(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_pci_cap, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test looking up BARs in EA capability structure */ +static int dm_test_pci_ea(struct unit_test_state *uts) +{ + struct udevice *bus, *swap; + void *bar; + int cap; + + /* + * use emulated device mapping function, we're not using real physical + * addresses in this test + */ + sandbox_set_enable_pci_map(true); + + ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus)); + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x01, 0), &swap)); + + /* look up PCI_CAP_ID_EA */ + cap = dm_pci_find_capability(swap, PCI_CAP_ID_EA); + ut_asserteq(PCI_CAP_ID_EA_OFFSET, cap); + + /* test swap case in BAR 1 */ + bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_0, 0); + ut_assertnonnull(bar); + *(int *)bar = 2; /* swap upper/lower */ + + bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0); + ut_assertnonnull(bar); + strcpy(bar, "ea TEST"); + unmap_sysmem(bar); + bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0); + ut_assertnonnull(bar); + ut_asserteq_str("EA test", bar); + + /* test magic values in BARs2, 4; BAR 3 is n/a */ + bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_2, 0); + ut_assertnonnull(bar); + ut_asserteq(PCI_EA_BAR2_MAGIC, *(u32 *)bar); + + bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_3, 0); + ut_assertnull(bar); + + bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_4, 0); + ut_assertnonnull(bar); + ut_asserteq(PCI_EA_BAR4_MAGIC, *(u32 *)bar); + + return 0; +} + +DM_TEST(dm_test_pci_ea, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); From patchwork Tue Jun 4 12:46:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Marginean X-Patchwork-Id: 1109833 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Tue, 04 Jun 2019 05:46:41 -0700 (PDT) Received: from fsr-ub1864-115.ea.freescale.net ([213.233.110.96]) by smtp.gmail.com with ESMTPSA id k125sm35024339wmb.34.2019.06.04.05.46.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 05:46:41 -0700 (PDT) From: Alex Marginean To: u-boot@lists.denx.de Date: Tue, 4 Jun 2019 15:46:28 +0300 Message-Id: <20190604124628.31882-4-alexm.osslist@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604124628.31882-1-alexm.osslist@gmail.com> References: <20190604124628.31882-1-alexm.osslist@gmail.com> Cc: Mingkai Hu , York Sun , Stefan Roese Subject: [U-Boot] [PATCH 4/4 v2] drivers: pci: add API to issue FLR on a PCI function if supported X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean Reviewed-by: Bin Meng --- Changes in v2: - Use kernel PCI_EXP macros for register offsets drivers/pci/pci-uclass.c | 24 ++++++++++++++++++++++++ include/pci.h | 14 ++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 389aec15ce..c74ebf6a76 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1494,6 +1494,30 @@ int dm_pci_find_ext_capability(struct udevice *dev, int cap) return dm_pci_find_next_ext_capability(dev, 0, cap); } +int dm_pci_flr(struct udevice *dev) +{ + int pcie_off; + u32 cap; + + /* look for PCI Express Capability */ + pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP); + if (!pcie_off) + return -ENOENT; + + /* check FLR capability */ + dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap); + if (!(cap & PCI_EXP_DEVCAP_FLR)) + return -ENOENT; + + dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0, + PCI_EXP_DEVCTL_BCR_FLR); + + /* wait 100ms, per PCI spec */ + mdelay(100); + + return 0; +} + UCLASS_DRIVER(pci) = { .id = UCLASS_PCI, .name = "pci", diff --git a/include/pci.h b/include/pci.h index 0aab438159..298d0d4355 100644 --- a/include/pci.h +++ b/include/pci.h @@ -466,6 +466,12 @@ #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ +/* PCI Express capabilities */ +#define PCI_EXP_DEVCAP 4 /* Device capabilities */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCTL 8 /* Device Control */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ + /* Include the ID list */ #include @@ -1426,6 +1432,14 @@ int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap); */ int dm_pci_find_ext_capability(struct udevice *dev, int cap); +/** + * dm_pci_flr() - Perform FLR if the device suppoorts it + * + * @dev: PCI device to reset + * @return: 0 if OK, -ENOENT if FLR is not supported by dev + */ +int dm_pci_flr(struct udevice *dev); + #define dm_pci_virt_to_bus(dev, addr, flags) \ dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \