From patchwork Mon Jun 3 18:59:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1109450 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OnUXwZor"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45HkxT5QQLz9s3Z for ; Tue, 4 Jun 2019 05:04:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726693AbfFCTEM (ORCPT ); Mon, 3 Jun 2019 15:04:12 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:46119 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726136AbfFCTEL (ORCPT ); Mon, 3 Jun 2019 15:04:11 -0400 Received: by mail-lj1-f193.google.com with SMTP id m15so8997253ljg.13; Mon, 03 Jun 2019 12:04:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Ed1+Ug4ZkhEgqg4yLYkOxWrNtJBdRgQSanrCzVExY8=; b=OnUXwZorfdeN+o6jT4EAX7ekTpNwsj8W0pV9F5kO4/Tf0+Bwir5QeUSt7rdYJNhN2H YROp6Rm0XsRi/FyqNVvk7hQuLcxxYszWiU9VNTiVAlon85xW/ktkrS5lpfGhTL5R/ms9 nYz63UDyLBps3oy4SijlPiNxjxJnpdpTLs15MTtp6SWPbObseHaGAY+9fQWYN+kt05m4 Xj2Eqbcxm4mcMnNMO4RKwJA9h0KsqW7db06nRa+/SPACB30iTbpi1fploxYo1qIOrCN3 4+g4xwCm1ngCinlsBDRJsCbg4cH10VChoubdRKMcDHlHkHulAs5O6Rg1Jm2bQbvSPbzm sPFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Ed1+Ug4ZkhEgqg4yLYkOxWrNtJBdRgQSanrCzVExY8=; b=BNHfrUybVjTAOVEzT5qJKz+vS4hfWn/vP3urHkeNCWXuJGiiNe7MerBMXbSw7dQuN+ 9jmPt0TVZVOKh3ImwmTuaXKH6gSPZRlioPpr1MhCnYJ2a2RH6FakB8TYEXCzXOW+kEx5 BHtTQCdZ3owDtPsGVnwNxQS6I5qblxECXrc3t5V3BoMKWM11Ho3tdXbQQBISJdfFIJb+ g1O6loR8jmILKPxamdM/eYupit5xIvZ2tt0WBzc/OQIsvenffK8CQNtZZV7weh6rGvpk gqtSBSKbNWisRhfgIPFNOOg4iosGZQ3d6G09xf7/3WVBxnDb72HYZSpimpKYDfPMNFuV q8CQ== X-Gm-Message-State: APjAAAUFj6DK4RHiTxem1pxaPBqH4PJR//7yqStUdY43L+zhuU2XvpdQ kyBPxNmxa40pNAWv8gg16QA= X-Google-Smtp-Source: APXvYqzook9Q+dtFUsA4V7UwiDsAmPzQcv83LPx6lkYElaI15HMFqLbfMRk7aqCFtViZJsg7BIwrvw== X-Received: by 2002:a2e:8785:: with SMTP id n5mr7696556lji.215.1559588649448; Mon, 03 Jun 2019 12:04:09 -0700 (PDT) Received: from localhost.localdomain ([94.29.35.141]) by smtp.gmail.com with ESMTPSA id l22sm2768805ljb.39.2019.06.03.12.04.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jun 2019 12:04:07 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 01/10] clocksource/drivers/tegra: Support per-CPU timers on all Tegra's Date: Mon, 3 Jun 2019 21:59:39 +0300 Message-Id: <20190603185948.30438-2-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603185948.30438-1-digetx@gmail.com> References: <20190603185948.30438-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Assign TMR1-4 per-CPU core on 32bit Tegra's in a way it is done for Tegra210. In a result each core can handle its own timer events, less code is unique to ARM64 and Tegra's clock events driver now has higher rating on all Tegra's, replacing the ARM's TWD timer which isn't very accurate due to the clock rate jitter caused by CPU frequency scaling. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 120 ++++++++++------------------ 1 file changed, 43 insertions(+), 77 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 919b3568c495..58e8bb6deac9 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -49,13 +49,18 @@ #define TIMER_PCR_INTR_CLR BIT(30) #ifdef CONFIG_ARM -#define TIMER_CPU0 0x50 /* TIMER3 */ +#define TIMER_CPU0 0x00 /* TIMER1 */ +#define TIMER_CPU2 0x50 /* TIMER3 */ +#define TIMER1_IRQ_IDX 0 +#define IRQ_IDX_FOR_CPU(cpu) (TIMER1_IRQ_IDX + cpu) +#define TIMER_BASE_FOR_CPU(cpu) \ + (((cpu) & 1) * 8 + ((cpu) < 2 ? TIMER_CPU0 : TIMER_CPU2)) #else #define TIMER_CPU0 0x90 /* TIMER10 */ #define TIMER10_IRQ_IDX 10 #define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) -#endif #define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) +#endif static u32 usec_config; static void __iomem *timer_reg_base; @@ -118,7 +123,6 @@ static void tegra_timer_resume(struct clock_event_device *evt) writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); } -#ifdef CONFIG_ARM64 static DEFINE_PER_CPU(struct timer_of, tegra_to) = { .flags = TIMER_OF_CLOCK | TIMER_OF_BASE, @@ -159,33 +163,8 @@ static int tegra_timer_stop(unsigned int cpu) return 0; } -#else /* CONFIG_ARM */ -static struct timer_of tegra_to = { - .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ, - - .clkevt = { - .name = "tegra_timer", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_DYNIRQ, - .set_next_event = tegra_timer_set_next_event, - .set_state_shutdown = tegra_timer_shutdown, - .set_state_periodic = tegra_timer_set_periodic, - .set_state_oneshot = tegra_timer_shutdown, - .tick_resume = tegra_timer_shutdown, - .suspend = tegra_timer_suspend, - .resume = tegra_timer_resume, - .cpumask = cpu_possible_mask, - }, - - .of_irq = { - .index = 2, - .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, - .handler = tegra_timer_isr, - }, -}; +#ifdef CONFIG_ARM static u64 notrace tegra_read_sched_clock(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); @@ -222,10 +201,12 @@ static struct clocksource suspend_rtc_clocksource = { }; #endif -static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) +static int tegra_init_timer(struct device_node *np, bool tegra20) { - int ret = 0; + struct timer_of *to; + int cpu, ret; + to = this_cpu_ptr(&tegra_to); ret = timer_of_init(np, to); if (ret < 0) goto out; @@ -267,29 +248,19 @@ static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) goto out; } - writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG); - -out: - return ret; -} - -#ifdef CONFIG_ARM64 -static int __init tegra_init_timer(struct device_node *np) -{ - int cpu, ret = 0; - struct timer_of *to; - - to = this_cpu_ptr(&tegra_to); - ret = tegra_timer_common_init(np, to); - if (ret < 0) - goto out; + writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); for_each_possible_cpu(cpu) { - struct timer_of *cpu_to; + struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); + + /* + * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the + * parent clock. + */ + if (tegra20) + cpu_to->of_clk.rate = 1000000; - cpu_to = per_cpu_ptr(&tegra_to, cpu); cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu); - cpu_to->of_clk.rate = timer_of_rate(to); cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); @@ -331,43 +302,39 @@ static int __init tegra_init_timer(struct device_node *np) timer_of_cleanup(to); return ret; } + +#ifdef CONFIG_ARM64 +static int __init tegra210_init_timer(struct device_node *np) +{ + return tegra_init_timer(np, false); +} +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); #else /* CONFIG_ARM */ -static int __init tegra_init_timer(struct device_node *np) +static int __init tegra20_init_timer(struct device_node *np) { - int ret = 0; + struct timer_of *to; + int err; - ret = tegra_timer_common_init(np, &tegra_to); - if (ret < 0) - goto out; + err = tegra_init_timer(np, true); + if (err) + return err; - tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0); - tegra_to.of_clk.rate = 1000000; /* microsecond timer */ + to = this_cpu_ptr(&tegra_to); sched_clock_register(tegra_read_sched_clock, 32, - timer_of_rate(&tegra_to)); - ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", timer_of_rate(&tegra_to), + timer_of_rate(to)); + err = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", timer_of_rate(to), 300, 32, clocksource_mmio_readl_up); - if (ret) { - pr_err("Failed to register clocksource\n"); - goto out; - } + if (err) + pr_err("Failed to register clocksource: %d\n", err); tegra_delay_timer.read_current_timer = tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = timer_of_rate(&tegra_to); + tegra_delay_timer.freq = timer_of_rate(to); register_current_timer_delay(&tegra_delay_timer); - clockevents_config_and_register(&tegra_to.clkevt, - timer_of_rate(&tegra_to), - 0x1, - 0x1fffffff); - - return ret; -out: - timer_of_cleanup(&tegra_to); - - return ret; + return 0; } static int __init tegra20_init_rtc(struct device_node *np) @@ -383,6 +350,5 @@ static int __init tegra20_init_rtc(struct device_node *np) return 0; } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); #endif -TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer); -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer); From patchwork Mon Jun 3 18:59:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1109458 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; 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Mon, 03 Jun 2019 12:04:11 -0700 (PDT) Received: from localhost.localdomain ([94.29.35.141]) by smtp.gmail.com with ESMTPSA id l22sm2768805ljb.39.2019.06.03.12.04.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jun 2019 12:04:10 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 02/10] clocksource/drivers/tegra: Unify timer code Date: Mon, 3 Jun 2019 21:59:40 +0300 Message-Id: <20190603185948.30438-3-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603185948.30438-1-digetx@gmail.com> References: <20190603185948.30438-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra132 is 64bit platform and it has the tegra20-timer hardware unit. Right now the corresponding timer code isn't compiled for ARM64, remove ifdef'iness from the code and compile tegra20-timer for both 32 and 64 bit platforms. Also note that like the older generations, Tegra210 has the microseconds counter, hence the timer_us clocksource is now made available for Tegra210 as well. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 111 +++++++++++++++------------- 1 file changed, 60 insertions(+), 51 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 58e8bb6deac9..57e7aa2b80a3 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -30,10 +30,6 @@ #include "timer-of.h" -#ifdef CONFIG_ARM -#include -#endif - #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c #define RTC_MILLISECONDS 0x10 @@ -48,25 +44,17 @@ #define TIMER_PCR 0x4 #define TIMER_PCR_INTR_CLR BIT(30) -#ifdef CONFIG_ARM -#define TIMER_CPU0 0x00 /* TIMER1 */ -#define TIMER_CPU2 0x50 /* TIMER3 */ +#define TIMER1_BASE 0x00 +#define TIMER2_BASE 0x08 +#define TIMER3_BASE 0x50 +#define TIMER4_BASE 0x58 +#define TIMER10_BASE 0x90 + #define TIMER1_IRQ_IDX 0 -#define IRQ_IDX_FOR_CPU(cpu) (TIMER1_IRQ_IDX + cpu) -#define TIMER_BASE_FOR_CPU(cpu) \ - (((cpu) & 1) * 8 + ((cpu) < 2 ? TIMER_CPU0 : TIMER_CPU2)) -#else -#define TIMER_CPU0 0x90 /* TIMER10 */ #define TIMER10_IRQ_IDX 10 -#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) -#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) -#endif static u32 usec_config; static void __iomem *timer_reg_base; -#ifdef CONFIG_ARM -static struct delay_timer tegra_delay_timer; -#endif static int tegra_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) @@ -164,17 +152,23 @@ static int tegra_timer_stop(unsigned int cpu) return 0; } -#ifdef CONFIG_ARM static u64 notrace tegra_read_sched_clock(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); } +#ifdef CONFIG_ARM static unsigned long tegra_delay_timer_read_counter_long(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); } +static struct delay_timer tegra_delay_timer = { + .read_current_timer = tegra_delay_timer_read_counter_long, + .freq = 1000000, +}; +#endif + static struct timer_of suspend_rtc_to = { .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, }; @@ -199,9 +193,34 @@ static struct clocksource suspend_rtc_clocksource = { .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, }; -#endif -static int tegra_init_timer(struct device_node *np, bool tegra20) +static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20) +{ + if (tegra20) { + switch (cpu) { + case 0: + return TIMER1_BASE; + case 1: + return TIMER2_BASE; + case 2: + return TIMER3_BASE; + default: + return TIMER4_BASE; + } + } + + return TIMER10_BASE + cpu * 8; +} + +static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) +{ + if (tegra20) + return TIMER1_IRQ_IDX + cpu; + + return TIMER10_IRQ_IDX + cpu; +} + +static int __init tegra_init_timer(struct device_node *np, bool tegra20) { struct timer_of *to; int cpu, ret; @@ -252,6 +271,8 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); + unsigned int base = tegra_base_for_cpu(cpu, tegra20); + unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20); /* * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the @@ -260,10 +281,10 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) if (tegra20) cpu_to->of_clk.rate = 1000000; - cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu); + cpu_to = per_cpu_ptr(&tegra_to, cpu); + cpu_to->of_base.base = timer_reg_base + base; cpu_to->clkevt.cpumask = cpumask_of(cpu); - cpu_to->clkevt.irq = - irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); + cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { pr_err("%s: can't map IRQ for CPU%d\n", __func__, cpu); @@ -283,6 +304,18 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) } } + sched_clock_register(tegra_read_sched_clock, 32, 1000000); + + ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", 1000000, + 300, 32, clocksource_mmio_readl_up); + if (ret) + pr_err("failed to register clocksource: %d\n", ret); + +#ifdef CONFIG_ARM + register_current_timer_delay(&tegra_delay_timer); +#endif + cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, tegra_timer_stop); @@ -303,39 +336,17 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) return ret; } -#ifdef CONFIG_ARM64 static int __init tegra210_init_timer(struct device_node *np) { return tegra_init_timer(np, false); } TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); -#else /* CONFIG_ARM */ + static int __init tegra20_init_timer(struct device_node *np) { - struct timer_of *to; - int err; - - err = tegra_init_timer(np, true); - if (err) - return err; - - to = this_cpu_ptr(&tegra_to); - - sched_clock_register(tegra_read_sched_clock, 32, - timer_of_rate(to)); - err = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", timer_of_rate(to), - 300, 32, clocksource_mmio_readl_up); - if (err) - pr_err("Failed to register clocksource: %d\n", err); - - tegra_delay_timer.read_current_timer = - tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = timer_of_rate(to); - register_current_timer_delay(&tegra_delay_timer); - - return 0; + return tegra_init_timer(np, true); } +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); static int __init tegra20_init_rtc(struct device_node *np) { @@ -350,5 +361,3 @@ static int __init tegra20_init_rtc(struct device_node *np) return 0; } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); -#endif From patchwork Mon Jun 3 18:59:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1109459 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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Mon, 03 Jun 2019 12:04:13 -0700 (PDT) Received: from localhost.localdomain ([94.29.35.141]) by smtp.gmail.com with ESMTPSA id l22sm2768805ljb.39.2019.06.03.12.04.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jun 2019 12:04:12 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/10] clocksource/drivers/tegra: Reset hardware state on init Date: Mon, 3 Jun 2019 21:59:41 +0300 Message-Id: <20190603185948.30438-4-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603185948.30438-1-digetx@gmail.com> References: <20190603185948.30438-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Reset timer's hardware state to ensure that initially it is in a predictable state. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 57e7aa2b80a3..739f83fdb318 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -132,6 +132,9 @@ static int tegra_timer_setup(unsigned int cpu) { struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + writel(0, timer_of_base(to) + TIMER_PTV); + writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); + irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); From patchwork Mon Jun 3 18:59:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1109455 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ctz2j1CP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45HkyD13YYz9s9y for ; Tue, 4 Jun 2019 05:04:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726786AbfFCTET (ORCPT ); Mon, 3 Jun 2019 15:04:19 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:35858 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726776AbfFCTES (ORCPT ); Mon, 3 Jun 2019 15:04:18 -0400 Received: by mail-lf1-f67.google.com with SMTP id q26so14465847lfc.3; Mon, 03 Jun 2019 12:04:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a9tPoKh6v4/2G+YqR2rAKuMQIIR4hdO1ztimbmlKniY=; b=ctz2j1CPsOaRHbcP3FCfLFeKnXv1Q+au7eLGREH7GC+Wt3xgU775ylu3EmR/1ws7FB K2DVmU2k2MuTRFIHGEXM+skt8cFnvh57fdrkHqp1ntjTVR/BnogxucDM/4L+KbfuprEy oVdikngLg+KDQ3ZFgWnIZrzm7nAfio00KB+FkwKO0KZg3u1eClV22hWx5z9y+fywKxwb XQmoLU6S7oFLfVpcC8tczLJ9o77QdmI8FSCLGsor9Rul2hscjK9YQyueuleVSAVPJBIM otqUYW+T1mgsVuTqSulLWlfneJl2+h7KzFq1jvdbO12buZGOVRe2dK62mMF+FZ3QPNuc oSbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a9tPoKh6v4/2G+YqR2rAKuMQIIR4hdO1ztimbmlKniY=; b=W0tTx/GqUmkPINGgeGLpjV7Zzul+g/nUnhnMDAjTgJ7imAwKsDlyXIb/AqCkoWjCda MiT+wlq3P3S1JXeLX6wlXsNPcMXvnx1H23M+wQU8MixJMKv/P6bEkPr7jGhlu8ACyqwL G1mUBDLnphF8hAar2ZG+eK8sIkYDRkrIepwWMBVKsIFz7AIrX6AmAcTMFNA5W/eJ/h/I aECl/balMOiaplchpeALg0m8HpO2RdN+qJwb1q9RqyxkQpDfurHcNlUFWlR7veu6GmTV /DJg5JpTUSy0WNpz2M6AZVqEWgXBwt4sm8IOYR8mq+VGdQ001wgHCpaXVErDenpzhsWu U2ag== X-Gm-Message-State: APjAAAXG52RNvIYoWBdWHjpFritdJ67j3iLjYnxCQ0jdcLL1ezGpzruZ 4uQMSXcUbFXzbYuhNwpiVvI= X-Google-Smtp-Source: APXvYqxixX828rCbWc6NDvLD9nrlJyu6+Gr/f5AKQPDc72s7CPX9d1V1Uw9ToNaaV8OqYr7AUxp9fA== X-Received: by 2002:ac2:5324:: with SMTP id f4mr14529107lfh.156.1559588655130; Mon, 03 Jun 2019 12:04:15 -0700 (PDT) Received: from localhost.localdomain ([94.29.35.141]) by smtp.gmail.com with ESMTPSA id l22sm2768805ljb.39.2019.06.03.12.04.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jun 2019 12:04:13 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 04/10] clocksource/drivers/tegra: Replace readl/writel with relaxed versions Date: Mon, 3 Jun 2019 21:59:42 +0300 Message-Id: <20190603185948.30438-5-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603185948.30438-1-digetx@gmail.com> References: <20190603185948.30438-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The readl/writel functions are inserting memory barrier to ensure that outstanding memory writes are completed, this results in L2 cache syncing being done on Tegra20 and Tegra30 which isn't a very cheap operation. Replace all readl/writel occurrences in the code with the relaxed versions since there is no need for the memory-access syncing. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 35 +++++++++++++++-------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 739f83fdb318..55e9b3e1fbeb 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -61,9 +61,9 @@ static int tegra_timer_set_next_event(unsigned long cycles, { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PTV_EN | - ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ - reg_base + TIMER_PTV); + writel_relaxed(TIMER_PTV_EN | + ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ + reg_base + TIMER_PTV); return 0; } @@ -72,7 +72,7 @@ static int tegra_timer_shutdown(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(0, reg_base + TIMER_PTV); + writel_relaxed(0, reg_base + TIMER_PTV); return 0; } @@ -81,9 +81,9 @@ static int tegra_timer_set_periodic(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PTV_EN | TIMER_PTV_PER | - ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), - reg_base + TIMER_PTV); + writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | + ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), + reg_base + TIMER_PTV); return 0; } @@ -93,7 +93,7 @@ static irqreturn_t tegra_timer_isr(int irq, void *dev_id) struct clock_event_device *evt = (struct clock_event_device *)dev_id; void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); evt->event_handler(evt); return IRQ_HANDLED; @@ -103,12 +103,12 @@ static void tegra_timer_suspend(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); } static void tegra_timer_resume(struct clock_event_device *evt) { - writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); + writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); } static DEFINE_PER_CPU(struct timer_of, tegra_to) = { @@ -132,8 +132,8 @@ static int tegra_timer_setup(unsigned int cpu) { struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); - writel(0, timer_of_base(to) + TIMER_PTV); - writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); + writel_relaxed(0, timer_of_base(to) + TIMER_PTV); + writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); @@ -157,13 +157,13 @@ static int tegra_timer_stop(unsigned int cpu) static u64 notrace tegra_read_sched_clock(void) { - return readl(timer_reg_base + TIMERUS_CNTR_1US); + return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); } #ifdef CONFIG_ARM static unsigned long tegra_delay_timer_read_counter_long(void) { - return readl(timer_reg_base + TIMERUS_CNTR_1US); + return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); } static struct delay_timer tegra_delay_timer = { @@ -184,8 +184,9 @@ static struct timer_of suspend_rtc_to = { */ static u64 tegra_rtc_read_ms(struct clocksource *cs) { - u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS); - u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS); + void __iomem *reg_base = timer_of_base(&suspend_rtc_to); + u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); + u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); return (u64)s * MSEC_PER_SEC + ms; } @@ -270,7 +271,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) goto out; } - writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); + writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); 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Mon, 03 Jun 2019 12:04:15 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 05/10] clocksource/drivers/tegra: Release all IRQ's on request_irq() error Date: Mon, 3 Jun 2019 21:59:43 +0300 Message-Id: <20190603185948.30438-6-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603185948.30438-1-digetx@gmail.com> References: <20190603185948.30438-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Release all requested IRQ's on the request error to properly clean up allocated resources. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 55e9b3e1fbeb..18b81d814b3b 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -293,7 +293,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) pr_err("%s: can't map IRQ for CPU%d\n", __func__, cpu); ret = -EINVAL; - goto out; + goto out_irq; } irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); @@ -303,7 +303,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) if (ret) { pr_err("%s: cannot setup irq %d for CPU%d\n", __func__, cpu_to->clkevt.irq, cpu); - ret = -EINVAL; + irq_dispose_mapping(cpu_to->clkevt.irq); + cpu_to->clkevt.irq = 0; goto out_irq; } } From patchwork Mon Jun 3 18:59:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1109456 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kZ93Ail9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45HkyP6Fswz9s9y for ; Tue, 4 Jun 2019 05:05:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726972AbfFCTEv (ORCPT ); Mon, 3 Jun 2019 15:04:51 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:44468 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726658AbfFCTEV (ORCPT ); Mon, 3 Jun 2019 15:04:21 -0400 Received: by mail-lf1-f67.google.com with SMTP id r15so14439469lfm.11; Mon, 03 Jun 2019 12:04:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FVedIOrmGpOcaFRJmHXTB7UeLVU4DsMUhFHAazuTakE=; b=kZ93Ail9+7vDuf/EP+z/Uk5Zc5nCngrmdm3PerDt+ORY1Bt3tlBRhNNWOPcfSwp3DS SISLTt9v3b06b4mgHNwLSBcCKh4xelPKDyFy44NPgZ6Tzlq/ZN3gVXKiLkPqJbJ7l4Ke Nz+U/CNv0HMP9Pi4CYrZkRLqZASmnRM9rG6VOsbzJcmKTlZMjaVN2bzZoXFa2lvEVwML 8knF+J/+pQROQzZkZ12Upx+2MCN82P7JRgu9cvndPWEPz2jkgvQNAHBff9ulwMOQlHlg ZHeUZTgk1jS9D4fmvGhivvdw74f1ChGrTmqhmilvrlrIc4lOOvbvVPxpCEfF6Zcp7IiX tGVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FVedIOrmGpOcaFRJmHXTB7UeLVU4DsMUhFHAazuTakE=; b=efK0DpdTMVTLfh/+IumbSBe+rg8VEwDBveMn0W7s8B/k4qgIKNbnpVpOuDJAj9eYX7 LVGrhGrqupoqB1Gk4k9hpjmoxauMH0ROJ7vHAecciz3QLGWXLwk06HFo+bVGVYQPdr6U sEeao0ozXzZb966Da3Bso5lAxNYLke2pN918rjChM8dKek/w+BP0xr/MrjQQVZtfwoj6 fByldXFKxQvwonXhezfpbxis6zjufnGTDmQscnu+TZM4m9NWP/S4JqAm9RTY58Fk8I5v l7TvuNoHTS72FjqUZAYqdjCrrPXX/ahV48JC7OXy+nFHjnAuCpiqLjeTejFlZSTKMe7Q geLA== X-Gm-Message-State: APjAAAXHu6uN2Z3Zgr0Xumnk90U7pZNV8SMxprVF4jwFw5lFxvQymDuX DoWDMY5MnhMIqYSl3gMk1b4= X-Google-Smtp-Source: APXvYqxdEv2Vn5T6ahWoa48i7Ub6eHb9RjI+J50YkgWmeZtzMHxY4+1+NkxtFb+4L4CNy54kOrA9uQ== X-Received: by 2002:a19:e34e:: with SMTP id c14mr14279884lfk.47.1559588658239; Mon, 03 Jun 2019 12:04:18 -0700 (PDT) Received: from localhost.localdomain ([94.29.35.141]) by smtp.gmail.com with ESMTPSA id l22sm2768805ljb.39.2019.06.03.12.04.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jun 2019 12:04:17 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/10] clocksource/drivers/tegra: Minor code clean up Date: Mon, 3 Jun 2019 21:59:44 +0300 Message-Id: <20190603185948.30438-7-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603185948.30438-1-digetx@gmail.com> References: <20190603185948.30438-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Correct typo and use proper upper casing for acronyms in the comments, use common style for error messages, prepend error messages with "tegra-timer:", add error message for cpuhp_setup_state() failure and clean up whitespaces in the code to fix checkpatch warnings. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 43 ++++++++++++++++------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 18b81d814b3b..12784a82fd57 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -15,6 +15,8 @@ * */ +#define pr_fmt(fmt) "tegra-timer: " fmt + #include #include #include @@ -30,13 +32,13 @@ #include "timer-of.h" -#define RTC_SECONDS 0x08 -#define RTC_SHADOW_SECONDS 0x0c -#define RTC_MILLISECONDS 0x10 +#define RTC_SECONDS 0x08 +#define RTC_SHADOW_SECONDS 0x0c +#define RTC_MILLISECONDS 0x10 -#define TIMERUS_CNTR_1US 0x10 -#define TIMERUS_USEC_CFG 0x14 -#define TIMERUS_CNTR_FREEZE 0x4c +#define TIMERUS_CNTR_1US 0x10 +#define TIMERUS_USEC_CFG 0x14 +#define TIMERUS_CNTR_FREEZE 0x4c #define TIMER_PTV 0x0 #define TIMER_PTV_EN BIT(31) @@ -57,7 +59,7 @@ static u32 usec_config; static void __iomem *timer_reg_base; static int tegra_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) + struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); @@ -178,15 +180,17 @@ static struct timer_of suspend_rtc_to = { /* * tegra_rtc_read - Reads the Tegra RTC registers - * Care must be taken that this funciton is not called while the + * Care must be taken that this function is not called while the * tegra_rtc driver could be executing to avoid race conditions * on the RTC shadow register */ static u64 tegra_rtc_read_ms(struct clocksource *cs) { void __iomem *reg_base = timer_of_base(&suspend_rtc_to); + u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); + return (u64)s * MSEC_PER_SEC + ms; } @@ -231,7 +235,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) to = this_cpu_ptr(&tegra_to); ret = timer_of_init(np, to); - if (ret < 0) + if (ret) goto out; timer_reg_base = timer_of_base(to); @@ -290,8 +294,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { - pr_err("%s: can't map IRQ for CPU%d\n", - __func__, cpu); + pr_err("failed to map irq for cpu%d\n", cpu); ret = -EINVAL; goto out_irq; } @@ -301,8 +304,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) IRQF_TIMER | IRQF_NOBALANCING, cpu_to->clkevt.name, &cpu_to->clkevt); if (ret) { - pr_err("%s: cannot setup irq %d for CPU%d\n", - __func__, cpu_to->clkevt.irq, cpu); + pr_err("failed to set up irq for cpu%d: %d\n", + cpu, ret); irq_dispose_mapping(cpu_to->clkevt.irq); cpu_to->clkevt.irq = 0; goto out_irq; @@ -321,11 +324,14 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) register_current_timer_delay(&tegra_delay_timer); #endif - cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, - "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, - tegra_timer_stop); + ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, + "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, + tegra_timer_stop); + if (ret) + pr_err("failed to set up cpu hp state: %d\n", ret); return ret; + out_irq: for_each_possible_cpu(cpu) { struct timer_of *cpu_to; @@ -338,6 +344,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) } out: timer_of_cleanup(to); + return ret; } @@ -361,8 +368,6 @@ static int __init tegra20_init_rtc(struct device_node *np) if (ret) return ret; - clocksource_register_hz(&suspend_rtc_clocksource, 1000); - - return 0; + return clocksource_register_hz(&suspend_rtc_clocksource, 1000); } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); From patchwork Mon Jun 3 18:59:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1109451 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 03 Jun 2019 12:04:20 -0700 (PDT) Received: from localhost.localdomain ([94.29.35.141]) by smtp.gmail.com with ESMTPSA id l22sm2768805ljb.39.2019.06.03.12.04.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jun 2019 12:04:19 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 07/10] clocksource/drivers/tegra: Use SPDX identifier Date: Mon, 3 Jun 2019 21:59:45 +0300 Message-Id: <20190603185948.30438-8-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603185948.30438-1-digetx@gmail.com> References: <20190603185948.30438-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Use SPDX tag for the license identification instead of a free form text to aid license-checking automation and for brevity. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 12784a82fd57..1a3ee928e9a5 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -1,18 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * + * Author: Colin Cross */ #define pr_fmt(fmt) "tegra-timer: " fmt From patchwork Mon Jun 3 18:59:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1109454 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XlCcbZXo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Hkxz2qF9z9s3l for ; Tue, 4 Jun 2019 05:04:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726867AbfFCTEY (ORCPT ); Mon, 3 Jun 2019 15:04:24 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:46513 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726842AbfFCTEX (ORCPT ); Mon, 3 Jun 2019 15:04:23 -0400 Received: by mail-lf1-f66.google.com with SMTP id l26so14429595lfh.13; Mon, 03 Jun 2019 12:04:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xLtUN7lXG9KPhRHs985aJMRbWTp9lCvBb94mMbrLpok=; b=XlCcbZXoDuvKN6jiSsX72oFNR8QupD/HNRosq4Y1f42OjPcCXPnpw6+y9nClElj1Kk XnS7flmeGNWwSVFC8m1+NLTmDXlW2Xj+1w6nHcUsyA2SlHfVyJJ77fyZdJuJTqg+81EJ j45t2f6omx2R9zlFldSPQfrrRG1zkpiLzc1u8onUiPR4QSLHZyR6YV+HniHdlF3kooUz G80mCs2PdTbe37DWkbvPiU/pURVC3f/G7aZVPtDiZXHRWJrpAFY35yf0otDPR1wu5aLn qhoFkLtJIY8U9omraXC3+B+utyF0G6aS9xPi4my1bpCJSxwGZToDkklkDMy4hXlrM+WX dDgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xLtUN7lXG9KPhRHs985aJMRbWTp9lCvBb94mMbrLpok=; b=G0iVIRjR0ih39/mJ0d47pnpD7g+KTaxnVeKCYOqNcWPw9IogWhTiUb9cwY14FO61ai x/pxmbymqRxBDRPxF6Bo2xYTKRV43wUNw3lSv+m9kxE+Z/aWAkjFlcFlteqC4oyne9Vr RjFtincIeZqiSc/VEg4Tm5P/lfoxIWc/hKOYLzroNiSiDmNWv/Pb9GsOrSqIMi9w09XI nfk6g0pIZ6F6es+YSegT/0qhIilmp99tTFYa8Maq5ESG7KX3aVhs9b3MzsIttw1fFO6m 4UYOfgrgKRk/vgulfxwTjx1Sz0bjVB52e/vPnwlgL9QpZEKnT5qXBX/qx3xM0fw6KjxY ijJg== X-Gm-Message-State: APjAAAVJm95D5gPBTcPoRPHE+oDf3d5ys80ZaBJ6nOSbbn32uKxe0Hcp X0+y+ynAkrzwkljhpTof5Jg= X-Google-Smtp-Source: APXvYqyIrpQTRMo2iHa9+63PmcTehopN8Jdz6wy41nwW1tr4mbaxMGxsc4Rw1NYjC9m5Vhg3GaCzXw== X-Received: by 2002:ac2:4565:: with SMTP id k5mr11068824lfm.170.1559588662180; Mon, 03 Jun 2019 12:04:22 -0700 (PDT) Received: from localhost.localdomain ([94.29.35.141]) by smtp.gmail.com with ESMTPSA id l22sm2768805ljb.39.2019.06.03.12.04.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jun 2019 12:04:21 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/10] clocksource/drivers/tegra: Support COMPILE_TEST universally Date: Mon, 3 Jun 2019 21:59:46 +0300 Message-Id: <20190603185948.30438-9-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603185948.30438-1-digetx@gmail.com> References: <20190603185948.30438-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Remove build dependency on ARM for compile-testing to allow non-arch specific build-bots (like Intel's test robot) to compile the driver and report about problems. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 3300739edce4..d17a347e813a 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -140,7 +140,7 @@ config TEGRA_TIMER bool "Tegra timer driver" if COMPILE_TEST select CLKSRC_MMIO select TIMER_OF - depends on ARM || ARM64 + depends on ARCH_TEGRA || COMPILE_TEST help Enables support for the Tegra driver. From patchwork Mon Jun 3 18:59:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1109453 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MXQ+RBFt"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Hkxw6lP5z9s9y for ; Tue, 4 Jun 2019 05:04:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726881AbfFCTE1 (ORCPT ); Mon, 3 Jun 2019 15:04:27 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:37375 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726875AbfFCTEZ (ORCPT ); Mon, 3 Jun 2019 15:04:25 -0400 Received: by mail-lj1-f194.google.com with SMTP id 131so4744734ljf.4; Mon, 03 Jun 2019 12:04:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lQRtuyDNyV7dZwY09phwCLey90itYrHs73do7JB/dQA=; b=MXQ+RBFtOXNg/VRjjbgw8XBWSoPNfjHfE0PsR2TDj5a5pfsTeDLIl5RVtB2y4E4bYt LVlXPqfg9InuDP+DrFtOt5Mx0tFpQp5OLsWh4/Y4R1GotPV06Nd+bECYj21/4F7xZ/fD niLXBCpTy+DNJ2aP5FRL4cKB2HBjHdrvpbqUirdZRkbVJoYKvnPrJJWCCL8q3xsrAx3X aGwllE0HRSfrSwdWLyNfFSaq3E/7dhuzahk0El+iMjdKXBFSbtjg3Jw9Ao0jRLyTZmxG h0+XbzbmRJH09SDEVG0Xzg+cxvrZC6lSe8r+fqILygiFPc4txZ79BI5UQFVGlnGfSKrW I/Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lQRtuyDNyV7dZwY09phwCLey90itYrHs73do7JB/dQA=; b=WsqW1CekkxG2ZXDgd9o9kxVsAyQSv5OaH0+cwWKCF9+c5kokeoRPNZyHOMyTewj+jf jYYD9MUbIjH3aI+36ChmquU9LytynChMca1z1W1CN9mspQ532Rlh0UxpPNr/d0LHTBRA ANV+xC+bqHteJ8fYWUaYsnMHbB65UEhC4mrlsarPEkHDh519hP4ZMSQBtRe8dryLvprf yixVGSIYfaRbWSiQcJtt0plty/ACqnrDH9lcFu/4OVIf8zU8AWCjRk7G4RPfJv7Sa5vf k1Sp/lPUd/KsJCnFKXzMkImL8QZsdtFrBuZjjVp71QB/O6BhusJZ43nNHjKVKr2VofjC nY4Q== X-Gm-Message-State: APjAAAXmqMwxABP9mEqYlqEPOcX/AAiGlVrS0qNuE3KMG3P4xTzxHs8q 6uG7/3g7hNc7xmv3i1X94jrLKYeD X-Google-Smtp-Source: APXvYqwlQaCv2KcKz+y9O1+3AEczxnu64bEZRIR3+igJCJoXV4ZPjAqBhBuw4VQQuPPjXrUrHdZTGw== X-Received: by 2002:a2e:8583:: with SMTP id b3mr14717192lji.136.1559588663943; Mon, 03 Jun 2019 12:04:23 -0700 (PDT) Received: from localhost.localdomain ([94.29.35.141]) by smtp.gmail.com with ESMTPSA id l22sm2768805ljb.39.2019.06.03.12.04.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jun 2019 12:04:22 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/10] clocksource/drivers/tegra: Lower clocksource rating for some Tegra's Date: Mon, 3 Jun 2019 21:59:47 +0300 Message-Id: <20190603185948.30438-10-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603185948.30438-1-digetx@gmail.com> References: <20190603185948.30438-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Arch-timer is more preferable for a range of Tegra SoC generations as it has higher precision and is not affect by any kind of problems. Pointed-out-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 30 +++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 1a3ee928e9a5..9406855781ff 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -107,7 +107,6 @@ static DEFINE_PER_CPU(struct timer_of, tegra_to) = { .clkevt = { .name = "tegra_timer", - .rating = 460, .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, .set_next_event = tegra_timer_set_next_event, .set_state_shutdown = tegra_timer_shutdown, @@ -217,7 +216,8 @@ static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) return TIMER10_IRQ_IDX + cpu; } -static int __init tegra_init_timer(struct device_node *np, bool tegra20) +static int __init tegra_init_timer(struct device_node *np, bool tegra20, + int rating) { struct timer_of *to; int cpu, ret; @@ -280,6 +280,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) cpu_to = per_cpu_ptr(&tegra_to, cpu); cpu_to->of_base.base = timer_reg_base + base; + cpu_to->clkevt.rating = rating; cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { @@ -339,13 +340,34 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) static int __init tegra210_init_timer(struct device_node *np) { - return tegra_init_timer(np, false); + /* + * Arch-timer can't survive across power cycle of CPU core and + * after CPUPORESET signal due to a system design shortcoming, + * hence tegra-timer is more preferable on Tegra210. + */ + return tegra_init_timer(np, false, 460); } TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); static int __init tegra20_init_timer(struct device_node *np) { - return tegra_init_timer(np, true); + int rating; + + /* + * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer, + * that timer runs off the CPU clock and hence is subjected to + * a jitter caused by DVFS clock rate changes. Tegra-timer is + * more preferable for older Tegra's, while later SoC generations + * have arch-timer as a main per-CPU timer and it is not affected + * by DVFS changes. + */ + if (of_machine_is_compatible("nvidia,tegra20") || + of_machine_is_compatible("nvidia,tegra30")) + rating = 460; + else + rating = 330; + + return tegra_init_timer(np, true, rating); } TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); From patchwork Mon Jun 3 18:59:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1109452 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sMrvAxcY"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Hkxw2pV1z9s3l for ; Tue, 4 Jun 2019 05:04:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726911AbfFCTE2 (ORCPT ); Mon, 3 Jun 2019 15:04:28 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:35871 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726842AbfFCTE2 (ORCPT ); Mon, 3 Jun 2019 15:04:28 -0400 Received: by mail-lf1-f68.google.com with SMTP id q26so14466181lfc.3; Mon, 03 Jun 2019 12:04:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UtwYPIjZ42A6onEXbTjq/QuGswOItAJSTPwR+apDGiY=; b=sMrvAxcYfXNUviEHEnCtvKgFVE836xKMCpUXm73t5lOkP5xUvKxgb5/vk75z0Sjajo 5krxgUniGjRrd/KPOmOD8i+pXAoaMGMd+63f99E4Ebe1QpxRQ7TT91KZATx2+aT2kAzL ke0VDy4NjLHdCQ3m5iBEgswbHThd8+p2Lqk8FDX98kJCeBN7OHpBy2bm40vzWY4jRDgY EPtlZw7svD1ZzInc22n5kGwVpG+Jdmu0v9k9+8EeUwUNRmem8oSzlSF4rsKGqQudCoKA jwWyT4ZorP4SuWRCUaTCA4WVXP9iVmLTS0hMj6c2RLt8feNYuRcZGiid/Fvj32G5E9ZD q8Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UtwYPIjZ42A6onEXbTjq/QuGswOItAJSTPwR+apDGiY=; b=FV9ZIMl/+uO7AHvm48oQ50XZeD2QRzefiYtTorCsW81pqJwqS0MfllYSEhhWesJUk+ Y/Un/TRvYDA+60mBA28suk9tMSHwRDqu2P+Z05OyXf3AAvr2KXMA8X0V7pp3lx4ihatJ tn2255Z9NGD00JBeUsoyvsbOZaH7Hub7JqTvbbSssxVhilH7su/1+sPdAJWZp5s5Pznk xOdJodcXT4W/AKvsU38XXGqM6j8GJeX1exWT7EShMFE/LBjnEg+UabA0QD9nrdgk9qYB WphCWK6ijxHlqdv0mi/oI5BCM83GkCVvbvfeSN9583BlRdpVB5NbWFZkU2NJWEd2alJs qytg== X-Gm-Message-State: APjAAAWzIDKHisLB6gNsVz1teSEE4UXh+x5dhtA3W/71QQw51ZVUS6mS DR1zPIe9ONHGnl0LpT0oDOQeUxo5 X-Google-Smtp-Source: APXvYqzqzLCtVGr7EitdsLEfbcc9TA3vFm+FQ8dUIaK97cWDR55QlhwCkEm47jV09PlMx00U/VkVHg== X-Received: by 2002:ac2:5922:: with SMTP id v2mr14401591lfi.180.1559588665943; Mon, 03 Jun 2019 12:04:25 -0700 (PDT) Received: from localhost.localdomain ([94.29.35.141]) by smtp.gmail.com with ESMTPSA id l22sm2768805ljb.39.2019.06.03.12.04.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jun 2019 12:04:25 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/10] clocksource/drivers/tegra: Rename timer-tegra20.c to timer-tegra.c Date: Mon, 3 Jun 2019 21:59:48 +0300 Message-Id: <20190603185948.30438-11-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603185948.30438-1-digetx@gmail.com> References: <20190603185948.30438-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Rename driver's source file to better reflect that it's not specific to older SoC generations. Suggested-by: Daniel Lezcano Signed-off-by: Dmitry Osipenko --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{timer-tegra20.c => timer-tegra.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{timer-tegra20.c => timer-tegra.c} (100%) diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 236858fa7fbf..4145b21eaed3 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -36,7 +36,7 @@ obj-$(CONFIG_U300_TIMER) += timer-u300.o obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += timer-meson6.o -obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o +obj-$(CONFIG_TEGRA_TIMER) += timer-tegra.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra.c similarity index 100% rename from drivers/clocksource/timer-tegra20.c rename to drivers/clocksource/timer-tegra.c