From patchwork Tue Oct 31 04:22:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 832223 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQys962ydz9t2c for ; Tue, 31 Oct 2017 15:23:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751175AbdJaEXk (ORCPT ); Tue, 31 Oct 2017 00:23:40 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13269 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750733AbdJaEXj (ORCPT ); Tue, 31 Oct 2017 00:23:39 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 30 Oct 2017 21:23:17 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 21:23:19 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 21:23:19 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Tue, 31 Oct 2017 04:22:58 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Tue, 31 Oct 2017 04:22:58 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.36.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 21:22:57 -0700 From: Vidya Sagar To: , , , , , CC: , , , , Subject: [PATCH V2 1/4] PCI/ASPM: Add API to supply LTR L1.2 threshold Date: Tue, 31 Oct 2017 09:52:46 +0530 Message-ID: <1509423769-10522-2-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> References: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org adds API for host controller drivers to specify LTR L1.2 threshold value if it is different from the default value. weak implementation of the API is added to supply default value Signed-off-by: Vidya Sagar --- V2: * removed dummy implementation of pcie_aspm_init_link_state() API drivers/pci/pcie/aspm.c | 11 ++++++++--- include/linux/pci-aspm.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 1dfa10cc566b..c6e8604796e5 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -436,6 +436,11 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) return NULL; } +u32 __weak pcie_aspm_get_ltr_l_1_2_threshold(void) +{ + return LTR_L1_2_THRESHOLD_BITS; +} + /* Calculate L1.2 PM substate timing parameters */ static void aspm_calc_l1ss_info(struct pcie_link_state *link, struct aspm_register_info *upreg, @@ -458,10 +463,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, else link->l1ss.ctl1 |= val2 << 8; /* - * We currently use LTR L1.2 threshold to be fixed constant picked from - * Intel's coreboot. + * Get LTR L1.2 threshold value specific to a platform if present + * Otherwise, get a constant value picked from Intel's coreboot. */ - link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS; + link->l1ss.ctl1 |= pcie_aspm_get_ltr_l_1_2_threshold(); /* Choose the greater of the two T_pwr_on */ val1 = (upreg->l1ss_cap >> 19) & 0x1F; diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h index 207c561fb40e..3a083f4ffe71 100644 --- a/include/linux/pci-aspm.h +++ b/include/linux/pci-aspm.h @@ -30,6 +30,7 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev); void pci_disable_link_state(struct pci_dev *pdev, int state); void pci_disable_link_state_locked(struct pci_dev *pdev, int state); void pcie_no_aspm(void); +u32 pcie_aspm_get_ltr_l_1_2_threshold(void); #else static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { From patchwork Tue Oct 31 04:22:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 832225 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQysD2Tbpz9sRg for ; Tue, 31 Oct 2017 15:23:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752028AbdJaEXn (ORCPT ); Tue, 31 Oct 2017 00:23:43 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5875 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751499AbdJaEXm (ORCPT ); Tue, 31 Oct 2017 00:23:42 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 30 Oct 2017 21:23:03 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 21:23:42 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 21:23:42 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Tue, 31 Oct 2017 04:23:02 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Tue, 31 Oct 2017 04:23:01 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Tue, 31 Oct 2017 04:23:01 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.36.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 21:23:01 -0700 From: Vidya Sagar To: , , , , , CC: , , , , Subject: [PATCH V2 2/4] PCI: tegra: Enable ASPM-L1 capability advertisement Date: Tue, 31 Oct 2017 09:52:47 +0530 Message-ID: <1509423769-10522-3-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> References: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enables advertisement of ASPM-L1 support in capability registers of applicable Tegra chips Signed-off-by: Vidya Sagar --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index adae03d671ab..e1526cc5d381 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -226,6 +226,9 @@ #define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) #define RP_VEND_XP_UPDATE_FC_THRESHOLD_T210 (0x60 << 18) +#define RP_VEND_XP1 0xf04 +#define RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT BIT(21) + #define RP_VEND_CTL0 0xf44 #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12) @@ -327,6 +330,7 @@ struct tegra_pcie_soc { bool RAW_violation_fixup; bool program_deskew_time; bool updateFC_threshold; + bool has_aspm_l1; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2188,6 +2192,13 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) value = readl(port->base + RP_VEND_CTL1); value |= RP_VEND_CTL1_ERPT; writel(value, port->base + RP_VEND_CTL1); + + if (port->pcie->soc->has_aspm_l1) { + /* Advertise ASPM-L1 state capability*/ + value = readl(port->base + RP_VEND_XP1); + value |= RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT; + writel(value, port->base + RP_VEND_XP1); + } } static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) @@ -2391,6 +2402,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .RAW_violation_fixup = false, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2412,6 +2424,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .RAW_violation_fixup = false, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = true, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2432,6 +2445,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .RAW_violation_fixup = true, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = true, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2460,6 +2474,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .RAW_violation_fixup = false, .program_deskew_time = true, .updateFC_threshold = true, + .has_aspm_l1 = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2481,6 +2496,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .RAW_violation_fixup = false, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = true, }; static const struct of_device_id tegra_pcie_of_match[] = { From patchwork Tue Oct 31 04:22:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 832229 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQytN6qW4z9sRg for ; Tue, 31 Oct 2017 15:24:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751434AbdJaEYn (ORCPT ); Tue, 31 Oct 2017 00:24:43 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5992 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751192AbdJaEYn (ORCPT ); Tue, 31 Oct 2017 00:24:43 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 30 Oct 2017 21:24:12 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 21:24:51 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 21:24:51 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Tue, 31 Oct 2017 04:23:05 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Tue, 31 Oct 2017 04:23:05 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.36.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 21:23:05 -0700 From: Vidya Sagar To: , , , , , CC: , , , , Subject: [PATCH V2 3/4] PCI: tegra: Apply sw fixups to support ASPM-L1 Sub-States Date: Tue, 31 Oct 2017 09:52:48 +0530 Message-ID: <1509423769-10522-4-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> References: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Programs T_cmrt (Commmon Mode Restore Time) and T_pwr_on (Power On) values to get them reflected in ASPM-L1 Sub-States capability registers Also adjusts internal counter values according to 19.2 MHz clk_m value Signed-off-by: Vidya Sagar --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 65 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index e1526cc5d381..08da67a82a2d 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -191,6 +192,27 @@ #define RP_PRIV_XP_DL 0x494 #define RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD (0x1ff << 1) +#define RP_L1_PM_SUBSTATES_CTL 0xC00 +#define RP_L1_PM_SUBSTATES_CTL_CM_RTIME_MASK (0xFF << 8) +#define RP_L1_PM_SUBSTATES_CTL_CM_RTIME_SHIFT 8 +#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_MASK (0x3 << 16) +#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_SHIFT 16 +#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_MASK (0x1F << 19) +#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT 19 +#define RP_L1_PM_SUBSTATES_CTL_HIDE_CAP (0x1 << 24) + +#define RP_L1_PM_SUBSTATES_1_CTL 0xC04 +#define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK 0x1FFF +#define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY 0x26 + +#define RP_L1_PM_SUBSTATES_2_CTL 0xC08 +#define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK 0x1FFF +#define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY 0x4D +#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_MASK (0xFF << 13) +#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND (0x13 << 13) +#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP_MASK (0xF << 21) +#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP (0x2 << 21) + #define RP_RX_HDR_LIMIT 0xe00 #define RP_RX_HDR_LIMIT_PW_MASK (0xff << 8) #define RP_RX_HDR_LIMIT_PW (0x0e << 8) @@ -331,6 +353,7 @@ struct tegra_pcie_soc { bool program_deskew_time; bool updateFC_threshold; bool has_aspm_l1; + bool has_aspm_l1ss; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -423,6 +446,12 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) return readl(pcie->pads + offset); } +u32 pcie_aspm_get_ltr_l_1_2_threshold(void) +{ + /* LTR L1.2 Threshold = 55us for all ports */ + return ((0x37 << 16) | (0x02 << 29)); +} + /* * The configuration space mapping on Tegra is somewhat similar to the ECAM * defined by PCIe. However it deviates a bit in how the 4 bits for extended @@ -2262,6 +2291,37 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_T210; writel(value, port->base + RP_VEND_XP); } + + if (soc->has_aspm_l1ss) { + /* Set Common Mode Restore Time to 30us */ + value = readl(port->base + RP_L1_PM_SUBSTATES_CTL); + value &= ~RP_L1_PM_SUBSTATES_CTL_CM_RTIME_MASK; + value |= (0x1E << RP_L1_PM_SUBSTATES_CTL_CM_RTIME_SHIFT); + writel(value, port->base + RP_L1_PM_SUBSTATES_CTL); + + /* set T_Power_On to 70us */ + value = readl(port->base + RP_L1_PM_SUBSTATES_CTL); + value &= ~(RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_MASK | + RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_MASK); + value |= (1 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_SHIFT) | + (7 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT); + writel(value, port->base + RP_L1_PM_SUBSTATES_CTL); + + /* Following is based on clk_m being 19.2 MHz */ + value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL); + value &= ~RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK; + value |= RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY; + writel(value, port->base + RP_L1_PM_SUBSTATES_1_CTL); + + value = readl(port->base + RP_L1_PM_SUBSTATES_2_CTL); + value &= ~RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK; + value |= RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY; + value &= ~RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_MASK; + value |= RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND; + value &= ~RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP_MASK; + value |= RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP; + writel(value, port->base + RP_L1_PM_SUBSTATES_2_CTL); + } } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2403,6 +2463,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .program_deskew_time = false, .updateFC_threshold = false, .has_aspm_l1 = false, + .has_aspm_l1ss = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2425,6 +2486,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .program_deskew_time = false, .updateFC_threshold = false, .has_aspm_l1 = true, + .has_aspm_l1ss = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2446,6 +2508,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .program_deskew_time = false, .updateFC_threshold = false, .has_aspm_l1 = true, + .has_aspm_l1ss = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2475,6 +2538,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .program_deskew_time = true, .updateFC_threshold = true, .has_aspm_l1 = true, + .has_aspm_l1ss = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2497,6 +2561,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .program_deskew_time = false, .updateFC_threshold = false, .has_aspm_l1 = true, + .has_aspm_l1ss = true, }; static const struct of_device_id tegra_pcie_of_match[] = { From patchwork Tue Oct 31 04:22:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 832227 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQysG5vSsz9sRg for ; Tue, 31 Oct 2017 15:23:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752683AbdJaEXp (ORCPT ); Tue, 31 Oct 2017 00:23:45 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15616 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751499AbdJaEXp (ORCPT ); Tue, 31 Oct 2017 00:23:45 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 30 Oct 2017 21:23:05 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 21:23:24 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 21:23:24 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Tue, 31 Oct 2017 04:23:09 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Tue, 31 Oct 2017 04:23:09 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.36.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 21:23:09 -0700 From: Vidya Sagar To: , , , , , CC: , , , , Subject: [PATCH V2 4/4] PCI: tegra: fixups to avoid unnecessary wakeup from ASPM-L1.2 Date: Tue, 31 Oct 2017 09:52:49 +0530 Message-ID: <1509423769-10522-5-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> References: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org sets CLKREQ asserted delay to a higher value to avoid unnecessary wake up from L1.2_ENTRY state for Tegra210 Signed-off-by: Vidya Sagar --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 08da67a82a2d..811209dedde2 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -204,6 +204,8 @@ #define RP_L1_PM_SUBSTATES_1_CTL 0xC04 #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK 0x1FFF #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY 0x26 +#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK (0x1FF << 13) +#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY (0x27 << 13) #define RP_L1_PM_SUBSTATES_2_CTL 0xC08 #define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK 0x1FFF @@ -354,6 +356,7 @@ struct tegra_pcie_soc { bool updateFC_threshold; bool has_aspm_l1; bool has_aspm_l1ss; + bool l1ss_rp_wake_fixup; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2307,6 +2310,16 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) (7 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT); writel(value, port->base + RP_L1_PM_SUBSTATES_CTL); + if (soc->l1ss_rp_wake_fixup) { + /* Set CLKREQ asserted delay greater than Power_Off + * time (2us) to avoid RP wakeup in L1.2_ENTRY + */ + value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL); + value &= ~RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK; + value |= RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY; + writel(value, port->base + RP_L1_PM_SUBSTATES_1_CTL); + } + /* Following is based on clk_m being 19.2 MHz */ value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL); value &= ~RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK; @@ -2464,6 +2477,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .updateFC_threshold = false, .has_aspm_l1 = false, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2487,6 +2501,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .updateFC_threshold = false, .has_aspm_l1 = true, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2509,6 +2524,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .updateFC_threshold = false, .has_aspm_l1 = true, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2539,6 +2555,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .updateFC_threshold = true, .has_aspm_l1 = true, .has_aspm_l1ss = true, + .l1ss_rp_wake_fixup = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2562,6 +2579,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .updateFC_threshold = false, .has_aspm_l1 = true, .has_aspm_l1ss = true, + .l1ss_rp_wake_fixup = false, }; static const struct of_device_id tegra_pcie_of_match[] = {