From patchwork Mon Oct 30 20:49:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 832157 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="OE8dDwM3"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="K2hjpoQp"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQmnt2lfbz9t64 for ; Tue, 31 Oct 2017 07:50:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932435AbdJ3UuJ (ORCPT ); Mon, 30 Oct 2017 16:50:09 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:43990 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932153AbdJ3UuI (ORCPT ); Mon, 30 Oct 2017 16:50:08 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 052FB607C7; Mon, 30 Oct 2017 20:50:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509396608; bh=tccmR0NiooqLnGQrvu0DrzMxsOfjVTNy0f/jZ/hu2EE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OE8dDwM3ydCOs7yVwhuwSSn/gwvyf6F+WhQ75+Bw2qXzVksGB7koOqgwfZ10eQiLg HilRsEYx2X8PJfj0jlT7+BD6vS4NdC3ldlUHs3jf7WLgWH/JSoO4SgrF9wsW8Vx18r ra4mTDttXUJk09GgRxkxSPUa9KOto+1fZWBlsMw4= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from timur-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: timur@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 99992607B5; Mon, 30 Oct 2017 20:50:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509396607; bh=tccmR0NiooqLnGQrvu0DrzMxsOfjVTNy0f/jZ/hu2EE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K2hjpoQpT9rZpGuuLTeyo7h2xDTmHQeFuaiNSrGiveUCnuotNxkaDpHYE1qyYeog4 mLct2zowN6/0JZGxko3xcevQ1l92T5UBZg6ywn6G3uzReJnz4neY2bCWb8hAJR69Ck U+4NqdqXbhAxgYGC1s/BxSPCFA5q05bU43EupIgU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 99992607B5 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij , Andy Shevchenko , Mika Westerberg , thierry.reding@gmail.com, Stephen Boyd , david.brown@linaro.org, andy.gross@linaro.org, Bjorn Andersson Cc: timur@codeaurora.org Subject: [PATCH 1/4] Revert "gpio: set up initial state from .get_direction()" Date: Mon, 30 Oct 2017 15:49:59 -0500 Message-Id: <1509396602-1936-2-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509396602-1936-1-git-send-email-timur@codeaurora.org> References: <1509396602-1936-1-git-send-email-timur@codeaurora.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This reverts commit 72d3200061776264941be1b5a9bb8e926b3b30a5. We cannot blindly query the direction of all GPIOs when the pins are first registered. The get_direction callback normally triggers a read/write to hardware, but we shouldn't be touching the hardware for an individual GPIO until after it's been properly requested. --- drivers/gpio/gpiolib.c | 31 +++++++------------------------ 1 file changed, 7 insertions(+), 24 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index eb80dac4e26a..60553af4c004 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1221,31 +1221,14 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data) struct gpio_desc *desc = &gdev->descs[i]; desc->gdev = gdev; - /* - * REVISIT: most hardware initializes GPIOs as inputs - * (often with pullups enabled) so power usage is - * minimized. Linux code should set the gpio direction - * first thing; but until it does, and in case - * chip->get_direction is not set, we may expose the - * wrong direction in sysfs. - */ - - if (chip->get_direction) { - /* - * If we have .get_direction, set up the initial - * direction flag from the hardware. - */ - int dir = chip->get_direction(chip, i); - if (!dir) - set_bit(FLAG_IS_OUT, &desc->flags); - } else if (!chip->direction_input) { - /* - * If the chip lacks the .direction_input callback - * we logically assume all lines are outputs. - */ - set_bit(FLAG_IS_OUT, &desc->flags); - } + /* REVISIT: most hardware initializes GPIOs as inputs (often + * with pullups enabled) so power usage is minimized. Linux + * code should set the gpio direction first thing; but until + * it does, and in case chip->get_direction is not set, we may + * expose the wrong direction in sysfs. + */ + desc->flags = !chip->direction_input ? (1 << FLAG_IS_OUT) : 0; } #ifdef CONFIG_PINCTRL From patchwork Mon Oct 30 20:50:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 832158 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="mxYiNLK/"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="EkJM8w1v"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQmnx0JlPz9t61 for ; Tue, 31 Oct 2017 07:50:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932503AbdJ3UuL (ORCPT ); Mon, 30 Oct 2017 16:50:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:44138 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932153AbdJ3UuK (ORCPT ); Mon, 30 Oct 2017 16:50:10 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B7570607E8; Mon, 30 Oct 2017 20:50:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509396609; bh=cDJ4gr2slX3EDntjeQ5sg8KEusyb+DRQh2D5l9SyDVo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mxYiNLK/MQZ1FloG9CUsHnVixGklGQ2klCFX0qi994gxCas05c3lKXLgEOtu9WTUo UiMS7+j6hCRTBJGdgpnZNMDXpL4NmDtZVynWn/dS1H6OKYQ5rT5DKC1dvkLBGWUmWf ZZL8heAsGv+ZtBH/q3Zv4zAM26b6PZFX7r2Sfupw= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from timur-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: timur@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D3CC7607C1; Mon, 30 Oct 2017 20:50:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509396608; bh=cDJ4gr2slX3EDntjeQ5sg8KEusyb+DRQh2D5l9SyDVo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EkJM8w1vOdodvvWuc3eNN2YsXk7g3LkdreJnh74Co5ucv743E9yeEOIAbJhOyIfhm Yxb5BnQnDrSEPLqUrtpUJd2C+ZdD8zk1ijyaNoBUjtpWTabAX6nIxJ/Znk3POUlvGQ 32ig59DUR0EiFmcEGp0PhJXg8zw4PshndL3lGcjM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D3CC7607C1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij , Andy Shevchenko , Mika Westerberg , thierry.reding@gmail.com, Stephen Boyd , david.brown@linaro.org, andy.gross@linaro.org, Bjorn Andersson Cc: timur@codeaurora.org Subject: [PATCH 2/4] gpiolib: add bitmask for valid GPIO lines Date: Mon, 30 Oct 2017 15:50:00 -0500 Message-Id: <1509396602-1936-3-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509396602-1936-1-git-send-email-timur@codeaurora.org> References: <1509396602-1936-1-git-send-email-timur@codeaurora.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add support for specifying that some GPIOs within a range are unavailable. Some systems have a sparse list of GPIOs, where a range of GPIOs is specified (usually 0 to n-1), but some subset within that range is absent or unavailable for whatever reason. To support this, allow drivers to specify a bitmask of GPIOs that are present or absent. Gpiolib will then block access to those that are absent. Signed-off-by: Timur Tabi --- drivers/gpio/gpiolib.c | 43 +++++++++++++++++++++++++++++++++++-------- include/linux/gpio/driver.h | 2 ++ 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 60553af4c004..c32387936cdd 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1481,22 +1481,36 @@ static struct gpio_chip *find_chip_by_name(const char *name) static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip) { - if (!gpiochip->irq_need_valid_mask) - return 0; + if (gpiochip->irq_need_valid_mask) { + gpiochip->irq_valid_mask = + kcalloc(BITS_TO_LONGS(gpiochip->ngpio), + sizeof(long), GFP_KERNEL); + if (!gpiochip->irq_valid_mask) + return -ENOMEM; - gpiochip->irq_valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio), - sizeof(long), GFP_KERNEL); - if (!gpiochip->irq_valid_mask) - return -ENOMEM; + /* Assume by default all GPIOs are valid */ + bitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio); + } - /* Assume by default all GPIOs are valid */ - bitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio); + if (gpiochip->line_need_valid_mask) { + gpiochip->line_valid_mask = + kcalloc(BITS_TO_LONGS(gpiochip->ngpio), + sizeof(long), GFP_KERNEL); + if (!gpiochip->line_valid_mask) + return -ENOMEM; + + /* Assume by default all GPIOs are valid */ + bitmap_fill(gpiochip->line_valid_mask, gpiochip->ngpio); + } return 0; } static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip) { + kfree(gpiochip->line_valid_mask); + gpiochip->line_valid_mask = NULL; + kfree(gpiochip->irq_valid_mask); gpiochip->irq_valid_mask = NULL; } @@ -1510,6 +1524,15 @@ static bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip, return test_bit(offset, gpiochip->irq_valid_mask); } +static bool gpiochip_irqchip_line_valid(const struct gpio_chip *gpiochip, + unsigned int offset) +{ + /* No mask means all valid */ + if (likely(!gpiochip->line_valid_mask)) + return true; + return test_bit(offset, gpiochip->line_valid_mask); +} + /** * gpiochip_set_cascaded_irqchip() - connects a cascaded irqchip to a gpiochip * @gpiochip: the gpiochip to set the irqchip chain to @@ -3320,6 +3343,10 @@ struct gpio_desc *__must_check gpiod_get_index(struct device *dev, return desc; } + /* Make sure the GPIO is valid before we request it. */ + if (!gpiochip_irqchip_line_valid(desc->gdev->chip, idx)) + return ERR_PTR(-EACCES); + status = gpiod_request(desc, con_id); if (status < 0) return ERR_PTR(status); diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index c97f8325e8bf..83df2934bdf7 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -172,6 +172,8 @@ struct gpio_chip { bool irq_nested; bool irq_need_valid_mask; unsigned long *irq_valid_mask; + bool line_need_valid_mask; + unsigned long *line_valid_mask; struct lock_class_key *lock_key; #endif From patchwork Mon Oct 30 20:50:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 832159 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="fxhxTXI/"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="fxhxTXI/"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQmny3vM4z9t61 for ; Tue, 31 Oct 2017 07:50:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932513AbdJ3UuN (ORCPT ); Mon, 30 Oct 2017 16:50:13 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:44258 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932474AbdJ3UuL (ORCPT ); Mon, 30 Oct 2017 16:50:11 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D118960725; Mon, 30 Oct 2017 20:50:10 +0000 (UTC) DKIM-Signature: v=1; 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s=default; t=1509396610; bh=OMhavYFOfDjShXbohMHkksyJMXkTEFM3fERxvsKSSaE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fxhxTXI/G2VQZXEjH6A5dcmyddcWNOZMWAWeCfqY+H/NnoEUXlPAQ0c+E6GotaVor sU+/NQkWi/OPSrV5vA3sQ9afd9+UMyxANrLDxIzPgRFdDPjOp95UeSHaViqDKcMQNv eVOKOqjUSFlvFDU3U7n5AiT+3YPjnukCBGMcpFc8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 17434607DE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij , Andy Shevchenko , Mika Westerberg , thierry.reding@gmail.com, Stephen Boyd , david.brown@linaro.org, andy.gross@linaro.org, Bjorn Andersson Cc: timur@codeaurora.org Subject: [PATCH 3/4] [v6] pinctrl: qcom: disable GPIO groups with no pins Date: Mon, 30 Oct 2017 15:50:01 -0500 Message-Id: <1509396602-1936-4-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509396602-1936-1-git-send-email-timur@codeaurora.org> References: <1509396602-1936-1-git-send-email-timur@codeaurora.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org pinctrl-msm only accepts an array of GPIOs from 0 to n-1, and it expects each group to support have only one pin (npins == 1). We can support "sparse" GPIO maps if we allow for some groups to have zero pins (npins == 0). These pins are "hidden" from the rest of the driver and gpiolib. A new boolean 'sparse' indicates whether the GPIO map is sparse. If any GPIO has an 'npins' value of 0, then 'sparse' must be set to True. Most access to unavailable GPIOs can be blocked via the gpio_chip.request function. The one exception is when gpiochip_add_data() scans all of the GPIOs without "requesting" them. To cover this case, msm_gpio_get_direction() separately checks if the GPIO is available. Signed-off-by: Timur Tabi --- drivers/pinctrl/qcom/pinctrl-msm.c | 48 +++++++++++++++++++++++++++++++++----- drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++ 2 files changed, 44 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index ff491da64dab..66c68a314ca9 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -507,6 +507,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, }; g = &pctrl->soc->groups[offset]; + + /* If the GPIO group has no pins, then don't show it. */ + if (!g->npins) + return; + ctl_reg = readl(pctrl->regs + g->ctl_reg); is_out = !!(ctl_reg & BIT(g->oe_bit)); @@ -516,7 +521,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); seq_printf(s, " %dmA", msm_regval_to_drive(drive)); - seq_printf(s, " %s", pulls[pull]); + seq_printf(s, " %s\n", pulls[pull]); } static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) @@ -524,23 +529,36 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) unsigned gpio = chip->base; unsigned i; - for (i = 0; i < chip->ngpio; i++, gpio++) { + for (i = 0; i < chip->ngpio; i++, gpio++) msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); - seq_puts(s, "\n"); - } } #else #define msm_gpio_dbg_show NULL #endif +/* + * If the requested GPIO has no pins, then treat it as unavailable. + * Otherwise, call the standard request function. + */ +static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + const struct msm_pingroup *g = &pctrl->soc->groups[offset]; + + if (!g->npins) + return -ENODEV; + + return gpiochip_generic_request(chip, offset); +} + static const struct gpio_chip msm_gpio_template = { .direction_input = msm_gpio_direction_input, .direction_output = msm_gpio_direction_output, .get_direction = msm_gpio_get_direction, .get = msm_gpio_get, .set = msm_gpio_set, - .request = gpiochip_generic_request, + .request = msm_gpio_request, .free = gpiochip_generic_free, .dbg_show = msm_gpio_dbg_show, }; @@ -813,6 +831,8 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) struct gpio_chip *chip; int ret; unsigned ngpio = pctrl->soc->ngpios; + const struct msm_pingroup *groups = pctrl->soc->groups; + unsigned int i; if (WARN_ON(ngpio > MAX_NR_GPIO)) return -EINVAL; @@ -825,13 +845,29 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) chip->owner = THIS_MODULE; chip->of_node = pctrl->dev->of_node; + /* If the GPIO map is sparse, then we need to disable specific IRQs */ + if (pctrl->soc->sparse) { + chip->irq_need_valid_mask = true; + chip->line_need_valid_mask = true; + } + ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { dev_err(pctrl->dev, "Failed register gpiochip\n"); return ret; } - ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); + if (chip->line_need_valid_mask) { + for (i = 0; i < ngpio; i++) + if (!groups[i].npins) { + clear_bit(i, pctrl->chip.irq_valid_mask); + clear_bit(i, pctrl->chip.line_valid_mask); + } + } + + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), + 0, 0, ngpio); + if (ret) { dev_err(pctrl->dev, "Failed to add pin range\n"); gpiochip_remove(&pctrl->chip); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 9b9feea540ff..70762bcb84cb 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -107,6 +107,7 @@ struct msm_pingroup { * @ngroups: The numbmer of entries in @groups. * @ngpio: The number of pingroups the driver should expose as GPIOs. * @pull_no_keeper: The SoC does not support keeper bias. + * @sparse: The GPIO map is sparse (some GPIOs have npins == 0) */ struct msm_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -117,6 +118,7 @@ struct msm_pinctrl_soc_data { unsigned ngroups; unsigned ngpios; bool pull_no_keeper; + bool sparse; }; int msm_pinctrl_probe(struct platform_device *pdev, From patchwork Mon Oct 30 20:50:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 832160 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509396611; bh=h2bUshz/RlnNVyv/v37wwDYXso+VV7sx6/HCMkvOY8M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Nb8Kid4jnBg1YTw0rUndUqaCA8gQqxwq4nlWL9EGVQofd1Pu6omRLLl+vTWC+S1dQ pCI7fADATT88bqe+Z2Y+Ex+A8LD50XG9HWVBgF85yY5Wa4eo2qlSsDfCw77BA/0+yt 18JrlGhXVwNFDEQMfIKu4c2Eg/FmTtbrvuHoWQqs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4FD7D60802 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij , Andy Shevchenko , Mika Westerberg , thierry.reding@gmail.com, Stephen Boyd , david.brown@linaro.org, andy.gross@linaro.org, Bjorn Andersson Cc: timur@codeaurora.org Subject: [PATCH 4/4] [v3] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002 Date: Mon, 30 Oct 2017 15:50:02 -0500 Message-Id: <1509396602-1936-5-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509396602-1936-1-git-send-email-timur@codeaurora.org> References: <1509396602-1936-1-git-send-email-timur@codeaurora.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Newer versions of the firmware for the Qualcomm Datacenter Technologies QDF2400 restricts access to a subset of the GPIOs on the TLMM. To prevent older kernels from accidentally accessing the restricted GPIOs, we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002, and introduce a new property "gpios". This property is an array of specific GPIOs that are accessible. When an older kernel boots on newer (restricted) firmware, it will fail to probe. To implement the sparse GPIO map, we register all of the GPIOs, but set the pin count for the unavailable GPIOs to zero. The pinctrl-msm driver will block those unavailable GPIOs from being accessed. To allow newer kernels to support older firmware, the driver retains support for QCOM8001. Signed-off-by: Timur Tabi --- drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 145 +++++++++++++++++++++++++-------- 1 file changed, 109 insertions(+), 36 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c index bb3ce5c3e18b..37f746f6eb8c 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -38,68 +38,147 @@ /* maximum size of each gpio name (enough room for "gpioXXX" + null) */ #define NAME_SIZE 8 +enum { + QDF2XXX_V1, + QDF2XXX_V2, +}; + +static const struct acpi_device_id qdf2xxx_acpi_ids[] = { + {"QCOM8001", QDF2XXX_V1}, + {"QCOM8002", QDF2XXX_V2}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids); + static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) { + const struct acpi_device_id *id = + acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev); struct pinctrl_pin_desc *pins; struct msm_pingroup *groups; char (*names)[NAME_SIZE]; unsigned int i; u32 num_gpios; + unsigned int avail_gpios; /* The number of GPIOs we support */ + u16 *gpios; /* An array of supported GPIOs */ int ret; /* Query the number of GPIOs from ACPI */ ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios); if (ret < 0) { - dev_warn(&pdev->dev, "missing num-gpios property\n"); + dev_err(&pdev->dev, "missing 'num-gpios' property\n"); return ret; } - if (!num_gpios || num_gpios > MAX_GPIOS) { - dev_warn(&pdev->dev, "invalid num-gpios property\n"); + dev_err(&pdev->dev, "invalid 'num-gpios' property\n"); return -ENODEV; } + /* + * The QCOM8001 HID contains only the number of GPIOs, and assumes + * that all of them are available. avail_gpios is the same as num_gpios. + * + * The QCOM8002 HID introduces the 'gpios' DSD, which lists + * specific GPIOs that the driver is allowed to access. + * + * The make the common code simpler, in both cases we create an + * array of GPIOs that are accessible. So for QCOM8001, that would + * be all of the GPIOs. + */ + if (id->driver_data == QDF2XXX_V1) { + avail_gpios = num_gpios; + + gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]), + GFP_KERNEL); + if (!gpios) + return -ENOMEM; + + for (i = 0; i < avail_gpios; i++) + gpios[i] = i; + } else { + /* The number of GPIOs in the approved list */ + ret = device_property_read_u16_array(&pdev->dev, "gpios", + NULL, 0); + if (ret < 0) { + dev_err(&pdev->dev, "missing 'num-gpios' property\n"); + return ret; + } + if (!ret || ret > MAX_GPIOS) { + dev_err(&pdev->dev, "invalid 'num-gpios' property\n"); + return -ENODEV; + } + avail_gpios = ret; + + gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]), + GFP_KERNEL); + if (!gpios) + return -ENOMEM; + + ret = device_property_read_u16_array(&pdev->dev, "gpios", gpios, + avail_gpios); + if (ret < 0) { + dev_err(&pdev->dev, "could not read list of GPIOs\n"); + return ret; + } + + /* + * Because we have a specific list of GPIOs, the GPIO map + * is 'sparse'. + */ + qdf2xxx_pinctrl.sparse = true; + } + pins = devm_kcalloc(&pdev->dev, num_gpios, sizeof(struct pinctrl_pin_desc), GFP_KERNEL); groups = devm_kcalloc(&pdev->dev, num_gpios, sizeof(struct msm_pingroup), GFP_KERNEL); - names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL); + names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL); if (!pins || !groups || !names) return -ENOMEM; + /* + * Initialize the array. GPIOs not listed in the 'gpios' array + * still need a number, but nothing else. + */ for (i = 0; i < num_gpios; i++) { - snprintf(names[i], NAME_SIZE, "gpio%u", i); - pins[i].number = i; - pins[i].name = names[i]; - - groups[i].npins = 1; - groups[i].name = names[i]; groups[i].pins = &pins[i].number; + } - groups[i].ctl_reg = 0x10000 * i; - groups[i].io_reg = 0x04 + 0x10000 * i; - groups[i].intr_cfg_reg = 0x08 + 0x10000 * i; - groups[i].intr_status_reg = 0x0c + 0x10000 * i; - groups[i].intr_target_reg = 0x08 + 0x10000 * i; - - groups[i].mux_bit = 2; - groups[i].pull_bit = 0; - groups[i].drv_bit = 6; - groups[i].oe_bit = 9; - groups[i].in_bit = 0; - groups[i].out_bit = 1; - groups[i].intr_enable_bit = 0; - groups[i].intr_status_bit = 0; - groups[i].intr_target_bit = 5; - groups[i].intr_target_kpss_val = 1; - groups[i].intr_raw_status_bit = 4; - groups[i].intr_polarity_bit = 1; - groups[i].intr_detection_bit = 2; - groups[i].intr_detection_width = 2; + /* Populate the entries that are meant to be exposes as GPIOs. */ + for (i = 0; i < avail_gpios; i++) { + unsigned int gpio = gpios[i]; + + groups[gpio].npins = 1; + snprintf(names[i], NAME_SIZE, "gpio%u", gpio); + pins[gpio].name = names[i]; + groups[gpio].name = names[i]; + + groups[gpio].ctl_reg = 0x10000 * gpio; + groups[gpio].io_reg = 0x04 + 0x10000 * gpio; + groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio; + groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio; + groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio; + + groups[gpio].mux_bit = 2; + groups[gpio].pull_bit = 0; + groups[gpio].drv_bit = 6; + groups[gpio].oe_bit = 9; + groups[gpio].in_bit = 0; + groups[gpio].out_bit = 1; + groups[gpio].intr_enable_bit = 0; + groups[gpio].intr_status_bit = 0; + groups[gpio].intr_target_bit = 5; + groups[gpio].intr_target_kpss_val = 1; + groups[gpio].intr_raw_status_bit = 4; + groups[gpio].intr_polarity_bit = 1; + groups[gpio].intr_detection_bit = 2; + groups[gpio].intr_detection_width = 2; } + devm_kfree(&pdev->dev, gpios); + qdf2xxx_pinctrl.pins = pins; qdf2xxx_pinctrl.groups = groups; qdf2xxx_pinctrl.npins = num_gpios; @@ -109,12 +188,6 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl); } -static const struct acpi_device_id qdf2xxx_acpi_ids[] = { - {"QCOM8001"}, - {}, -}; -MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids); - static struct platform_driver qdf2xxx_pinctrl_driver = { .driver = { .name = "qdf2xxx-pinctrl",