From patchwork Wed May 22 16:19:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 1103452 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Mf/P/3Fr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 458Hv24xzPz9sCJ for ; Thu, 23 May 2019 02:21:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730080AbfEVQVJ (ORCPT ); Wed, 22 May 2019 12:21:09 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49360 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730063AbfEVQVJ (ORCPT ); Wed, 22 May 2019 12:21:09 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4MGKdev102267; Wed, 22 May 2019 11:20:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1558542039; bh=VCnEYJi1HcEwa5Iq6WKWhniPEkwL4k0FanrWfiqf6K0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Mf/P/3FrkUIXW+4ewz5KuRrQNOyEVulTEvST+4lJY0UrfaqaTtyGv1adilwWDWgK3 e9FmQgBOxYd0v5uH1mX1lfQNxaTHTczQ3NuqPLMlYEK2cFefsYDiSH2V+i6cAbbGxQ nkswLRTNCwaPTYS0Jejs7+ZqqCWn+gmjC/0IYIZE= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4MGKdxC099357 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 22 May 2019 11:20:39 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 22 May 2019 11:20:38 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 22 May 2019 11:20:38 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4MGKcsX122870; Wed, 22 May 2019 11:20:38 -0500 From: Nishanth Menon To: Arnd Bergmann , Olof Johansson , Santosh Shilimkar , Will Deacon , Catalin Marinas , Greg Kroah-Hartman , Mark Rutland , Rob Herring CC: , , , , Tony Lindgren , Russell King , Tero Kristo , Nishanth Menon Subject: [PATCH 1/6] dt-bindings: arm: ti: Add bindings for J721E SoC Date: Wed, 22 May 2019 11:19:16 -0500 Message-ID: <20190522161921.20750-2-nm@ti.com> X-Mailer: git-send-email 2.21.0.777.g83232e38648b In-Reply-To: <20190522161921.20750-1-nm@ti.com> References: <20190522161921.20750-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The J721E SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable lower system costs of automotive applications such as infotainment, cluster, premium Audio, Gateway, industrial and a range of broad market applications. This SoC is designed around reducing the system cost by eliminating the need of an external system MCU and is targeted towards ASIL-B/C certification/requirements in addition to allowing complex software and system use-cases. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP, Two C66x floating point DSPs. * 3D GPU PowerVR Rogue 8XE GE8430 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and up to two DPI interfaces. * Integrated Ethernet switch supporting up to a total of 8 external ports in addition to legacy Ethernet switch of up to 2 ports. * System MMU (SMMU) Version 3.0 and advanced virtualisation capabilities. * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS * Centralized System Controller for Security, Power, and Resource Management (DMSC) See J721E Technical Reference Manual (SPRUIL1, May 2019) for further details: http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Nishanth Menon Reviewed-by: Rob Herring Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt index 6a059cabb2da..333e7256126a 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.txt +++ b/Documentation/devicetree/bindings/arm/ti/k3.txt @@ -13,6 +13,9 @@ architecture it uses, using one of the following compatible values: - AM654 compatible = "ti,am654"; +- J721E + compatible = "ti,j721e"; + Boards ------ From patchwork Wed May 22 16:19:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 1103454 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="V8dAIqL5"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 458HvH56Gyz9sCJ for ; Thu, 23 May 2019 02:21:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730125AbfEVQVT (ORCPT ); Wed, 22 May 2019 12:21:19 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:59370 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730040AbfEVQVI (ORCPT ); Wed, 22 May 2019 12:21:08 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4MGKdI2037691; Wed, 22 May 2019 11:20:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1558542039; bh=NHGPWtIBtgCaIRfzn2pY4Joyz5HN6po2SvcIC4DkkMU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=V8dAIqL5X+4hefMSssRkIut7wYFjJgbloh2SRmA3cR+POQ6fJ+qEzPAfZ+NP6nNEv pxe/i9D7N7Pd1xHiQxMZbeRBvWXsAQhRazuFYrVaonambtOeQTcr+wQKl0dXOtlAeD GW3lwzAjZuQdeAzQqjuoaxECxDRFT/bAeR1uyv1M= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4MGKdLk099362 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 22 May 2019 11:20:39 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 22 May 2019 11:20:38 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 22 May 2019 11:20:38 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4MGKcW6126463; Wed, 22 May 2019 11:20:38 -0500 From: Nishanth Menon To: Arnd Bergmann , Olof Johansson , Santosh Shilimkar , Will Deacon , Catalin Marinas , Greg Kroah-Hartman , Mark Rutland , Rob Herring CC: , , , , Tony Lindgren , Russell King , Tero Kristo , Nishanth Menon , Sekhar Nori , Vignesh R Subject: [PATCH 2/6] dt-bindings: serial: 8250_omap: Add compatible for J721E UART controller Date: Wed, 22 May 2019 11:19:17 -0500 Message-ID: <20190522161921.20750-3-nm@ti.com> X-Mailer: git-send-email 2.21.0.777.g83232e38648b In-Reply-To: <20190522161921.20750-1-nm@ti.com> References: <20190522161921.20750-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org J721e uses a UART controller that is compatible with AM654 UART. Introduce a specific compatible to help handle the differences if necessary. Cc: Sekhar Nori Cc: Vignesh R Signed-off-by: Nishanth Menon Reviewed-by: Rob Herring --- NOTE: - If Greg is ok, we can pick up the uart compatibility via the k3 tree, else, I can spawn it off the series into it's own patch, but it seemed better in a logical order. Documentation/devicetree/bindings/serial/omap_serial.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt index 0a9b5444f4e6..dcba86b0a0d0 100644 --- a/Documentation/devicetree/bindings/serial/omap_serial.txt +++ b/Documentation/devicetree/bindings/serial/omap_serial.txt @@ -1,6 +1,7 @@ OMAP UART controller Required properties: +- compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers - compatible : should be "ti,am654-uart" for AM654 controllers - compatible : should be "ti,omap2-uart" for OMAP2 controllers - compatible : should be "ti,omap3-uart" for OMAP3 controllers