From patchwork Mon Oct 30 13:57:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832053 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbhj0S8kz9t2c for ; Tue, 31 Oct 2017 01:00:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752322AbdJ3OAD (ORCPT ); Mon, 30 Oct 2017 10:00:03 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8386 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752019AbdJ3OAD (ORCPT ); Mon, 30 Oct 2017 10:00:03 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 30 Oct 2017 06:59:51 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 07:00:10 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 07:00:10 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:57:44 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:57:43 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:57:43 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:57:43 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 01/12] PCI: tegra: Start LTSSM after programming root port Date: Mon, 30 Oct 2017 19:27:12 +0530 Message-ID: <1509371843-22931-2-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch ensures that LTSSM is started (by deasserting pcie_xrst) only after all the required root port register programming is completed. Signed-off-by: Manikanta Maddireddy --- V3: * no change in this patch V2: * no change in this patch drivers/pci/host/pci-tegra.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 96e8038c3019..b41c60c7414c 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -1024,9 +1024,6 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) } } - /* take the PCIe interface module out of reset */ - reset_control_deassert(pcie->pcie_xrst); - /* finally enable PCIe */ value = afi_readl(pcie, AFI_CONFIGURATION); value |= AFI_CONFIGURATION_EN_FPCI; @@ -1065,7 +1062,6 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie) dev_err(dev, "failed to power off PHY(s): %d\n", err); } - reset_control_assert(pcie->pcie_xrst); reset_control_assert(pcie->afi_rst); reset_control_assert(pcie->pex_rst); @@ -2116,7 +2112,12 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) port->index, port->lanes); tegra_pcie_port_enable(port); + } + /* take the PCIe interface module out of reset */ + reset_control_deassert(pcie->pcie_xrst); + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { if (tegra_pcie_port_check_link(port)) continue; From patchwork Mon Oct 30 13:57:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832055 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbjL29Zxz9t2r for ; Tue, 31 Oct 2017 01:00:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752557AbdJ3OAf (ORCPT ); Mon, 30 Oct 2017 10:00:35 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8492 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752455AbdJ3OAd (ORCPT ); Mon, 30 Oct 2017 10:00:33 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 30 Oct 2017 07:00:11 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 07:00:30 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 07:00:30 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:57:53 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:57:53 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:57:53 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 02/12] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Date: Mon, 30 Oct 2017 19:27:13 +0530 Message-ID: <1509371843-22931-3-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In Tegra186 PHY programming is done by BPMP-FW, so PHY calls are skipped in driver. REFCLK pad settings are independent of PHY and should be programmed by driver. So move REFCLK pad settings out of phy_power_on(). These pad settings improve REFCLK peak to peak amplitude. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V3: * Corrected commit log V2: * no change in this patch drivers/pci/host/pci-tegra.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index b41c60c7414c..068510b40c1a 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -910,7 +910,6 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port) static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; - const struct tegra_pcie_soc *soc = pcie->soc; struct tegra_pcie_port *port; int err; @@ -936,12 +935,6 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) } } - /* Configure the reference clock driver */ - pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); - - if (soc->num_ports > 2) - pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); - return 0; } @@ -2049,6 +2042,17 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie) return 0; } +static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie) +{ + const struct tegra_pcie_soc *soc = pcie->soc; + + /* Configure the reference clock driver */ + pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); + + if (soc->num_ports > 2) + pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); +} + /* * FIXME: If there are no PCIe cards attached, then calling this function * can result in the increase of the bootup time as there are big timeout @@ -2107,6 +2111,8 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) struct device *dev = pcie->dev; struct tegra_pcie_port *port, *tmp; + tegra_pcie_apply_pad_settings(pcie); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { dev_info(dev, "probing port %u, using %u lanes\n", port->index, port->lanes); From patchwork Mon Oct 30 13:57:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832037 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbfm2W3Nz9t2r for ; Tue, 31 Oct 2017 00:58:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751895AbdJ3N6W (ORCPT ); Mon, 30 Oct 2017 09:58:22 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8266 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751572AbdJ3N6W (ORCPT ); Mon, 30 Oct 2017 09:58:22 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 30 Oct 2017 06:58:01 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 06:58:02 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 06:58:02 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:02 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:02 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:01 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:01 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 03/12] PCI: tegra: Retrain link for Gen2 speed Date: Mon, 30 Oct 2017 19:27:14 +0530 Message-ID: <1509371843-22931-4-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra124, 132, 210 and 186 support Gen2 link speed. After the link is up in Gen1, set target link speed as Gen2 and retrain link. Link switches to Gen2 speed if Gen2 capable end point is connected, else link stays in Gen1. Signed-off-by: Manikanta Maddireddy --- V3: * Corrected commit log * Replaced jiffies with ktime V2: * no change in this patch drivers/pci/host/pci-tegra.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 068510b40c1a..ed5e8acfdc32 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -232,6 +232,8 @@ #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ +#define LINK_RETRAIN_TIMEOUT 100000 + struct tegra_msi { struct msi_controller chip; DECLARE_BITMAP(used, INT_PCI_MSI_NR); @@ -2134,6 +2136,42 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) } } +static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie, + struct pci_dev *pci_dev) +{ + struct device *dev = pcie->dev; + ktime_t deadline; + unsigned short val; + + /* Skip if the current device is not a root port */ + if (pci_pcie_type(pci_dev) != PCI_EXP_TYPE_ROOT_PORT) + return; + + pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL2, &val); + val &= ~PCI_EXP_LNKSTA_CLS; + val |= PCI_EXP_LNKSTA_CLS_5_0GB; + pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL2, val); + + /* Retrain the link */ + pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &val); + val |= PCI_EXP_LNKCTL_RL; + pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL, val); + + deadline = ktime_add_us(ktime_get(), LINK_RETRAIN_TIMEOUT); + for (;;) { + pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &val); + if (!(val & PCI_EXP_LNKSTA_LT)) + break; + if (ktime_after(ktime_get(), deadline)) + break; + usleep_range(2000, 3000); + } + + if (val & PCI_EXP_LNKSTA_LT) + dev_err(dev, "link retrain of PCIe slot %u failed\n", + PCI_SLOT(pci_dev->devfn)); +} + static const struct tegra_pcie_soc tegra20_pcie = { .num_ports = 2, .msi_base_shift = 0, @@ -2335,6 +2373,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) struct pci_host_bridge *host; struct tegra_pcie *pcie; struct pci_bus *child; + struct pci_dev *pci_dev = NULL; int err; host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); @@ -2400,6 +2439,9 @@ static int tegra_pcie_probe(struct platform_device *pdev) pci_bus_add_devices(host->bus); + for_each_pci_dev(pci_dev) + tegra_pcie_change_link_speed(pcie, pci_dev); + if (IS_ENABLED(CONFIG_DEBUG_FS)) { err = tegra_pcie_debugfs_init(pcie); if (err < 0) From patchwork Mon Oct 30 13:57:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832041 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbgM5vVXz9t2c for ; Tue, 31 Oct 2017 00:58:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752171AbdJ3N6y (ORCPT ); Mon, 30 Oct 2017 09:58:54 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17801 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751572AbdJ3N6y (ORCPT ); Mon, 30 Oct 2017 09:58:54 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 30 Oct 2017 06:58:15 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 06:58:50 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 06:58:50 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:08 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:08 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:07 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 04/12] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Date: Mon, 30 Oct 2017 19:27:15 +0530 Message-ID: <1509371843-22931-5-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Default root port settings hide AER capability. This patch enables the advertisement of AER capability by root port. Signed-off-by: Manikanta Maddireddy --- V3: * updated commit log V2: * no change in this patch drivers/pci/host/pci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index ed5e8acfdc32..46896aaab81d 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -187,6 +187,9 @@ #define RP_VEND_XP 0x00000f00 #define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_CTL1 0xf48 +#define RP_VEND_CTL1_ERPT (1 << 13) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -2055,6 +2058,16 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie) pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); } +static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) +{ + unsigned long value; + + /* Enable AER capability */ + value = readl(port->base + RP_VEND_CTL1); + value |= RP_VEND_CTL1_ERPT; + writel(value, port->base + RP_VEND_CTL1); +} + /* * FIXME: If there are no PCIe cards attached, then calling this function * can result in the increase of the bootup time as there are big timeout @@ -2120,6 +2133,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) port->index, port->lanes); tegra_pcie_port_enable(port); + tegra_pcie_enable_rp_features(port); } /* take the PCIe interface module out of reset */ From patchwork Mon Oct 30 13:57:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832049 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbhL4prTz9t2c for ; Tue, 31 Oct 2017 00:59:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752250AbdJ3N7p (ORCPT ); Mon, 30 Oct 2017 09:59:45 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17867 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751733AbdJ3N7o (ORCPT ); Mon, 30 Oct 2017 09:59:44 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 30 Oct 2017 06:59:05 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 06:59:41 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 06:59:41 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:13 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:13 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:13 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 05/12] PCI: tegra: Program UPHY electrical settings in Tegra210 Date: Mon, 30 Oct 2017 19:27:16 +0530 Message-ID: <1509371843-22931-6-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org UPHY electrical programming guidelines are documented in Tegra210 TRM. Program these electrical settings for proper eye diagram in all link speeds. Signed-off-by: Manikanta Maddireddy --- V3: * Added shift operation for readability V2: * no change in this patch drivers/pci/host/pci-tegra.c | 97 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 46896aaab81d..c862facfd6e9 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -184,6 +184,32 @@ #define AFI_PEXBIAS_CTRL_0 0x168 +#define RP_ECTL_2_R1 0xe84 +#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff + +#define RP_ECTL_4_R1 0xe8c +#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK (0xffff << 16) +#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT 16 + +#define RP_ECTL_5_R1 0xe90 +#define RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK 0xffffffff + +#define RP_ECTL_6_R1 0xe94 +#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK 0xffffffff + +#define RP_ECTL_2_R2 0xea4 +#define RP_ECTL_2_R2_RX_CTLE_1C_MASK 0xffff + +#define RP_ECTL_4_R2 0xeac +#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK (0xffff << 16) +#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT 16 + +#define RP_ECTL_5_R2 0xeb0 +#define RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK 0xffffffff + +#define RP_ECTL_6_R2 0xeb4 +#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff + #define RP_VEND_XP 0x00000f00 #define RP_VEND_XP_DL_UP (1 << 30) @@ -254,6 +280,14 @@ struct tegra_pcie_soc { u32 tx_ref_sel; u32 pads_refclk_cfg0; u32 pads_refclk_cfg1; + u32 rp_ectl_2_r1; + u32 rp_ectl_4_r1; + u32 rp_ectl_5_r1; + u32 rp_ectl_6_r1; + u32 rp_ectl_2_r2; + u32 rp_ectl_4_r2; + u32 rp_ectl_5_r2; + u32 rp_ectl_6_r2; bool has_pex_clkreq_en; bool has_pex_bias_ctrl; bool has_intr_prsnt_sense; @@ -261,6 +295,7 @@ struct tegra_pcie_soc { bool has_gen2; bool force_pca_enable; bool program_uphy; + bool program_ectl_settings; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2058,6 +2093,52 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie) pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); } +static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port) +{ + unsigned long value; + const struct tegra_pcie_soc *soc = port->pcie->soc; + + value = readl(port->base + RP_ECTL_2_R1); + value &= ~RP_ECTL_2_R1_RX_CTLE_1C_MASK; + value |= soc->rp_ectl_2_r1; + writel(value, port->base + RP_ECTL_2_R1); + + value = readl(port->base + RP_ECTL_4_R1); + value &= ~RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK; + value |= (soc->rp_ectl_4_r1 << RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT); + writel(value, port->base + RP_ECTL_4_R1); + + value = readl(port->base + RP_ECTL_5_R1); + value &= ~RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK; + value |= soc->rp_ectl_5_r1; + writel(value, port->base + RP_ECTL_5_R1); + + value = readl(port->base + RP_ECTL_6_R1); + value &= ~RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK; + value |= soc->rp_ectl_6_r1; + writel(value, port->base + RP_ECTL_6_R1); + + value = readl(port->base + RP_ECTL_2_R2); + value &= ~RP_ECTL_2_R2_RX_CTLE_1C_MASK; + value |= soc->rp_ectl_2_r2; + writel(value, port->base + RP_ECTL_2_R2); + + value = readl(port->base + RP_ECTL_4_R2); + value &= ~RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK; + value |= (soc->rp_ectl_4_r2 << RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT); + writel(value, port->base + RP_ECTL_4_R2); + + value = readl(port->base + RP_ECTL_5_R2); + value &= ~RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK; + value |= soc->rp_ectl_5_r2; + writel(value, port->base + RP_ECTL_5_R2); + + value = readl(port->base + RP_ECTL_6_R2); + value &= ~RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK; + value |= soc->rp_ectl_6_r2; + writel(value, port->base + RP_ECTL_6_R2); +} + static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) { unsigned long value; @@ -2125,6 +2206,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; struct tegra_pcie_port *port, *tmp; + const struct tegra_pcie_soc *soc = pcie->soc; tegra_pcie_apply_pad_settings(pcie); @@ -2133,6 +2215,8 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) port->index, port->lanes); tegra_pcie_port_enable(port); + if (soc->program_ectl_settings) + tegra_pcie_program_ectl_settings(port); tegra_pcie_enable_rp_features(port); } @@ -2199,6 +2283,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, + .program_ectl_settings = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2215,6 +2300,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, + .program_ectl_settings = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2230,6 +2316,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .has_gen2 = true, .force_pca_enable = false, .program_uphy = true, + .program_ectl_settings = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2238,6 +2325,14 @@ static const struct tegra_pcie_soc tegra210_pcie = { .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, .pads_refclk_cfg0 = 0x90b890b8, + .rp_ectl_2_r1 = 0x0000000f, + .rp_ectl_4_r1 = 0x00000067, + .rp_ectl_5_r1 = 0x55010000, + .rp_ectl_6_r1 = 0x00000001, + .rp_ectl_2_r2 = 0x0000008f, + .rp_ectl_4_r2 = 0x000000c7, + .rp_ectl_5_r2 = 0x55010000, + .rp_ectl_6_r2 = 0x00000001, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, @@ -2245,6 +2340,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .has_gen2 = true, .force_pca_enable = true, .program_uphy = true, + .program_ectl_settings = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2261,6 +2357,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .has_gen2 = true, .force_pca_enable = false, .program_uphy = false, + .program_ectl_settings = false, }; static const struct of_device_id tegra_pcie_of_match[] = { From patchwork Mon Oct 30 13:57:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832058 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbjh493zz9t2c for ; Tue, 31 Oct 2017 01:00:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752561AbdJ3OAy (ORCPT ); Mon, 30 Oct 2017 10:00:54 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:18588 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752455AbdJ3OAy (ORCPT ); Mon, 30 Oct 2017 10:00:54 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 30 Oct 2017 07:00:24 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 07:00:43 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 07:00:43 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:18 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:18 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:17 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 06/12] PCI: tegra: Enable opportunistic update FC and ACK Date: Mon, 30 Oct 2017 19:27:17 +0530 Message-ID: <1509371843-22931-7-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch ensures that DL sends pending ACKs and update FC packets when link is idle instead of waiting for timers to expire which improves PCIe bandwidth. Signed-off-by: Manikanta Maddireddy --- V3: * no change in this patch V2: * no change in this patch drivers/pci/host/pci-tegra.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index c862facfd6e9..4562b0c113a8 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -211,7 +211,9 @@ #define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff #define RP_VEND_XP 0x00000f00 -#define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) +#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_CTL1 0xf48 #define RP_VEND_CTL1_ERPT (1 << 13) @@ -2149,6 +2151,16 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) writel(value, port->base + RP_VEND_CTL1); } +static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) +{ + unsigned long value; + + /* Optimal settings to enhance bandwidth */ + value = readl(port->base + RP_VEND_XP); + value |= RP_VEND_XP_OPPORTUNISTIC_ACK; + value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC; + writel(value, port->base + RP_VEND_XP); +} /* * FIXME: If there are no PCIe cards attached, then calling this function * can result in the increase of the bootup time as there are big timeout @@ -2218,6 +2230,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) if (soc->program_ectl_settings) tegra_pcie_program_ectl_settings(port); tegra_pcie_enable_rp_features(port); + tegra_pcie_apply_sw_fixup(port); } /* take the PCIe interface module out of reset */ From patchwork Mon Oct 30 13:57:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832045 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbgZ0nR9z9t2c for ; Tue, 31 Oct 2017 00:59:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752262AbdJ3N7E (ORCPT ); Mon, 30 Oct 2017 09:59:04 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17825 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752212AbdJ3N7E (ORCPT ); Mon, 30 Oct 2017 09:59:04 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 30 Oct 2017 06:58:35 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 06:59:11 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 06:59:11 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:26 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:25 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:25 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:25 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 07/12] PCI: tegra: Disable AFI dynamic clock gating Date: Mon, 30 Oct 2017 19:27:18 +0530 Message-ID: <1509371843-22931-8-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org When there are 32 outstanding writes from AFI to memory, the outstanding write counter overflows and indicates that there are "0" outstanding write transactions. This outstanding write counter is used to generate IDLE signal to dynamically gate the AFI clock. When memory controller is under heavy load, its possible that write completions will come back to AFI after long delay and AFI write counter overflows. AFI clock gets gated even when there are outstanding transactions towards memory controller resutling in system hang. Disable dynamic clock gating of AFI clock to avoid system hang. Signed-off-by: Manikanta Maddireddy --- V3: * no change in this patch V2: * no change in this patch drivers/pci/host/pci-tegra.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 4562b0c113a8..c264037112cb 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -103,8 +103,9 @@ #define AFI_MSI_EN_VEC6 0xa4 #define AFI_MSI_EN_VEC7 0xa8 -#define AFI_CONFIGURATION 0xac -#define AFI_CONFIGURATION_EN_FPCI (1 << 0) +#define AFI_CONFIGURATION 0xac +#define AFI_CONFIGURATION_EN_FPCI (1 << 0) +#define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31) #define AFI_FPCI_ERROR_MASKS 0xb0 @@ -1059,9 +1060,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) } } - /* finally enable PCIe */ + /* Disable AFI dynamic clock gating and enable PCIe */ value = afi_readl(pcie, AFI_CONFIGURATION); - value |= AFI_CONFIGURATION_EN_FPCI; + value |= (AFI_CONFIGURATION_EN_FPCI | + AFI_CONFIGURATION_CLKEN_OVERRIDE); afi_writel(pcie, value, AFI_CONFIGURATION); value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | From patchwork Mon Oct 30 13:57:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832047 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbgw2scJz9t2c for ; Tue, 31 Oct 2017 00:59:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752155AbdJ3N7X (ORCPT ); Mon, 30 Oct 2017 09:59:23 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8332 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752103AbdJ3N7W (ORCPT ); Mon, 30 Oct 2017 09:59:22 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 30 Oct 2017 06:58:55 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 06:58:57 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 06:58:57 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:30 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:30 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:30 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:30 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2 Date: Mon, 30 Oct 2017 19:27:19 +0530 Message-ID: <1509371843-22931-9-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Set required bit to have LTSSM wait for DLLP to finish before entering L1 or L2. This avoids truncation of PM messages which results in receiver errors. Signed-off-by: Manikanta Maddireddy --- V3: * no change in this patch V2: * no change in this patch drivers/pci/host/pci-tegra.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index c264037112cb..34740a7033f7 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -219,6 +219,9 @@ #define RP_VEND_CTL1 0xf48 #define RP_VEND_CTL1_ERPT (1 << 13) +#define RP_VEND_XP_BIST 0xf4c +#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -2162,6 +2165,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_XP_OPPORTUNISTIC_ACK; value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC; writel(value, port->base + RP_VEND_XP); + + /* LTSSM will wait for DLLP to finish before entering L1 or L2, + * to avoid truncation of PM messages which results in receiver errors + */ + value = readl(port->base + RP_VEND_XP_BIST); + value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; + writel(value, port->base + RP_VEND_XP_BIST); } /* * FIXME: If there are no PCIe cards attached, then calling this function From patchwork Mon Oct 30 13:57:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832043 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbgX0WwKz9t2c for ; Tue, 31 Oct 2017 00:59:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752213AbdJ3N7C (ORCPT ); Mon, 30 Oct 2017 09:59:02 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8298 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751624AbdJ3N7C (ORCPT ); Mon, 30 Oct 2017 09:59:02 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 30 Oct 2017 06:58:35 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 06:58:37 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 06:58:37 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:35 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:35 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:35 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 09/12] PCI: tegra: Enable PCIe xclk clock clamping Date: Mon, 30 Oct 2017 19:27:20 +0530 Message-ID: <1509371843-22931-10-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch enables PCIe xlck clock clamping by pad control. Pad control asserts UPHY lane sleep signal when L1 entry signal received from PCIe. UPHY sleep signal assertion is done per lane. Default clamp threshold margin is not enough to assert all UPHY lane sleep signals. Increase the clamp threshold in Tegra124, 132, 210 and 186. Signed-off-by: Manikanta Maddireddy --- V3: * Parentheses removed for OR operation V2: * no change in this patch drivers/pci/host/pci-tegra.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 34740a7033f7..9f13e6fcc64e 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -226,8 +226,14 @@ #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) #define RP_PRIV_MISC 0x00000fe0 -#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) -#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) +#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) +#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK (0x7f << 16) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD (0xf << 16) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE (1 << 23) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK (0x7f << 24) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD (0xf << 24) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE (1 << 31) #define RP_LINK_CONTROL_STATUS 0x00000090 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 @@ -302,6 +308,7 @@ struct tegra_pcie_soc { bool force_pca_enable; bool program_uphy; bool program_ectl_settings; + bool update_clamp_threshold; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2158,6 +2165,7 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) { + const struct tegra_pcie_soc *soc = port->pcie->soc; unsigned long value; /* Optimal settings to enhance bandwidth */ @@ -2172,6 +2180,17 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value = readl(port->base + RP_VEND_XP_BIST); value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; writel(value, port->base + RP_VEND_XP_BIST); + + value = readl(port->base + RP_PRIV_MISC); + value |= RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE | + RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE; + if (soc->update_clamp_threshold) { + value &= ~(RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK | + RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK); + value |= RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD | + RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD; + } + writel(value, port->base + RP_PRIV_MISC); } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2309,6 +2328,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .force_pca_enable = false, .program_uphy = true, .program_ectl_settings = false, + .update_clamp_threshold = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2326,6 +2346,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .force_pca_enable = false, .program_uphy = true, .program_ectl_settings = false, + .update_clamp_threshold = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2342,6 +2363,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .force_pca_enable = false, .program_uphy = true, .program_ectl_settings = false, + .update_clamp_threshold = true, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2366,6 +2388,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .force_pca_enable = true, .program_uphy = true, .program_ectl_settings = true, + .update_clamp_threshold = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2383,6 +2406,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .force_pca_enable = false, .program_uphy = false, .program_ectl_settings = false, + .update_clamp_threshold = false, }; static const struct of_device_id tegra_pcie_of_match[] = { From patchwork Mon Oct 30 13:57:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832062 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbk40vW4z9t2c for ; Tue, 31 Oct 2017 01:01:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752563AbdJ3OBO (ORCPT ); Mon, 30 Oct 2017 10:01:14 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8561 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752562AbdJ3OBO (ORCPT ); Mon, 30 Oct 2017 10:01:14 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 30 Oct 2017 07:00:52 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 07:01:10 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 07:01:10 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:40 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:40 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:39 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 10/12] PCI: tegra: Add SW fixup for RAW violations Date: Mon, 30 Oct 2017 19:27:21 +0530 Message-ID: <1509371843-22931-11-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The logic which blocks read requests till AFI gets ACK for all outstanding MC writes does not behave correctly when number of outstanding write becomes more than 32. SW fixup to prevent this issue is to limit outstanding posted writes and tweak updateFC timer threshold. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V3: * changed soc parameter name V2: * no change in this patch drivers/pci/host/pci-tegra.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 9f13e6fcc64e..3993e9221c96 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -185,6 +185,13 @@ #define AFI_PEXBIAS_CTRL_0 0x168 +#define RP_PRIV_XP_DL 0x494 +#define RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD (0x1ff << 1) + +#define RP_RX_HDR_LIMIT 0xe00 +#define RP_RX_HDR_LIMIT_PW_MASK (0xff << 8) +#define RP_RX_HDR_LIMIT_PW (0x0e << 8) + #define RP_ECTL_2_R1 0xe84 #define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff @@ -215,6 +222,7 @@ #define RP_VEND_XP_DL_UP (1 << 30) #define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) +#define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) #define RP_VEND_CTL1 0xf48 #define RP_VEND_CTL1_ERPT (1 << 13) @@ -309,6 +317,7 @@ struct tegra_pcie_soc { bool program_uphy; bool program_ectl_settings; bool update_clamp_threshold; + bool raw_violation_fixup; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2191,6 +2200,22 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD; } writel(value, port->base + RP_PRIV_MISC); + + /* Fixup for read after write violation in T124 & T132 platforms */ + if (soc->raw_violation_fixup) { + value = readl(port->base + RP_RX_HDR_LIMIT); + value &= ~RP_RX_HDR_LIMIT_PW_MASK; + value |= RP_RX_HDR_LIMIT_PW; + writel(value, port->base + RP_RX_HDR_LIMIT); + + value = readl(port->base + RP_PRIV_XP_DL); + value |= RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD; + writel(value, port->base + RP_PRIV_XP_DL); + + value = readl(port->base + RP_VEND_XP); + value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK; + writel(value, port->base + RP_VEND_XP); + } } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2329,6 +2354,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .program_uphy = true, .program_ectl_settings = false, .update_clamp_threshold = false, + .raw_violation_fixup = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2347,6 +2373,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .program_uphy = true, .program_ectl_settings = false, .update_clamp_threshold = false, + .raw_violation_fixup = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2364,6 +2391,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .program_uphy = true, .program_ectl_settings = false, .update_clamp_threshold = true, + .raw_violation_fixup = true, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2389,6 +2417,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .program_uphy = true, .program_ectl_settings = true, .update_clamp_threshold = true, + .raw_violation_fixup = false, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2407,6 +2436,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .program_uphy = false, .program_ectl_settings = false, .update_clamp_threshold = false, + .raw_violation_fixup = false, }; static const struct of_device_id tegra_pcie_of_match[] = { From patchwork Mon Oct 30 13:57:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832051 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbhV5Ncnz9t1G for ; Tue, 31 Oct 2017 00:59:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752103AbdJ3N7x (ORCPT ); Mon, 30 Oct 2017 09:59:53 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8362 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751959AbdJ3N7x (ORCPT ); Mon, 30 Oct 2017 09:59:53 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 30 Oct 2017 06:59:41 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 06:59:42 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 06:59:42 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:45 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:45 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:44 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 11/12] PCI: tegra: Increase the deskew retry time Date: Mon, 30 Oct 2017 19:27:22 +0530 Message-ID: <1509371843-22931-12-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some times Gen2 to Gen1 link speed switching fails due to instability in deskew logic on lane0 in Tegra210. Increase the deskew retry time to resolve this issue. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V3: * no change in this patch V2: * no change in this patch drivers/pci/host/pci-tegra.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 3993e9221c96..b29329226e3d 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -224,6 +224,10 @@ #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) +#define RP_VEND_CTL0 0xf44 +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12) + #define RP_VEND_CTL1 0xf48 #define RP_VEND_CTL1_ERPT (1 << 13) @@ -318,6 +322,7 @@ struct tegra_pcie_soc { bool program_ectl_settings; bool update_clamp_threshold; bool raw_violation_fixup; + bool program_deskew_time; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2216,6 +2221,16 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK; writel(value, port->base + RP_VEND_XP); } + + /* Tune deskew retry time to take care of Gen2 -> Gen1 + * link speed change error in corner cases + */ + if (soc->program_deskew_time) { + value = readl(port->base + RP_VEND_CTL0); + value &= ~RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK; + value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH; + writel(value, port->base + RP_VEND_CTL0); + } } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2355,6 +2370,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .program_ectl_settings = false, .update_clamp_threshold = false, .raw_violation_fixup = false, + .program_deskew_time = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2374,6 +2390,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .program_ectl_settings = false, .update_clamp_threshold = false, .raw_violation_fixup = false, + .program_deskew_time = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2392,6 +2409,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .program_ectl_settings = false, .update_clamp_threshold = true, .raw_violation_fixup = true, + .program_deskew_time = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2418,6 +2436,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .program_ectl_settings = true, .update_clamp_threshold = true, .raw_violation_fixup = false, + .program_deskew_time = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2437,6 +2456,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .program_ectl_settings = false, .update_clamp_threshold = false, .raw_violation_fixup = false, + .program_deskew_time = false, }; static const struct of_device_id tegra_pcie_of_match[] = { From patchwork Mon Oct 30 13:57:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832060 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbjt24d2z9t2c for ; Tue, 31 Oct 2017 01:01:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752455AbdJ3OBF (ORCPT ); Mon, 30 Oct 2017 10:01:05 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:18606 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752053AbdJ3OBE (ORCPT ); Mon, 30 Oct 2017 10:01:04 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 30 Oct 2017 07:00:34 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 07:00:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 07:00:53 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:50 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:50 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:50 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 12/12] PCI: tegra: Update flow control threshold in Tegra210 Date: Mon, 30 Oct 2017 19:27:23 +0530 Message-ID: <1509371843-22931-13-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Recommended update FC threshold in Tegra210 is 0x60 for best performance of x1 link. Setting this to 0x60 provides the best balance between number of UpdateFC and read data sent over the link. Signed-off-by: Manikanta Maddireddy --- V3: * changed soc parameter name V2: * no change in this patch drivers/pci/host/pci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index b29329226e3d..812d32cfdd0e 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -223,6 +223,7 @@ #define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) +#define RP_VEND_XP_UPDATE_FC_THRESHOLD_T210 (0x60 << 18) #define RP_VEND_CTL0 0xf44 #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) @@ -323,6 +324,7 @@ struct tegra_pcie_soc { bool update_clamp_threshold; bool raw_violation_fixup; bool program_deskew_time; + bool update_fc_threshold; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2231,6 +2233,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH; writel(value, port->base + RP_VEND_CTL0); } + + if (soc->update_fc_threshold) { + value = readl(port->base + RP_VEND_XP); + value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK; + value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_T210; + writel(value, port->base + RP_VEND_XP); + } } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2371,6 +2380,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .update_clamp_threshold = false, .raw_violation_fixup = false, .program_deskew_time = false, + .update_fc_threshold = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2391,6 +2401,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .update_clamp_threshold = false, .raw_violation_fixup = false, .program_deskew_time = false, + .update_fc_threshold = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2410,6 +2421,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .update_clamp_threshold = true, .raw_violation_fixup = true, .program_deskew_time = false, + .update_fc_threshold = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2437,6 +2449,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .update_clamp_threshold = true, .raw_violation_fixup = false, .program_deskew_time = true, + .update_fc_threshold = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2457,6 +2470,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .update_clamp_threshold = false, .raw_violation_fixup = false, .program_deskew_time = false, + .update_fc_threshold = false, }; static const struct of_device_id tegra_pcie_of_match[] = {