From patchwork Tue May 21 13:32:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 1102753 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="f26zEdbO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 457cCg754fz9sCJ for ; Tue, 21 May 2019 23:33:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726900AbfEUNdS (ORCPT ); Tue, 21 May 2019 09:33:18 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:32928 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727976AbfEUNdS (ORCPT ); Tue, 21 May 2019 09:33:18 -0400 Received: by mail-pf1-f196.google.com with SMTP id z28so9121714pfk.0 for ; Tue, 21 May 2019 06:33:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=1nncQI8i+UzrmjnlsMRQHRUYfFHMZeTgvwjX0KHzdBA=; b=f26zEdbOr6/dfMG4dZ18wDImXn+s/c9tAyneJjTEQ8q4wwuCQOoRV0s9WNWLE5TY/+ 6FPXNnznDxFmhxUkuG206BsU1sCn29p1+zIGX1OiapFO5QTKyhVUB7T9pxTo1gsoMxF2 snSehzN5j/TwJbSUF0HFLSHe70+I34quFmDL9NC7ctWrpgKRM5kX9le0izOaUO0GdYXR mMkX6faXXaiQrFZAn4GgylFDFlhz239Tc/xJouGdAs3uTuibqre29yXkcDaro6ZLYGHQ xpC2SE/ixcmNRq47e4XR/hQxVwhh5a5TW2CE8szYNM5qHM1UgCbBRXhYawPXuRhmT061 AogA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=1nncQI8i+UzrmjnlsMRQHRUYfFHMZeTgvwjX0KHzdBA=; b=DZz6awQWkh7jwE7YodRgBu1CwtKkwxKLlySSUwd8zbNH7fRkTxVGvDA1No/i8iCZN7 6DZobJJ0yUqtn7UG0Al/pNP8M16fs2AWyRdhlDc5uBcEUglcb1TtQzhQj+yYQH3GznP4 0vP87BI1srrkNwjk5xJj26Uh7FKsprLrwFLQUgbzco4RZCtNKr/QgBSn09/+RgsSwFu3 9nSwZLl0rBYvdbDns3bd/2aBvnheuGcfalGHfFDgDFaDeY9Tlzhs7bqyj3weLZl7+Pca R9I8MLzL2BI82ZrF0mDrjbDU3vssRxvpOqVu7Q6I57Q0vXtByzgd0D5xh7Zu9B98ujcW ijvw== X-Gm-Message-State: APjAAAUXtkXIkR3I3gjRGRAsoqhUA/hchXB00MvWcEOSn9tliKNjuc0m m0JCnJFiHdwqLPHamiSQLctHip1TDdiQWw== X-Google-Smtp-Source: APXvYqz+cNDOns4a+HlYUkMCadstIOBWgdjWKopWeJjmo4sMLBkDSX21RNmLsVKKcrIEMBu95K3+Og== X-Received: by 2002:a65:628b:: with SMTP id f11mr78696250pgv.95.1558445597973; Tue, 21 May 2019 06:33:17 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id d15sm65368906pfm.186.2019.05.21.06.33.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 May 2019 06:33:17 -0700 (PDT) From: Sagar Shrikant Kadam To: robh+dt@kernel.org, mark.rutland@arm.com, peter@korsgaard.com, andrew@lunn.ch, palmer@sifive.com, paul.walmsley@sifive.com, sagar.kadam@sifive.com, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/3] dt-bindings: i2c: extend existing opencore bindings. Date: Tue, 21 May 2019 19:02:52 +0530 Message-Id: <1558445574-16471-2-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1558445574-16471-1-git-send-email-sagar.kadam@sifive.com> References: <1558445574-16471-1-git-send-email-sagar.kadam@sifive.com> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Reformatted compatibility strings to one valid combination on each line. Add FU540-C000 specific device tree bindings to already available i2-ocores file. This device is available on HiFive Unleashed Rev A00 board. Move interrupt under optional property list as this can be optional. The FU540-C000 SoC from sifive, has an Opencore's I2C block reimplementation. The DT compatibility string for this IP is present in HDL and available at. https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/i2c/I2C.scala#L73 Signed-off-by: Sagar Shrikant Kadam --- Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt index 17bef9a..6ac062c 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt @@ -1,9 +1,13 @@ Device tree configuration for i2c-ocores Required properties: -- compatible : "opencores,i2c-ocores" or "aeroflexgaisler,i2cmst" +- compatible : "opencores,i2c-ocores", + "aeroflexgaisler,i2cmst", + "sifive,fu540-c000-i2c","sifive,i2c0". + For Opencore based I2C IP block reimplemented in + FU540-C000 SoC.Please refer sifive-blocks-ip-versioning.txt + for additional details. - reg : bus address start and address range size of device -- interrupts : interrupt number - clocks : handle to the controller clock; see the note below. Mutually exclusive with opencores,ip-clock-frequency - opencores,ip-clock-frequency: frequency of the controller clock in Hz; @@ -12,6 +16,7 @@ Required properties: - #size-cells : should be <0> Optional properties: +- interrupts : interrupt number. - clock-frequency : frequency of bus clock in Hz; see the note below. Defaults to 100 KHz when the property is not specified - reg-shift : device register offsets are shifted by this value From patchwork Tue May 21 13:32:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 1102755 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="MihmeJoI"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 457cCv09Kgz9sMM for ; Tue, 21 May 2019 23:33:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728321AbfEUNdZ (ORCPT ); Tue, 21 May 2019 09:33:25 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:44281 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728317AbfEUNdY (ORCPT ); Tue, 21 May 2019 09:33:24 -0400 Received: by mail-pg1-f195.google.com with SMTP id n2so1935280pgp.11 for ; Tue, 21 May 2019 06:33:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=/BRFvwHTJGi4mC+l6/NtyYz/ZOf9cjorYo3iOt6cwfc=; b=MihmeJoI2Kctk0t4cBE6oHsC3/eL4jMiONd0z9ECsi8xF1h36S2fBIAYttGJ+D/VR6 lqUeTum/ne1zyIfAWGp7YIF0hAuqw9Ru6Ee9KOw4M6h1fHcU4CtUeCPLTrt+ESAkZDbz EBvXNPjJps5LmyKDeUtSTeh+zfNLZnSFKAsV6P3uiaN5nQ9DXL/+28bW7LQWUN9lPRju jNS+d1P3PwHSigIq5bMuDW2bUKSUvzDGM24Wc/2iDlKQagXjw6WGe1SdsZQja2oPT7cL GMXoYXJBGLWcysOjoJih56jXxc9nUsTO29getB3MaFyK4NGgHFSSoOZtJQ8ueCZ1LZDe sO1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=/BRFvwHTJGi4mC+l6/NtyYz/ZOf9cjorYo3iOt6cwfc=; b=lWYpLgyGGTrWU1kL5pMBlnkPGk5QEhwQkZ6VGo5uhL89cvY/LdBaUNpJf3WnVxGKJZ SIFn/iRzha19zj7B31qNie8gqnYrFNcFRXj97v12xZHFtSyQXwtT96gBjknpq/k4MwSk PihWKBBsajFm6QISJRWe9PStJNRKjF5UaNO+ncAImqZ4kAJASVcZDVgw7hug8CY6L1C+ YnUi95fS2Kxy+ezC1atwF0WxlGgIeGfLa5hP5jM44kKaWNKoXqcs/O67XGDpcyiHg7e+ u2a9qjmcv+L65X+GTtKu8zk+o7DlvzAFKENrXLb101Jr++idQ8+yO/8U32c+bjkLwpJO cNzg== X-Gm-Message-State: APjAAAUR+XrUfGEPRaeNVcXWGy4M7trSum0smO2h1Km+mLKBVR9LplK0 xwPSH1Mr+G9FPniU8GqSBGZzbw== X-Google-Smtp-Source: APXvYqxEv2PJu+YRU/OJSvjSo53F+3SPbm1+GyvMmTi3+tv2KXiA05zIWK5yTfHuZpUZZI5bB1e+Mw== X-Received: by 2002:a63:e43:: with SMTP id 3mr39548393pgo.253.1558445604442; Tue, 21 May 2019 06:33:24 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id d15sm65368906pfm.186.2019.05.21.06.33.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 May 2019 06:33:22 -0700 (PDT) From: Sagar Shrikant Kadam To: robh+dt@kernel.org, mark.rutland@arm.com, peter@korsgaard.com, andrew@lunn.ch, palmer@sifive.com, paul.walmsley@sifive.com, sagar.kadam@sifive.com, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 2/3] i2c-ocores: sifive: add support for i2c device on FU540-c000 SoC. Date: Tue, 21 May 2019 19:02:53 +0530 Message-Id: <1558445574-16471-3-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1558445574-16471-1-git-send-email-sagar.kadam@sifive.com> References: <1558445574-16471-1-git-send-email-sagar.kadam@sifive.com> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Update device id table for Opencore's I2C master based re-implementation used in FU540-c000 chipset on HiFive Unleashed platform. Device ID's include Sifive, soc-specific device for chip specific tweaks and sifive IP block specific device for generic programming model. Signed-off-by: Sagar Shrikant Kadam --- drivers/i2c/busses/i2c-ocores.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c index c3dabee..b334fa2 100644 --- a/drivers/i2c/busses/i2c-ocores.c +++ b/drivers/i2c/busses/i2c-ocores.c @@ -82,6 +82,7 @@ struct ocores_i2c { #define TYPE_OCORES 0 #define TYPE_GRLIB 1 +#define TYPE_SIFIVE_REV0 2 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) { @@ -462,6 +463,14 @@ static u32 ocores_func(struct i2c_adapter *adap) .compatible = "aeroflexgaisler,i2cmst", .data = (void *)TYPE_GRLIB, }, + { + .compatible = "sifive,fu540-c000-i2c", + .data = (void *)TYPE_SIFIVE_REV0, + }, + { + .compatible = "sifive,i2c0", + .data = (void *)TYPE_SIFIVE_REV0, + }, {}, }; MODULE_DEVICE_TABLE(of, ocores_i2c_match); From patchwork Tue May 21 13:32:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 1102756 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="VlOYu1dr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 457cD13bG2z9sMM for ; Tue, 21 May 2019 23:33:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728339AbfEUNdg (ORCPT ); Tue, 21 May 2019 09:33:36 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:34959 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728053AbfEUNdb (ORCPT ); Tue, 21 May 2019 09:33:31 -0400 Received: by mail-pl1-f193.google.com with SMTP id p1so3091619plo.2 for ; Tue, 21 May 2019 06:33:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=q9ZIgayitHYinuwIIIQjmbyGj4R/0KKMdcZ9auHzvr8=; b=VlOYu1drdYLZpHJV9yk0qWwSSx5N4LCVyuAnvbVQ2maCo9bVARUiY89bZ1yKPhQCcH uNvDtxSgCuPt3Ou37gyoxRCm/9qexGEjOWipubkYFzvm6+F4Fazk2Q5S1WHGsW3SOYis C7cPoFIqYa4MEZ1trtTOhUXsiHoAjNl4bkEJe06N6edwmKhwXdq5wWmH2yEKnVMIaKR4 AwbUMSTsfTlj43zrdVGSUl2wkrPrzteOPZScOYgg/PEXBq8b2vzftNajJPqmkNpNfcxq gF1EJ26O7OCpQEhcta7+PRX1PRcD7FZzYeHylUeNWK4DQk8rBl7ohWSoPx9cIVRf/1Sd fHqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=q9ZIgayitHYinuwIIIQjmbyGj4R/0KKMdcZ9auHzvr8=; b=CiQbPx3XAT/q3B2vgzYlO7Xe3FqlWI5Ac2WFq9rSYoBXEq+stebWz29jQJxlPplHQx nL4etKda7dKz2Wam8DAUcd4OQQ+xOUMY26xmx1GCiZMXu1RlbavK8zl00Eho+WjJeUwG Bo/HpmiOz0ETuMHtRK8gK8sLwUmcfu7xyD7MNX9ndmGsB3FuzC2GUWrhzjBzEq/ZhlsY aJm3RzEuNcvGu8jR/jxc9YVfsGWf0rFTUyk2gFGOtQDsau4lrqYXteaY2rEGh16o/4M/ 6NN8nwyWO4gbCTK4t/p3I18TDWB4T/38zSGsVKsPsGBjhLc34YxnN5omwZzSwer+AsmA wV0Q== X-Gm-Message-State: APjAAAWDuzbB6A7CaxzzebHjsFq3r5uQenL/c3avUD7fyb0vxGs+LgV1 ifehs3l9ZC5hWkmQCxyqedvTJQ== X-Google-Smtp-Source: APXvYqwosybVnv92iOwCWSgxiLTjp16vqLrYP4NZArVA1GDu0mXZO7aPxnIG51uYXApdUCoO0dkHxQ== X-Received: by 2002:a17:902:2aa6:: with SMTP id j35mr503646plb.189.1558445610576; Tue, 21 May 2019 06:33:30 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id d15sm65368906pfm.186.2019.05.21.06.33.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 May 2019 06:33:29 -0700 (PDT) From: Sagar Shrikant Kadam To: robh+dt@kernel.org, mark.rutland@arm.com, peter@korsgaard.com, andrew@lunn.ch, palmer@sifive.com, paul.walmsley@sifive.com, sagar.kadam@sifive.com, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/3] i2c-ocores: sifive: add polling mode workaround for FU540-C000 SoC. Date: Tue, 21 May 2019 19:02:54 +0530 Message-Id: <1558445574-16471-4-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1558445574-16471-1-git-send-email-sagar.kadam@sifive.com> References: <1558445574-16471-1-git-send-email-sagar.kadam@sifive.com> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org The i2c-ocore driver already has a polling mode interface.But it needs a workaround for FU540 Chipset on HiFive unleashed board (RevA00). There is an erratum in FU540 chip that prevents interrupt driven i2c transfers from working, and also the I2C controller's interrupt bit cannot be cleared if set, due to this the existing i2c polling mode interface added in mainline earlier doesn't work, and CPU stall's infinitely, when-ever i2c transfer is initiated. Ref: commit dd7dbf0eb090 ("i2c: ocores: refactor setup for polling") The workaround / fix under OCORES_FLAG_BROKEN_IRQ is particularly for FU540-COOO SoC. The polling function identifies a SiFive device based on the device node and enables the workaround. Signed-off-by: Sagar Shrikant Kadam --- drivers/i2c/busses/i2c-ocores.c | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c index b334fa2..3175c72 100644 --- a/drivers/i2c/busses/i2c-ocores.c +++ b/drivers/i2c/busses/i2c-ocores.c @@ -84,6 +84,10 @@ struct ocores_i2c { #define TYPE_GRLIB 1 #define TYPE_SIFIVE_REV0 2 +#define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */ + +static const struct of_device_id ocores_i2c_match[]; + static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) { iowrite8(value, i2c->base + (reg << i2c->reg_shift)); @@ -236,9 +240,13 @@ static irqreturn_t ocores_isr(int irq, void *dev_id) struct ocores_i2c *i2c = dev_id; u8 stat = oc_getreg(i2c, OCI2C_STATUS); - if (!(stat & OCI2C_STAT_IF)) + if (irq == OCORES_FLAG_BROKEN_IRQ) { + if (stat & OCI2C_STAT_IF) + if (!(stat & OCI2C_STAT_BUSY)) + return IRQ_NONE; + } else if (!(stat & OCI2C_STAT_IF)) { return IRQ_NONE; - + } ocores_process(i2c, stat); return IRQ_HANDLED; @@ -340,6 +348,10 @@ static int ocores_poll_wait(struct ocores_i2c *i2c) */ static void ocores_process_polling(struct ocores_i2c *i2c) { + const struct of_device_id *match; + + match = of_match_node(ocores_i2c_match, i2c->adap.dev.of_node); + while (1) { irqreturn_t ret; int err; @@ -350,9 +362,25 @@ static void ocores_process_polling(struct ocores_i2c *i2c) break; /* timeout */ } - ret = ocores_isr(-1, i2c); - if (ret == IRQ_NONE) - break; /* all messages have been transferred */ + /* + * If it's a SiFive Device(FU540-C000 SoC ) use + * OCORES_FLAG_BROKEN_IRQ to enable workaround in + * polling mode. + */ + if (match && (long)match->data == TYPE_SIFIVE_REV0) { + ret = ocores_isr(OCORES_FLAG_BROKEN_IRQ, i2c); + if (ret == IRQ_NONE) + break; /* all messages have been transferred */ + else + if (i2c->state == STATE_DONE) + break; + } else { + ret = ocores_isr(-1, i2c); + if (ret == IRQ_NONE) + break; /* all messages have been transferred */ + + } + } }