From patchwork Mon Oct 30 04:18:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831856 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLsC1gNdz9t3B for ; Mon, 30 Oct 2017 15:21:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750758AbdJ3EVd (ORCPT ); Mon, 30 Oct 2017 00:21:33 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15959 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751315AbdJ3EVc (ORCPT ); Mon, 30 Oct 2017 00:21:32 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 29 Oct 2017 21:21:03 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:21:38 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 29 Oct 2017 21:21:38 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:19:36 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:19:36 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:19:36 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 01/12] PCI: tegra: Start LTSSM after programming root port Date: Mon, 30 Oct 2017 09:48:52 +0530 Message-ID: <1509337143-25963-2-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch ensures that LTSSM is started (by deasserting pcie_xrst) only after all the required root port register programming is completed. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 96e8038c3019..b41c60c7414c 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -1024,9 +1024,6 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) } } - /* take the PCIe interface module out of reset */ - reset_control_deassert(pcie->pcie_xrst); - /* finally enable PCIe */ value = afi_readl(pcie, AFI_CONFIGURATION); value |= AFI_CONFIGURATION_EN_FPCI; @@ -1065,7 +1062,6 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie) dev_err(dev, "failed to power off PHY(s): %d\n", err); } - reset_control_assert(pcie->pcie_xrst); reset_control_assert(pcie->afi_rst); reset_control_assert(pcie->pex_rst); @@ -2116,7 +2112,12 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) port->index, port->lanes); tegra_pcie_port_enable(port); + } + /* take the PCIe interface module out of reset */ + reset_control_deassert(pcie->pcie_xrst); + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { if (tegra_pcie_port_check_link(port)) continue; From patchwork Mon Oct 30 04:18:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831855 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLsB4X2Fz9t3v for ; Mon, 30 Oct 2017 15:21:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751853AbdJ3EVc (ORCPT ); Mon, 30 Oct 2017 00:21:32 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15958 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750758AbdJ3EVc (ORCPT ); Mon, 30 Oct 2017 00:21:32 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 29 Oct 2017 21:21:03 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:21:22 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 29 Oct 2017 21:21:22 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:19:43 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:19:43 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:19:43 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 02/12] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Date: Mon, 30 Oct 2017 09:48:53 +0530 Message-ID: <1509337143-25963-3-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In Tegra186 PHY programming is done by BPMP-FW, so PHY calls are skipped in driver. REFCLK pad settings are independent of PHY and should be programmed by driver. So move REFCLK pad settings out of phy_power_on(). These pad settings improves REFCLK peak to peak amplitude. Signed-off-by: Manikanta Maddireddy Reviewed-by: Mikko Perttunen --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index b41c60c7414c..2c64eb6cc3cc 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -910,7 +910,6 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port) static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; - const struct tegra_pcie_soc *soc = pcie->soc; struct tegra_pcie_port *port; int err; @@ -936,12 +935,6 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) } } - /* Configure the reference clock driver */ - pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); - - if (soc->num_ports > 2) - pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); - return 0; } @@ -2049,6 +2042,17 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie) return 0; } +static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie) +{ + const struct tegra_pcie_soc *soc = pcie->soc; + + /* Configure the reference clock driver */ + pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); + + if (soc->num_ports > 2) + pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); +} + /* * FIXME: If there are no PCIe cards attached, then calling this function * can result in the increase of the bootup time as there are big timeout @@ -2107,6 +2111,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) struct device *dev = pcie->dev; struct tegra_pcie_port *port, *tmp; + tegra_pcie_apply_pad_settings(pcie); list_for_each_entry_safe(port, tmp, &pcie->ports, list) { dev_info(dev, "probing port %u, using %u lanes\n", port->index, port->lanes); From patchwork Mon Oct 30 04:18:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831859 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLsZ0cVrz9t2M for ; Mon, 30 Oct 2017 15:21:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751347AbdJ3EVw (ORCPT ); Mon, 30 Oct 2017 00:21:52 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13972 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751209AbdJ3EVw (ORCPT ); Mon, 30 Oct 2017 00:21:52 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Sun, 29 Oct 2017 21:21:30 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:21:48 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 29 Oct 2017 21:21:48 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:19:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:19:55 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:19:54 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 03/12] PCI: tegra: Retrain link for Gen2 speed Date: Mon, 30 Oct 2017 09:48:54 +0530 Message-ID: <1509337143-25963-4-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra124, 132, 210 and 186 supports Gen2 link speed. After the link is up in Gen1, set target link speed as Gen2 and retrain link. Link switches to Gen2 speed if Gen2 capable end point is connected, else link stays in Gen1. Signed-off-by: Manikanta Maddireddy --- V2: * Fixed alignment issue drivers/pci/host/pci-tegra.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 2c64eb6cc3cc..9f6d331c3571 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -232,6 +232,8 @@ #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ +#define LINK_RETRAIN_TIMEOUT HZ + struct tegra_msi { struct msi_controller chip; DECLARE_BITMAP(used, INT_PCI_MSI_NR); @@ -2133,6 +2135,42 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) } } +static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie, + struct pci_dev *pci_dev) +{ + struct device *dev = pcie->dev; + unsigned long start_jiffies; + unsigned short val; + + /* Skip if the current device is not a root port */ + if (pci_pcie_type(pci_dev) != PCI_EXP_TYPE_ROOT_PORT) + return; + + pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL2, &val); + val &= ~PCI_EXP_LNKSTA_CLS; + val |= PCI_EXP_LNKSTA_CLS_5_0GB; + pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL2, val); + + /* Retrain the link */ + pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &val); + val |= PCI_EXP_LNKCTL_RL; + pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL, val); + + start_jiffies = jiffies; + for (;;) { + pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &val); + if (!(val & PCI_EXP_LNKSTA_LT)) + break; + if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) + break; + usleep_range(2000, 3000); + } + + if (val & PCI_EXP_LNKSTA_LT) + dev_err(dev, "link retrain of PCIe slot %u failed\n", + PCI_SLOT(pci_dev->devfn)); +} + static const struct tegra_pcie_soc tegra20_pcie = { .num_ports = 2, .msi_base_shift = 0, @@ -2334,6 +2372,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) struct pci_host_bridge *host; struct tegra_pcie *pcie; struct pci_bus *child; + struct pci_dev *pci_dev = NULL; int err; host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); @@ -2399,6 +2438,9 @@ static int tegra_pcie_probe(struct platform_device *pdev) pci_bus_add_devices(host->bus); + for_each_pci_dev(pci_dev) + tegra_pcie_change_link_speed(pcie, pci_dev); + if (IS_ENABLED(CONFIG_DEBUG_FS)) { err = tegra_pcie_debugfs_init(pcie); if (err < 0) From patchwork Mon Oct 30 04:18:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831853 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLs023d9z9t3B for ; Mon, 30 Oct 2017 15:21:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751478AbdJ3EVW (ORCPT ); Mon, 30 Oct 2017 00:21:22 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15951 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750758AbdJ3EVW (ORCPT ); Mon, 30 Oct 2017 00:21:22 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 29 Oct 2017 21:20:53 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:21:28 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 29 Oct 2017 21:21:28 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:20:07 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:20:07 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:20:07 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:20:07 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 04/12] PCI: tegra: Advertise AER capability Date: Mon, 30 Oct 2017 09:48:55 +0530 Message-ID: <1509337143-25963-5-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Default root port settings hide AER capability. This patch enables the advertisement of AER capability by root port. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 9f6d331c3571..2a7665a9ce5b 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -187,6 +187,9 @@ #define RP_VEND_XP 0x00000f00 #define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_CTL1 0xf48 +#define RP_VEND_CTL1_ERPT (1 << 13) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -2055,6 +2058,16 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie) pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); } +static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) +{ + unsigned long value; + + /* Enable AER capability */ + value = readl(port->base + RP_VEND_CTL1); + value |= RP_VEND_CTL1_ERPT; + writel(value, port->base + RP_VEND_CTL1); +} + /* * FIXME: If there are no PCIe cards attached, then calling this function * can result in the increase of the bootup time as there are big timeout @@ -2119,6 +2132,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) port->index, port->lanes); tegra_pcie_port_enable(port); + tegra_pcie_enable_rp_features(port); } /* take the PCIe interface module out of reset */ From patchwork Mon Oct 30 04:18:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831861 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLtY31Z9z9t3v for ; Mon, 30 Oct 2017 15:22:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750808AbdJ3EWo (ORCPT ); Mon, 30 Oct 2017 00:22:44 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5555 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750750AbdJ3EWn (ORCPT ); Mon, 30 Oct 2017 00:22:43 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sun, 29 Oct 2017 21:22:05 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:22:40 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 29 Oct 2017 21:22:40 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:20:22 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:20:22 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:20:22 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 05/12] PCI: tegra: Program UPHY electrical settings in Tegra210 Date: Mon, 30 Oct 2017 09:48:56 +0530 Message-ID: <1509337143-25963-6-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org UPHY electrical programming guidelines are documented in Tegra210 TRM. Program these electrical settings for proper eye diagram in all link speeds. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 95 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 2a7665a9ce5b..51b7821646eb 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -184,6 +184,30 @@ #define AFI_PEXBIAS_CTRL_0 0x168 +#define RP_ECTL_2_R1 0xe84 +#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff + +#define RP_ECTL_4_R1 0xe8c +#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK (0xffff << 16) + +#define RP_ECTL_5_R1 0xe90 +#define RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK 0xffffffff + +#define RP_ECTL_6_R1 0xe94 +#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK 0xffffffff + +#define RP_ECTL_2_R2 0xea4 +#define RP_ECTL_2_R2_RX_CTLE_1C_MASK 0xffff + +#define RP_ECTL_4_R2 0xeac +#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK (0xffff << 16) + +#define RP_ECTL_5_R2 0xeb0 +#define RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK 0xffffffff + +#define RP_ECTL_6_R2 0xeb4 +#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff + #define RP_VEND_XP 0x00000f00 #define RP_VEND_XP_DL_UP (1 << 30) @@ -254,6 +278,14 @@ struct tegra_pcie_soc { u32 tx_ref_sel; u32 pads_refclk_cfg0; u32 pads_refclk_cfg1; + u32 rp_ectl_2_r1; + u32 rp_ectl_4_r1; + u32 rp_ectl_5_r1; + u32 rp_ectl_6_r1; + u32 rp_ectl_2_r2; + u32 rp_ectl_4_r2; + u32 rp_ectl_5_r2; + u32 rp_ectl_6_r2; bool has_pex_clkreq_en; bool has_pex_bias_ctrl; bool has_intr_prsnt_sense; @@ -261,6 +293,7 @@ struct tegra_pcie_soc { bool has_gen2; bool force_pca_enable; bool program_uphy; + bool program_ectl_settings; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2058,6 +2091,52 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie) pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); } +static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port) +{ + unsigned long value; + const struct tegra_pcie_soc *soc = port->pcie->soc; + + value = readl(port->base + RP_ECTL_2_R1); + value &= ~RP_ECTL_2_R1_RX_CTLE_1C_MASK; + value |= soc->rp_ectl_2_r1; + writel(value, port->base + RP_ECTL_2_R1); + + value = readl(port->base + RP_ECTL_4_R1); + value &= ~RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK; + value |= soc->rp_ectl_4_r1; + writel(value, port->base + RP_ECTL_4_R1); + + value = readl(port->base + RP_ECTL_5_R1); + value &= ~RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK; + value |= soc->rp_ectl_5_r1; + writel(value, port->base + RP_ECTL_5_R1); + + value = readl(port->base + RP_ECTL_6_R1); + value &= ~RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK; + value |= soc->rp_ectl_6_r1; + writel(value, port->base + RP_ECTL_6_R1); + + value = readl(port->base + RP_ECTL_2_R2); + value &= ~RP_ECTL_2_R2_RX_CTLE_1C_MASK; + value |= soc->rp_ectl_2_r2; + writel(value, port->base + RP_ECTL_2_R2); + + value = readl(port->base + RP_ECTL_4_R2); + value &= ~RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK; + value |= soc->rp_ectl_4_r2; + writel(value, port->base + RP_ECTL_4_R2); + + value = readl(port->base + RP_ECTL_5_R2); + value &= ~RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK; + value |= soc->rp_ectl_5_r2; + writel(value, port->base + RP_ECTL_5_R2); + + value = readl(port->base + RP_ECTL_6_R2); + value &= ~RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK; + value |= soc->rp_ectl_6_r2; + writel(value, port->base + RP_ECTL_6_R2); +} + static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) { unsigned long value; @@ -2125,6 +2204,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; struct tegra_pcie_port *port, *tmp; + const struct tegra_pcie_soc *soc = pcie->soc; tegra_pcie_apply_pad_settings(pcie); list_for_each_entry_safe(port, tmp, &pcie->ports, list) { @@ -2132,6 +2212,8 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) port->index, port->lanes); tegra_pcie_port_enable(port); + if (soc->program_ectl_settings) + tegra_pcie_program_ectl_settings(port); tegra_pcie_enable_rp_features(port); } @@ -2198,6 +2280,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, + .program_ectl_settings = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2214,6 +2297,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, + .program_ectl_settings = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2229,6 +2313,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .has_gen2 = true, .force_pca_enable = false, .program_uphy = true, + .program_ectl_settings = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2237,6 +2322,14 @@ static const struct tegra_pcie_soc tegra210_pcie = { .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, .pads_refclk_cfg0 = 0x90b890b8, + .rp_ectl_2_r1 = 0x0000000f, + .rp_ectl_4_r1 = 0x00670000, + .rp_ectl_5_r1 = 0x55010000, + .rp_ectl_6_r1 = 0x00000001, + .rp_ectl_2_r2 = 0x0000008f, + .rp_ectl_4_r2 = 0x00c70000, + .rp_ectl_5_r2 = 0x55010000, + .rp_ectl_6_r2 = 0x00000001, .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, @@ -2244,6 +2337,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .has_gen2 = true, .force_pca_enable = true, .program_uphy = true, + .program_ectl_settings = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2260,6 +2354,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .has_gen2 = true, .force_pca_enable = false, .program_uphy = false, + .program_ectl_settings = false, }; static const struct of_device_id tegra_pcie_of_match[] = { From patchwork Mon Oct 30 04:18:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831863 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLtl2shSz9t3v for ; Mon, 30 Oct 2017 15:22:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751168AbdJ3EWy (ORCPT ); Mon, 30 Oct 2017 00:22:54 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5565 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750750AbdJ3EWx (ORCPT ); Mon, 30 Oct 2017 00:22:53 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sun, 29 Oct 2017 21:22:24 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:22:59 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 29 Oct 2017 21:22:59 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:20:34 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:20:33 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:20:33 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:20:33 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 06/12] PCI: tegra: Enable opportunistic update FC and ACK Date: Mon, 30 Oct 2017 09:48:57 +0530 Message-ID: <1509337143-25963-7-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch ensures that DL sends pending ACKs and update FC packets when link is idle instead of waiting for timers to expire which improves PCIe bandwidth. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 51b7821646eb..bf615c5e6b78 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -209,7 +209,9 @@ #define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff #define RP_VEND_XP 0x00000f00 -#define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) +#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_CTL1 0xf48 #define RP_VEND_CTL1_ERPT (1 << 13) @@ -2147,6 +2149,16 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) writel(value, port->base + RP_VEND_CTL1); } +static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) +{ + unsigned long value; + + /* Optimal settings to enhance bandwidth */ + value = readl(port->base + RP_VEND_XP); + value |= RP_VEND_XP_OPPORTUNISTIC_ACK; + value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC; + writel(value, port->base + RP_VEND_XP); +} /* * FIXME: If there are no PCIe cards attached, then calling this function * can result in the increase of the bootup time as there are big timeout @@ -2215,6 +2227,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) if (soc->program_ectl_settings) tegra_pcie_program_ectl_settings(port); tegra_pcie_enable_rp_features(port); + tegra_pcie_apply_sw_fixup(port); } /* take the PCIe interface module out of reset */ From patchwork Mon Oct 30 04:18:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831871 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLvM4V1xz9t3v for ; Mon, 30 Oct 2017 15:23:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751304AbdJ3EXZ (ORCPT ); Mon, 30 Oct 2017 00:23:25 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:16086 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751342AbdJ3EXY (ORCPT ); Mon, 30 Oct 2017 00:23:24 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 29 Oct 2017 21:22:34 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:22:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 29 Oct 2017 21:22:53 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:20:46 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:20:46 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:20:46 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 07/12] PCI: tegra: Disable AFI dynamic clock gating Date: Mon, 30 Oct 2017 09:48:58 +0530 Message-ID: <1509337143-25963-8-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org When there are 32 outstanding writes from AFI to memory, the outstanding write counter overflows and indicates that there are "0" outstanding write transactions. This outstanding write counter is used to generate IDLE signal to dynamically gate the AFI clock. When memory controller is under heavy load, its possible that write completions will come back to AFI after long delay and AFI write counter overflows. AFI clock gets gated even when there are outstanding transactions towards memory controller resutling in system hang. Disable dynamic clock gating of AFI clock to avoid system hang. Signed-off-by: Manikanta Maddireddy Reviewed-by: Mikko Perttunen --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index bf615c5e6b78..75b408b32b8b 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -103,8 +103,9 @@ #define AFI_MSI_EN_VEC6 0xa4 #define AFI_MSI_EN_VEC7 0xa8 -#define AFI_CONFIGURATION 0xac -#define AFI_CONFIGURATION_EN_FPCI (1 << 0) +#define AFI_CONFIGURATION 0xac +#define AFI_CONFIGURATION_EN_FPCI (1 << 0) +#define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31) #define AFI_FPCI_ERROR_MASKS 0xb0 @@ -1057,9 +1058,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) } } - /* finally enable PCIe */ + /* Disable AFI dynamic clock gating and enable PCIe */ value = afi_readl(pcie, AFI_CONFIGURATION); - value |= AFI_CONFIGURATION_EN_FPCI; + value |= (AFI_CONFIGURATION_EN_FPCI | + AFI_CONFIGURATION_CLKEN_OVERRIDE); afi_writel(pcie, value, AFI_CONFIGURATION); value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | From patchwork Mon Oct 30 04:18:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831865 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLv75bYnz9t3v for ; Mon, 30 Oct 2017 15:23:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751300AbdJ3EXO (ORCPT ); Mon, 30 Oct 2017 00:23:14 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:14060 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750750AbdJ3EXN (ORCPT ); Mon, 30 Oct 2017 00:23:13 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Sun, 29 Oct 2017 21:22:41 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:22:42 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 29 Oct 2017 21:22:42 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:20:53 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:20:53 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:20:53 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2 Date: Mon, 30 Oct 2017 09:48:59 +0530 Message-ID: <1509337143-25963-9-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Set required bit to have LTSSM wait for DLLP to finish before entering L1 or L2. This avoids truncation of PM messages which results in receiver errors. Signed-off-by: Manikanta Maddireddy Reviewed-by: Mikko Perttunen --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 75b408b32b8b..7f1e34e670d7 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -217,6 +217,9 @@ #define RP_VEND_CTL1 0xf48 #define RP_VEND_CTL1_ERPT (1 << 13) +#define RP_VEND_XP_BIST 0xf4c +#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -2160,6 +2163,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_XP_OPPORTUNISTIC_ACK; value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC; writel(value, port->base + RP_VEND_XP); + + /* LTSSM will wait for DLLP to finish before entering L1 or L2, + * to avoid truncation of PM messages which results in receiver errors + */ + value = readl(port->base + RP_VEND_XP_BIST); + value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; + writel(value, port->base + RP_VEND_XP_BIST); } /* * FIXME: If there are no PCIe cards attached, then calling this function From patchwork Mon Oct 30 04:19:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831867 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLv86m1Mz9t3v for ; Mon, 30 Oct 2017 15:23:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751517AbdJ3EXO (ORCPT ); Mon, 30 Oct 2017 00:23:14 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5598 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751209AbdJ3EXN (ORCPT ); Mon, 30 Oct 2017 00:23:13 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sun, 29 Oct 2017 21:22:44 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:23:19 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 29 Oct 2017 21:23:19 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:20:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:20:59 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:20:59 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 09/12] PCI: tegra: Enable PCIe xclk clock clamping Date: Mon, 30 Oct 2017 09:49:00 +0530 Message-ID: <1509337143-25963-10-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch enables PCIe xlck clock clamping by pad control. Pad control asserts UPHY lane sleep signal when L1 entry signal received from PCIe. UPHY sleep signal assertion is done per lane. Default clamp threshold margin is not enough to assert all UPHY lane sleep signals. Increase the clamp threshold in Tegra124, 132, 210 and 186. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 7f1e34e670d7..3c625ccfa539 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -224,8 +224,14 @@ #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) #define RP_PRIV_MISC 0x00000fe0 -#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) -#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) +#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) +#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK (0x7f << 16) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD (0xf << 16) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE (1 << 23) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK (0x7f << 24) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD (0xf << 24) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE (1 << 31) #define RP_LINK_CONTROL_STATUS 0x00000090 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 @@ -300,6 +306,7 @@ struct tegra_pcie_soc { bool force_pca_enable; bool program_uphy; bool program_ectl_settings; + bool update_clamp_threshold; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2156,6 +2163,7 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) { + const struct tegra_pcie_soc *soc = port->pcie->soc; unsigned long value; /* Optimal settings to enhance bandwidth */ @@ -2170,6 +2178,17 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value = readl(port->base + RP_VEND_XP_BIST); value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; writel(value, port->base + RP_VEND_XP_BIST); + + value = readl(port->base + RP_PRIV_MISC); + value |= (RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE | + RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE); + if (soc->update_clamp_threshold) { + value &= ~(RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK | + RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK); + value |= (RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD | + RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD); + } + writel(value, port->base + RP_PRIV_MISC); } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2306,6 +2325,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .force_pca_enable = false, .program_uphy = true, .program_ectl_settings = false, + .update_clamp_threshold = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2323,6 +2343,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .force_pca_enable = false, .program_uphy = true, .program_ectl_settings = false, + .update_clamp_threshold = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2339,6 +2360,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .force_pca_enable = false, .program_uphy = true, .program_ectl_settings = false, + .update_clamp_threshold = true, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2363,6 +2385,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .force_pca_enable = true, .program_uphy = true, .program_ectl_settings = true, + .update_clamp_threshold = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2380,6 +2403,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .force_pca_enable = false, .program_uphy = false, .program_ectl_settings = false, + .update_clamp_threshold = false, }; static const struct of_device_id tegra_pcie_of_match[] = { From patchwork Mon Oct 30 04:19:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLvN5jb2z9t3v for ; Mon, 30 Oct 2017 15:23:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752071AbdJ3EXY (ORCPT ); Mon, 30 Oct 2017 00:23:24 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:16082 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751302AbdJ3EXX (ORCPT ); Mon, 30 Oct 2017 00:23:23 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 29 Oct 2017 21:22:34 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:22:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 29 Oct 2017 21:22:53 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:21:06 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:21:06 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:21:06 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 10/12] PCI: tegra: Add SW fixup for RAW violations Date: Mon, 30 Oct 2017 09:49:01 +0530 Message-ID: <1509337143-25963-11-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The logic which blocks read requests till AFI gets ACK for all outstanding MC writes does not behave correctly when number of outstanding write becomes more than 32. SW fixup to prevent this issue is to limit outstanding posted writes and tweak updateFC timer threshold. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 3c625ccfa539..d348f487f5d7 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -185,6 +185,13 @@ #define AFI_PEXBIAS_CTRL_0 0x168 +#define RP_PRIV_XP_DL 0x494 +#define RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD (0x1ff << 1) + +#define RP_RX_HDR_LIMIT 0xe00 +#define RP_RX_HDR_LIMIT_PW_MASK (0xff << 8) +#define RP_RX_HDR_LIMIT_PW (0x0e << 8) + #define RP_ECTL_2_R1 0xe84 #define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff @@ -213,6 +220,7 @@ #define RP_VEND_XP_DL_UP (1 << 30) #define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) +#define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) #define RP_VEND_CTL1 0xf48 #define RP_VEND_CTL1_ERPT (1 << 13) @@ -307,6 +315,7 @@ struct tegra_pcie_soc { bool program_uphy; bool program_ectl_settings; bool update_clamp_threshold; + bool RAW_violation_fixup; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2189,6 +2198,22 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD); } writel(value, port->base + RP_PRIV_MISC); + + /* Fixup for read after write violation in T124 & T132 platforms */ + if (soc->RAW_violation_fixup) { + value = readl(port->base + RP_RX_HDR_LIMIT); + value &= ~RP_RX_HDR_LIMIT_PW_MASK; + value |= RP_RX_HDR_LIMIT_PW; + writel(value, port->base + RP_RX_HDR_LIMIT); + + value = readl(port->base + RP_PRIV_XP_DL); + value |= RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD; + writel(value, port->base + RP_PRIV_XP_DL); + + value = readl(port->base + RP_VEND_XP); + value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK; + writel(value, port->base + RP_VEND_XP); + } } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2326,6 +2351,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .program_uphy = true, .program_ectl_settings = false, .update_clamp_threshold = false, + .RAW_violation_fixup = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2344,6 +2370,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .program_uphy = true, .program_ectl_settings = false, .update_clamp_threshold = false, + .RAW_violation_fixup = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2361,6 +2388,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .program_uphy = true, .program_ectl_settings = false, .update_clamp_threshold = true, + .RAW_violation_fixup = true, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2386,6 +2414,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .program_uphy = true, .program_ectl_settings = true, .update_clamp_threshold = true, + .RAW_violation_fixup = false, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2404,6 +2433,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .program_uphy = false, .program_ectl_settings = false, .update_clamp_threshold = false, + .RAW_violation_fixup = false, }; static const struct of_device_id tegra_pcie_of_match[] = { From patchwork Mon Oct 30 04:19:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831875 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLvj4zB0z9t3v for ; Mon, 30 Oct 2017 15:23:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752083AbdJ3EXo (ORCPT ); Mon, 30 Oct 2017 00:23:44 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:14090 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751342AbdJ3EXo (ORCPT ); Mon, 30 Oct 2017 00:23:44 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Sun, 29 Oct 2017 21:23:12 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:23:13 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 29 Oct 2017 21:23:13 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:21:11 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:21:11 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:21:11 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 11/12] PCI: tegra: Increase the deskew retry time Date: Mon, 30 Oct 2017 09:49:02 +0530 Message-ID: <1509337143-25963-12-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some times Gen2 to Gen1 link speed switching fails due to instability in deskew logic on lane0 in Tegra210. Increase the deskew retry time to resolve this issue. Signed-off-by: Manikanta Maddireddy Reviewed-by: Mikko Perttunen --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index d348f487f5d7..afde9bfb867f 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -222,6 +222,10 @@ #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) +#define RP_VEND_CTL0 0xf44 +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12) + #define RP_VEND_CTL1 0xf48 #define RP_VEND_CTL1_ERPT (1 << 13) @@ -316,6 +320,7 @@ struct tegra_pcie_soc { bool program_ectl_settings; bool update_clamp_threshold; bool RAW_violation_fixup; + bool program_deskew_time; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2214,6 +2219,16 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK; writel(value, port->base + RP_VEND_XP); } + + /* Tune deskew retry time to take care of Gen2 -> Gen1 + * link speed change error in corner cases + */ + if (soc->program_deskew_time) { + value = readl(port->base + RP_VEND_CTL0); + value &= ~RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK; + value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH; + writel(value, port->base + RP_VEND_CTL0); + } } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2352,6 +2367,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .program_ectl_settings = false, .update_clamp_threshold = false, .RAW_violation_fixup = false, + .program_deskew_time = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2371,6 +2387,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .program_ectl_settings = false, .update_clamp_threshold = false, .RAW_violation_fixup = false, + .program_deskew_time = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2389,6 +2406,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .program_ectl_settings = false, .update_clamp_threshold = true, .RAW_violation_fixup = true, + .program_deskew_time = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2415,6 +2433,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .program_ectl_settings = true, .update_clamp_threshold = true, .RAW_violation_fixup = false, + .program_deskew_time = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2434,6 +2453,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .program_ectl_settings = false, .update_clamp_threshold = false, .RAW_violation_fixup = false, + .program_deskew_time = false, }; static const struct of_device_id tegra_pcie_of_match[] = { From patchwork Mon Oct 30 04:19:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831869 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLvL3GYMz9t3v for ; Mon, 30 Oct 2017 15:23:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751996AbdJ3EXY (ORCPT ); Mon, 30 Oct 2017 00:23:24 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:16084 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751304AbdJ3EXX (ORCPT ); Mon, 30 Oct 2017 00:23:23 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 29 Oct 2017 21:22:34 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:23:09 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 29 Oct 2017 21:23:09 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:21:19 +0000 Received: from HQMAIL102.nvidia.com (172.18.146.10) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:21:18 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:21:18 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:21:18 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 12/12] PCI: tegra: Update flow control threshold in Tegra210 Date: Mon, 30 Oct 2017 09:49:03 +0530 Message-ID: <1509337143-25963-13-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Recommended update FC threshold in Tegra210 is 0x60 for best performance of x1 link. Setting this to 0x60 provides the best balance between number of UpdateFC and read data sent over the link. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index afde9bfb867f..1adf9332560a 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -221,6 +221,7 @@ #define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) +#define RP_VEND_XP_UPDATE_FC_THRESHOLD_T210 (0x60 << 18) #define RP_VEND_CTL0 0xf44 #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) @@ -321,6 +322,7 @@ struct tegra_pcie_soc { bool update_clamp_threshold; bool RAW_violation_fixup; bool program_deskew_time; + bool updateFC_threshold; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2229,6 +2231,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH; writel(value, port->base + RP_VEND_CTL0); } + + if (soc->updateFC_threshold) { + value = readl(port->base + RP_VEND_XP); + value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK; + value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_T210; + writel(value, port->base + RP_VEND_XP); + } } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2368,6 +2377,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .update_clamp_threshold = false, .RAW_violation_fixup = false, .program_deskew_time = false, + .updateFC_threshold = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2388,6 +2398,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .update_clamp_threshold = false, .RAW_violation_fixup = false, .program_deskew_time = false, + .updateFC_threshold = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2407,6 +2418,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .update_clamp_threshold = true, .RAW_violation_fixup = true, .program_deskew_time = false, + .updateFC_threshold = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2434,6 +2446,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .update_clamp_threshold = true, .RAW_violation_fixup = false, .program_deskew_time = true, + .updateFC_threshold = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2454,6 +2467,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .update_clamp_threshold = false, .RAW_violation_fixup = false, .program_deskew_time = false, + .updateFC_threshold = false, }; static const struct of_device_id tegra_pcie_of_match[] = {