From patchwork Tue May 14 03:37:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 1099203 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4533Kz4bsnz9sBK for ; Tue, 14 May 2019 13:37:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726851AbfENDhk (ORCPT ); Mon, 13 May 2019 23:37:40 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:60003 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726677AbfENDhj (ORCPT ); Mon, 13 May 2019 23:37:39 -0400 X-UUID: 3e8f6e16f38e4db2badf82b5f7f493f0-20190514 X-UUID: 3e8f6e16f38e4db2badf82b5f7f493f0-20190514 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 990929432; Tue, 14 May 2019 11:37:32 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 14 May 2019 11:37:29 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 14 May 2019 11:37:29 +0800 From: Biao Huang To: Jose Abreu CC: Giuseppe Cavallaro , Alexandre Torgue , Maxime Coquelin , Matthias Brugger , , , , , , , , , Subject: [v3, PATCH 1/4] net: stmmac: update rx tail pointer register to fix rx dma hang issue. Date: Tue, 14 May 2019 11:37:23 +0800 Message-ID: <1557805046-306-2-git-send-email-biao.huang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1557805046-306-1-git-send-email-biao.huang@mediatek.com> References: <1557805046-306-1-git-send-email-biao.huang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E088786E60850BAFA2F416078B4746A1156CA15658EC3916A3A3E2ED30BAED4A2000:8 X-MTK: N Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Currently we will not update the receive descriptor tail pointer in stmmac_rx_refill. Rx dma will think no available descriptors and stop once received packets exceed DMA_RX_SIZE, so that the rx only test will fail. Update the receive tail pointer in stmmac_rx_refill to add more descriptors to the rx channel, so packets can be received continually Fixes: 54139cf3bb33 ("net: stmmac: adding multiple buffers for rx") Signed-off-by: Biao Huang --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 97c5e1a..906f2be 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3336,6 +3336,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); } rx_q->dirty_rx = entry; + stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); } /** From patchwork Tue May 14 03:37:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 1099204 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4533L30j8Tz9sBK for ; Tue, 14 May 2019 13:38:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726812AbfENDhk (ORCPT ); Mon, 13 May 2019 23:37:40 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:56571 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726672AbfENDhj (ORCPT ); Mon, 13 May 2019 23:37:39 -0400 X-UUID: 7e7b64bdd5c743cca87edf23b68a1ce2-20190514 X-UUID: 7e7b64bdd5c743cca87edf23b68a1ce2-20190514 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1437643664; Tue, 14 May 2019 11:37:32 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 14 May 2019 11:37:30 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 14 May 2019 11:37:30 +0800 From: Biao Huang To: Jose Abreu CC: Giuseppe Cavallaro , Alexandre Torgue , Maxime Coquelin , Matthias Brugger , , , , , , , , , Subject: [v3, PATCH 2/4] net: stmmac: fix csr_clk can't be zero issue Date: Tue, 14 May 2019 11:37:24 +0800 Message-ID: <1557805046-306-3-git-send-email-biao.huang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1557805046-306-1-git-send-email-biao.huang@mediatek.com> References: <1557805046-306-1-git-send-email-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The specific clk_csr value can be zero, and stmmac_clk is necessary for MDC clock which can be set dynamically. So, change the condition from plat->clk_csr to plat->stmmac_clk to fix clk_csr can't be zero issue. Fixes: cd7201f477b9 ("stmmac: MDC clock dynamically based on the csr clock input") Signed-off-by: Biao Huang --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +++--- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 5 ++++- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 906f2be..a905b63 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4374,10 +4374,10 @@ int stmmac_dvr_probe(struct device *device, * set the MDC clock dynamically according to the csr actual * clock input. */ - if (!priv->plat->clk_csr) - stmmac_clk_csr_set(priv); - else + if (priv->plat->clk_csr >= 0) priv->clk_csr = priv->plat->clk_csr; + else + stmmac_clk_csr_set(priv); stmmac_check_pcs_mode(priv); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 3031f2b..f45bfbe 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -408,7 +408,10 @@ struct plat_stmmacenet_data * /* Default to phy auto-detection */ plat->phy_addr = -1; - /* Get clk_csr from device tree */ + /* Default to get clk_csr from stmmac_clk_crs_set(), + * or get clk_csr from device tree. + */ + plat->clk_csr = -1; of_property_read_u32(np, "clk_csr", &plat->clk_csr); /* "snps,phy-addr" is not a standard property. Mark it as deprecated From patchwork Tue May 14 03:37:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 1099202 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4533Kx5Rt1z9sBV for ; Tue, 14 May 2019 13:37:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726875AbfENDhl (ORCPT ); Mon, 13 May 2019 23:37:41 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:17554 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726715AbfENDhi (ORCPT ); Mon, 13 May 2019 23:37:38 -0400 X-UUID: 5047478a6478490db2ab990ae828ce44-20190514 X-UUID: 5047478a6478490db2ab990ae828ce44-20190514 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2037696403; Tue, 14 May 2019 11:37:32 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 14 May 2019 11:37:31 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 14 May 2019 11:37:31 +0800 From: Biao Huang To: Jose Abreu CC: Giuseppe Cavallaro , Alexandre Torgue , Maxime Coquelin , Matthias Brugger , , , , , , , , , Subject: [v3, PATCH 3/4] net: stmmac: write the modified value back to MTL_OPERATION_MODE Date: Tue, 14 May 2019 11:37:25 +0800 Message-ID: <1557805046-306-4-git-send-email-biao.huang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1557805046-306-1-git-send-email-biao.huang@mediatek.com> References: <1557805046-306-1-git-send-email-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The value of MTL_OPERATION_MODE is modified, and should be write back to the register. Fixes: d0a9c9f9c6d0 ("net: stmmac: configure mtl rx and tx algorithms") Signed-off-by: Biao Huang --- drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c index 7e5d5db..b4bb562 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -192,6 +192,8 @@ static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw, default: break; } + + writel(value, ioaddr + MTL_OPERATION_MODE); } static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw, From patchwork Tue May 14 03:37:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 1099200 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4533Kv1pkqz9sBK for ; Tue, 14 May 2019 13:37:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726898AbfENDhm (ORCPT ); Mon, 13 May 2019 23:37:42 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:24838 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726667AbfENDhl (ORCPT ); Mon, 13 May 2019 23:37:41 -0400 X-UUID: 3c8e7df6f26343faa879a53b2744ee03-20190514 X-UUID: 3c8e7df6f26343faa879a53b2744ee03-20190514 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1346034389; Tue, 14 May 2019 11:37:34 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 14 May 2019 11:37:32 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 14 May 2019 11:37:31 +0800 From: Biao Huang To: Jose Abreu CC: Giuseppe Cavallaro , Alexandre Torgue , Maxime Coquelin , Matthias Brugger , , , , , , , , , Subject: [v3, PATCH 4/4] net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail Date: Tue, 14 May 2019 11:37:26 +0800 Message-ID: <1557805046-306-5-git-send-email-biao.huang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1557805046-306-1-git-send-email-biao.huang@mediatek.com> References: <1557805046-306-1-git-send-email-biao.huang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: F2B365903E93E975129223F92EB2A84756F66B62B388A4727965D843D351ADDA2000:8 X-MTK: N Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org 1. the frequency of csr clock is 66.5MHz, so the csr_clk value should be 0 other than 5. 2. the csr_clk can be got from device tree, so remove initialization here. Fixes: 9992f37e346b ("stmmac: dwmac-mediatek: add support for mt2712") Signed-off-by: Biao Huang --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index bf25629..126b66b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -346,8 +346,6 @@ static int mediatek_dwmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); plat_dat->interface = priv_plat->phy_mode; - /* clk_csr_i = 250-300MHz & MDC = clk_csr_i/124 */ - plat_dat->clk_csr = 5; plat_dat->has_gmac4 = 1; plat_dat->has_gmac = 0; plat_dat->pmt = 0;