From patchwork Thu May 9 08:08:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1097396 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="GA0bAGEL"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4505jW0C6mz9sBr for ; Thu, 9 May 2019 18:14:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726179AbfEIIOh (ORCPT ); Thu, 9 May 2019 04:14:37 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:15130 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725822AbfEIIOh (ORCPT ); Thu, 9 May 2019 04:14:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 09 May 2019 01:14:43 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 09 May 2019 01:14:35 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 09 May 2019 01:14:35 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 9 May 2019 08:14:34 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 9 May 2019 08:14:23 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 9 May 2019 08:14:23 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 09 May 2019 01:09:09 -0700 From: Krishna Yarlagadda To: , , , , , , CC: , , , , , Krishna Yarlagadda Subject: [Patch-V2 1/4] dt-binding: Tegra194 pinctrl support Date: Thu, 9 May 2019 13:38:13 +0530 Message-ID: <1557389296-10257-1-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557389683; bh=sB+iNXK22PqlMOrwAHWKGUHwkQpr8r09L+/nsBMb4Sc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=GA0bAGEL/DAPS78zX5a367cWB8RdvvBw6tWe/9m6LlC9zib6Q24SBDrVMm93RYtIB BYe6kZ9ljbw/36gmgTRWe5R4g2gJKgRAXYmnYImmwsWRMrSBIFrhHE6X2H8Zvtsgbk oDsTmApIIT0rj5ZvR4bYXVtPyWf7/jldKzAJbRpOjmtju/oi+wNXidJe4ETA6YfxGw xhi2Lbu0JJFK4awN/Qk8VBDP8QyQa1FCoqhENDZNg03Kc/9ytl7wB15MUM1dBujcDY FHHb+GG/mBROKlF65R6khL9Ifz9vo/zy4JctqZLqoZDExh0+mzZxvJjHAlAL2kXVHb xYpmKmbu42gBw== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add binding doc for Tegra 194 pinctrl driver Signed-off-by: Krishna Yarlagadda --- Changes in V2: created new binding doc to handle Tegra194 pinctrl driver .../bindings/pinctrl/nvidia,tegra194-pinmux.txt | 116 +++++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt new file mode 100644 index 0000000..80e36c7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt @@ -0,0 +1,116 @@ +NVIDIA Tegra194 pinmux controller + +Required properties: +- compatible: "nvidia,tegra194-pinmux" +- reg: Should contain a list of base address and size pairs for: + - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control) + - second entry: The PINMUX_AUX_* registers (pinmux) + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Tegra's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, tristate, drive strength, etc. + +See the TRM to determine which properties and values apply to each pin/group. +Macro values for property values are defined in +include/dt-binding/pinctrl/pinctrl-tegra.h. + +Required subnode-properties: +- nvidia,pins : An array of strings. Each string contains the name of a pin or + group. Valid values for these names are listed below. + +Optional subnode-properties: +- nvidia,function: A string containing the name of the function to mux to the + pin or group. +- nvidia,pull: Integer, representing the pull-down/up to apply to the pin. + 0: none, 1: down, 2: up. +- nvidia,tristate: Integer. + 0: drive, 1: tristate. +- nvidia,enable-input: Integer. Enable the pin's input path. + enable :TEGRA_PIN_ENABLE and + disable or output only: TEGRA_PIN_DISABLE. +- nvidia,open-drain: Integer. + enable: TEGRA_PIN_ENABLE. + disable: TEGRA_PIN_DISABLE. +- nvidia,lock: Integer. Lock the pin configuration against further changes + until reset. + enable: TEGRA_PIN_ENABLE. + disable: TEGRA_PIN_DISABLE. +- nvidia,io-hv: Integer. Select high-voltage receivers. + normal: TEGRA_PIN_DISABLE + high: TEGRA_PIN_ENABLE +- nvidia,high-speed-mode: Integer. Enable high speed mode the pins. + normal: TEGRA_PIN_DISABLE + high: TEGRA_PIN_ENABLE +- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input. + normal: TEGRA_PIN_DISABLE + high: TEGRA_PIN_ENABLE +- nvidia,drive-type: Integer. Valid range 0...3. +- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest. + The range of valid values depends on the pingroup. See "CAL_DRVDN" in the + Tegra TRM. +- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest. + The range of valid values depends on the pingroup. See "CAL_DRVUP" in the + Tegra TRM. +- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is + fastest. The range of valid values depends on the pingroup. See + "DRVDN_SLWR" in the Tegra TRM. +- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is + fastest. The range of valid values depends on the pingroup. See + "DRVUP_SLWF" in the Tegra TRM. + +Valid values for pin and group names (nvidia,pin) are: + + These correspond to Tegra PADCTL_* (pinmux) registers. + + Mux groups: + + These correspond to Tegra PADCTL_* (pinmux) registers. Any property + that exists in those registers may be set for the following pin names. + + pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1 + + Drive groups: + + These registers controls a single pin for which a mux group exists. + See the list above for the pin name to use when configuring the pinmux. + + pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1 + +Valid values for nvidia,functions are: + + pe5 + +Power Domain: + pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 are part of PCIE C5 power + partition. Client devices must enable this partition before accessing + these pins here. + + +Example: + + tegra_pinctrl: pinmux: pinmux@2430000 { + compatible = "nvidia,tegra194-pinmux"; + reg = <0x2430000 0x17000 + 0xc300000 0x4000>; + + pinctrl-names = "pex_rst"; + pinctrl-0 = <&pex_rst_c5_out_state>; + + pex_rst_c5_out_state: pex_rst_c5_out { + pex_rst { + nvidia,pins = "pex_l5_rst_n_pgg1"; + nvidia,schmitt = ; + nvidia,lpdr = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,tristate = ; + nvidia,pull = ; + }; + }; + }; From patchwork Thu May 9 08:08:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1097395 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="J2BXM12o"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4505jG1Vqvz9sCJ for ; Thu, 9 May 2019 18:14:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725869AbfEIIOX (ORCPT ); Thu, 9 May 2019 04:14:23 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14984 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725822AbfEIIOX (ORCPT ); Thu, 9 May 2019 04:14:23 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 09 May 2019 01:13:46 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 09 May 2019 01:14:22 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 09 May 2019 01:14:22 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 9 May 2019 08:14:21 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 9 May 2019 08:14:22 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 09 May 2019 01:09:21 -0700 From: Krishna Yarlagadda To: , , , , , , CC: , , , , , Krishna Yarlagadda Subject: [Patch-V2 2/4] pinctrl: tegra: Support 32 bit register access Date: Thu, 9 May 2019 13:38:14 +0530 Message-ID: <1557389296-10257-2-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557389296-10257-1-git-send-email-kyarlagadda@nvidia.com> References: <1557389296-10257-1-git-send-email-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557389626; bh=9yMa0MdESN+pqf3yySouNjMJ8Zwp0P/OmYwg+K6jF8I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=J2BXM12oxrdqWYx4UJrlHxPtNvpUtPpxr3TUyCXrbzXhIWEKE6VQwHtY+BxZpRg1O iOSjYcKWOclsg1KZkoxULIOEOG68MtVRWJjsJy/qFhJEVqI/LfD/i+lUMdXdBVmeUw hjQIJsWd1HIPHdNIAedXXSBAmjtA0jEZgJV4occrX+ib+LrUpuFEuEzWEXIUmVdoqC XPGT8sRsdhvb0PfiO1eitzKDF8H4ERbjAq9Qjvsj2j3Z1NEjk+5koW/C1ok+egjLft LZUiTQh3O3o2ayl0kUG4EjGzXJbGr9n01zsYmfbOw/ARGDrfIwnrhRU0cINNQpAmD3 DuIIncJ/YPF8g== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Tegra194 chip has 32 bit pinctrl registers. Existing register defines in header are only 16 bit. Modified common pinctrl-tegra driver to support 32 bit registers of Tegra 194 and later chips. Signed-off-by: Krishna Yarlagadda --- drivers/pinctrl/tegra/pinctrl-tegra.c | 8 ++++---- drivers/pinctrl/tegra/pinctrl-tegra.h | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index a5008c0..76e88c4 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -292,7 +292,7 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, const struct tegra_pingroup *g, enum tegra_pinconf_param param, bool report_err, - s8 *bank, s16 *reg, s8 *bit, s8 *width) + s8 *bank, s32 *reg, s8 *bit, s8 *width) { switch (param) { case TEGRA_PINCONF_PARAM_PULL: @@ -451,7 +451,7 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, const struct tegra_pingroup *g; int ret; s8 bank, bit, width; - s16 reg; + s32 reg; u32 val, mask; g = &pmx->soc->groups[group]; @@ -480,7 +480,7 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, const struct tegra_pingroup *g; int ret, i; s8 bank, bit, width; - s16 reg; + s32 reg; u32 val, mask; g = &pmx->soc->groups[group]; @@ -548,7 +548,7 @@ static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, const struct tegra_pingroup *g; int i, ret; s8 bank, bit, width; - s16 reg; + s32 reg; u32 val; g = &pmx->soc->groups[group]; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 44c7194..82cd947 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -143,10 +143,10 @@ struct tegra_pingroup { const unsigned *pins; u8 npins; u8 funcs[4]; - s16 mux_reg; - s16 pupd_reg; - s16 tri_reg; - s16 drv_reg; + s32 mux_reg; + s32 pupd_reg; + s32 tri_reg; + s32 drv_reg; u32 mux_bank:2; u32 pupd_bank:2; u32 tri_bank:2; From patchwork Thu May 9 08:08:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1097390 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="M3lWK+Hj"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4505bm10q9z9sBV for ; Thu, 9 May 2019 18:09:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725963AbfEIIJf (ORCPT ); Thu, 9 May 2019 04:09:35 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14754 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725822AbfEIIJf (ORCPT ); Thu, 9 May 2019 04:09:35 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 09 May 2019 01:08:56 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 09 May 2019 01:09:32 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 09 May 2019 01:09:32 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 9 May 2019 08:09:31 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 9 May 2019 08:09:31 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 09 May 2019 01:09:31 -0700 From: Krishna Yarlagadda To: , , , , , , CC: , , , , , Krishna Yarlagadda Subject: [Patch-V2 3/4] pinctrl: tegra: Add Tegra194 pinmux driver Date: Thu, 9 May 2019 13:38:15 +0530 Message-ID: <1557389296-10257-3-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557389296-10257-1-git-send-email-kyarlagadda@nvidia.com> References: <1557389296-10257-1-git-send-email-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557389336; bh=I9ztogdgQWxlUbRsIE1w6IFbR6hAxS6MHG5OxI6z/HY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=M3lWK+HjnFEVZ7a4vFZyLmyDGOyDjX54Y9Fh/dJNAeZOFekV4i0XqnRpTobg9CRBa sxfkxQU01GM+LNFrI4OgR/Q42VWYB0AZI5+AkuToZw664OgeLxjyxc5qbC4yir/EMV pMhSiIGehjynufJ+Ji0T8HyhQ9fKTgUR5N7NbKS2DMhHBPpbg3oCdIr4VlIPJVyes+ qziunCkiOrj2LpRKMHtCK/QrsMENR7E8FPiyXIgyGGvAjLkiMW03HQYJ+VIt1NoJNJ hgBrSQNvCh6ejKmlBzi8rw1Paagb+4LtT6PUvr74+eMd8n1a5g0duNwCY+iYgYb6VE 4tAUd6GuafJXg== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Tegra194 has PCIE L5 rst and clkreq pins which need to be controlled dynamically at runtime. This driver supports change pinmux for these pins. Pinmux for rest of the pins is set statically by bootloader and will not be changed by this driver Signed-off-by: Krishna Yarlagadda Signed-off-by: Suresh Mangipudi --- Changes in V2: split V1 patch into 3 patches driver change, updating header to support new driver and select pinmux drier in soc. Remove irrelevant macros. drivers/pinctrl/tegra/Kconfig | 4 + drivers/pinctrl/tegra/Makefile | 1 + drivers/pinctrl/tegra/pinctrl-tegra194.c | 168 +++++++++++++++++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra194.c diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig index 24e20cc..6f79f1f 100644 --- a/drivers/pinctrl/tegra/Kconfig +++ b/drivers/pinctrl/tegra/Kconfig @@ -23,6 +23,10 @@ config PINCTRL_TEGRA210 bool select PINCTRL_TEGRA +config PINCTRL_TEGRA194 + bool + select PINCTRL_TEGRA + config PINCTRL_TEGRA_XUSB def_bool y if ARCH_TEGRA select GENERIC_PHY diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile index bbcb043..ead4e10 100644 --- a/drivers/pinctrl/tegra/Makefile +++ b/drivers/pinctrl/tegra/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o +obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c new file mode 100644 index 0000000..399598a --- /dev/null +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Pinctrl data for the NVIDIA Tegra194 pinmux + * + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include + +/* Define unique ID for each pins */ +enum pin_id { + TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256, + TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257, + TEGRA_PIN_NUM_GPIOS = 258, +}; + +/* Table for pin descriptor */ +static const struct pinctrl_pin_desc tegra194_pins[] = { + PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, + "TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"), + PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, + "TEGRA_PIN_PEX_L5_RST_N_PGG1"), +}; + +static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = { + TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, +}; + +static const unsigned int pex_l5_rst_n_pgg1_pins[] = { + TEGRA_PIN_PEX_L5_RST_N_PGG1, +}; + +/* Define unique ID for each function */ +enum tegra_mux_dt { + TEGRA_MUX_RSVD0, + TEGRA_MUX_RSVD1, + TEGRA_MUX_RSVD2, + TEGRA_MUX_RSVD3, + TEGRA_MUX_PE5, +}; + +/* Make list of each function name */ +#define TEGRA_PIN_FUNCTION(lid) \ + { \ + .name = #lid, \ + } +static struct tegra_function tegra194_functions[] = { + TEGRA_PIN_FUNCTION(rsvd0), + TEGRA_PIN_FUNCTION(rsvd1), + TEGRA_PIN_FUNCTION(rsvd2), + TEGRA_PIN_FUNCTION(rsvd3), + TEGRA_PIN_FUNCTION(pe5), +}; + +#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \ + drvup_w, slwr_b, slwr_w, slwf_b, \ + slwf_w, bank) \ + .drv_reg = DRV_PINGROUP_Y(r), \ + .drv_bank = bank, \ + .drvdn_bit = drvdn_b, \ + .drvdn_width = drvdn_w, \ + .drvup_bit = drvup_b, \ + .drvup_width = drvup_w, \ + .slwr_bit = slwr_b, \ + .slwr_width = slwr_w, \ + .slwf_bit = slwf_b, \ + .slwf_width = slwf_w + +#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, e_input, \ + e_od, schmitt_b, drvtype) \ + .mux_reg = ((r)), \ + .lpmd_bit = -1, \ + .lock_bit = -1, \ + .hsm_bit = -1, \ + .parked_bit = -1, \ + .mux_bank = bank, \ + .mux_bit = 0, \ + .pupd_reg = PINGROUP_REG_##pupd(r), \ + .pupd_bank = bank, \ + .pupd_bit = 2, \ + .tri_reg = ((r)), \ + .tri_bank = bank, \ + .tri_bit = 4, \ + .einput_bit = e_input, \ + .odrain_bit = e_od, \ + .schmitt_bit = schmitt_b, \ + .drvtype_bit = 13, \ + .drv_reg = -1 + +#define drive_pex_l5_clkreq_n_pgg0 \ + DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_l5_rst_n_pgg1 \ + DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0) + +#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk, \ + e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .funcs = { \ + TEGRA_MUX_##f0, \ + TEGRA_MUX_##f1, \ + TEGRA_MUX_##f2, \ + TEGRA_MUX_##f3, \ + }, \ + PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, \ + e_input, e_od, \ + schmitt_b, drvtype), \ + drive_##pg_name, \ + } + +static const struct tegra_pingroup tegra194_groups[] = { + PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, + Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"), + PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, + Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"), +}; + +static const struct tegra_pinctrl_soc_data tegra194_pinctrl = { + .ngpios = TEGRA_PIN_NUM_GPIOS, + .pins = tegra194_pins, + .npins = ARRAY_SIZE(tegra194_pins), + .functions = tegra194_functions, + .nfunctions = ARRAY_SIZE(tegra194_functions), + .groups = tegra194_groups, + .ngroups = ARRAY_SIZE(tegra194_groups), + .hsm_in_mux = true, + .schmitt_in_mux = true, + .drvtype_in_mux = true, +}; + +static int tegra194_pinctrl_probe(struct platform_device *pdev) +{ + return tegra_pinctrl_probe(pdev, &tegra194_pinctrl); +} + +static const struct of_device_id tegra194_pinctrl_of_match[] = { + { .compatible = "nvidia,tegra194-pinmux", }, + { }, +}; + +static struct platform_driver tegra194_pinctrl_driver = { + .driver = { + .name = "tegra194-pinctrl", + .of_match_table = tegra194_pinctrl_of_match, + }, + .probe = tegra194_pinctrl_probe, +}; + +static int __init tegra194_pinctrl_init(void) +{ + return platform_driver_register(&tegra194_pinctrl_driver); +} +arch_initcall(tegra194_pinctrl_init); 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Thu, 09 May 2019 01:09:39 -0700 From: Krishna Yarlagadda To: , , , , , , CC: , , , , , Krishna Yarlagadda Subject: [Patch-V2 4/4] soc/tegra: select pinctrl for Tegra194 Date: Thu, 9 May 2019 13:38:16 +0530 Message-ID: <1557389296-10257-4-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557389296-10257-1-git-send-email-kyarlagadda@nvidia.com> References: <1557389296-10257-1-git-send-email-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557389344; bh=vZPeMulyG2M0BcsrWsBCmVEo9iVP+aStJoSJsHmSI2c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=mwp57xtWIpxNBSQE8ikeX1AHF7uCddS8NC+nbAirV61E/j27vdK3zhHBgozbwztLi gdaJ8QLKEtJlJdhmbtGRkr55FKXhLbwJPa9VvpqcCv2ruCS/klLAQ0NehgwNaB4Q+N MVqBaItfyCA5+aSxLpx44nu5AUuFc5XgdXLzEfkVQ5RPLA02vLDsX+RW9N9tKwmHJT dFvMHwyuaCwkE2oRqIKnpSYaomyaWB0qUwm6QOdoWPcZNpjCCFVaaCSuAh0Jjkrro5 R+PwxJHaucAg0s+po+pXRddC/yE0/Z5SLxIE0dDzyj8Gl4QnvdiJtBZs2Nab9uL9Hk 6NSmco929F2Aw== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Select PINCTRL_TEGRA194 by default for Tegra194 SOC needed for dynamically controlling PCIe pins Signed-off-by: Krishna Yarlagadda --- drivers/soc/tegra/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index a0b0344..6f0df55 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -108,6 +108,7 @@ config ARCH_TEGRA_186_SOC config ARCH_TEGRA_194_SOC bool "NVIDIA Tegra194 SoC" select MAILBOX + select PINCTRL_TEGRA194 select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC