From patchwork Sun May 5 16:24:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1095494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="U2+OuuUO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44xrp163nQz9sB8 for ; Mon, 6 May 2019 02:25:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727940AbfEEQZT (ORCPT ); Sun, 5 May 2019 12:25:19 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:44952 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727825AbfEEQZR (ORCPT ); Sun, 5 May 2019 12:25:17 -0400 Received: by mail-lj1-f196.google.com with SMTP id c6so3656304lji.11; Sun, 05 May 2019 09:25:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Ed1+Ug4ZkhEgqg4yLYkOxWrNtJBdRgQSanrCzVExY8=; b=U2+OuuUOtYl6RwL9uGv6wsWQ/WcV2MZQS9RLwQ1GDseswwrTNWTQ1uw+JzeomNP73n LP1TpKYt5d+9XM20J8uEiag2zVc4clK45ecSG0mU2ebK9lcG5H0nxK/R+4yapnO/lCx5 QFoAGDV/pN8rJAWs+YCbie09XndCsafqho9l3274PQGvtWXnTCT95GadVYRlsoxRnJBL JNCE4izUPpMBaZRbIy5xwkfLeJsWZo8wrdXsALFFBZoiE6MSJdQQ+1S86my0JwICBt/F vIE9+Nk9l3SMM1UidceqtvOBx3Z2kdtpmtHuAfBGMTjwx8VOcm8WkrBFKUQHyoIcadj6 mqVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Ed1+Ug4ZkhEgqg4yLYkOxWrNtJBdRgQSanrCzVExY8=; b=Cocdwk8AIG5g68zLeOR/lR7QOfH8qXla1fLLE30drI/uorHxv3B07br1TYJHGT18CE zzxcYLTZ5kAAho38Vpmze5b+ZENTClajSpTrQuEon8RVMZiygq5/gCW4+LtJXGV7HOhk pS7x1FlylJmjUdtvuY3nn1tRESghj5kGAWhH2B9V7vprCrsDxmKwqqR5LiOSKLfYOOo7 0tpm5zLwUrZuBlpjIy6+2//VO0vtw+9e1yXtBejb+G8D4LAOBcbsaeQfZrtvdWZbkOSJ 34zq1pR+5VnjQ0M0z0rlBUlrq/wjdVcaLOC3kQV36gBwsvsLJj9YrmVe1cVuPputxC+r FsiA== X-Gm-Message-State: APjAAAX5PzVv9UFOR9XpEi/Wg0Oi4MbhKV/nVO2fEL1oFt/CRAcrIjZe UX1e3/c+H3z+7zKiXmeOYk0= X-Google-Smtp-Source: APXvYqyvXKY7d6yTX+XHrZGD3cJbqyoz84YfPcX4rbgh6cgV8Novi5bOekmjy7CVP7sPuVSshdfwYg== X-Received: by 2002:a2e:b1ce:: with SMTP id e14mr7854106lja.143.1557073515287; Sun, 05 May 2019 09:25:15 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-35-107.pppoe.spdop.ru. [94.29.35.107]) by smtp.gmail.com with ESMTPSA id g13sm1581649lfh.49.2019.05.05.09.25.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 May 2019 09:25:14 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Thomas Gleixner , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/7] clocksource/drivers/tegra: Support per-CPU timers on all Tegra's Date: Sun, 5 May 2019 19:24:30 +0300 Message-Id: <20190505162436.23125-2-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190505162436.23125-1-digetx@gmail.com> References: <20190505162436.23125-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Assign TMR1-4 per-CPU core on 32bit Tegra's in a way it is done for Tegra210. In a result each core can handle its own timer events, less code is unique to ARM64 and Tegra's clock events driver now has higher rating on all Tegra's, replacing the ARM's TWD timer which isn't very accurate due to the clock rate jitter caused by CPU frequency scaling. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 120 ++++++++++------------------ 1 file changed, 43 insertions(+), 77 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 919b3568c495..58e8bb6deac9 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -49,13 +49,18 @@ #define TIMER_PCR_INTR_CLR BIT(30) #ifdef CONFIG_ARM -#define TIMER_CPU0 0x50 /* TIMER3 */ +#define TIMER_CPU0 0x00 /* TIMER1 */ +#define TIMER_CPU2 0x50 /* TIMER3 */ +#define TIMER1_IRQ_IDX 0 +#define IRQ_IDX_FOR_CPU(cpu) (TIMER1_IRQ_IDX + cpu) +#define TIMER_BASE_FOR_CPU(cpu) \ + (((cpu) & 1) * 8 + ((cpu) < 2 ? TIMER_CPU0 : TIMER_CPU2)) #else #define TIMER_CPU0 0x90 /* TIMER10 */ #define TIMER10_IRQ_IDX 10 #define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) -#endif #define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) +#endif static u32 usec_config; static void __iomem *timer_reg_base; @@ -118,7 +123,6 @@ static void tegra_timer_resume(struct clock_event_device *evt) writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); } -#ifdef CONFIG_ARM64 static DEFINE_PER_CPU(struct timer_of, tegra_to) = { .flags = TIMER_OF_CLOCK | TIMER_OF_BASE, @@ -159,33 +163,8 @@ static int tegra_timer_stop(unsigned int cpu) return 0; } -#else /* CONFIG_ARM */ -static struct timer_of tegra_to = { - .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ, - - .clkevt = { - .name = "tegra_timer", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_DYNIRQ, - .set_next_event = tegra_timer_set_next_event, - .set_state_shutdown = tegra_timer_shutdown, - .set_state_periodic = tegra_timer_set_periodic, - .set_state_oneshot = tegra_timer_shutdown, - .tick_resume = tegra_timer_shutdown, - .suspend = tegra_timer_suspend, - .resume = tegra_timer_resume, - .cpumask = cpu_possible_mask, - }, - - .of_irq = { - .index = 2, - .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, - .handler = tegra_timer_isr, - }, -}; +#ifdef CONFIG_ARM static u64 notrace tegra_read_sched_clock(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); @@ -222,10 +201,12 @@ static struct clocksource suspend_rtc_clocksource = { }; #endif -static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) +static int tegra_init_timer(struct device_node *np, bool tegra20) { - int ret = 0; + struct timer_of *to; + int cpu, ret; + to = this_cpu_ptr(&tegra_to); ret = timer_of_init(np, to); if (ret < 0) goto out; @@ -267,29 +248,19 @@ static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) goto out; } - writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG); - -out: - return ret; -} - -#ifdef CONFIG_ARM64 -static int __init tegra_init_timer(struct device_node *np) -{ - int cpu, ret = 0; - struct timer_of *to; - - to = this_cpu_ptr(&tegra_to); - ret = tegra_timer_common_init(np, to); - if (ret < 0) - goto out; + writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); for_each_possible_cpu(cpu) { - struct timer_of *cpu_to; + struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); + + /* + * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the + * parent clock. + */ + if (tegra20) + cpu_to->of_clk.rate = 1000000; - cpu_to = per_cpu_ptr(&tegra_to, cpu); cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu); - cpu_to->of_clk.rate = timer_of_rate(to); cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); @@ -331,43 +302,39 @@ static int __init tegra_init_timer(struct device_node *np) timer_of_cleanup(to); return ret; } + +#ifdef CONFIG_ARM64 +static int __init tegra210_init_timer(struct device_node *np) +{ + return tegra_init_timer(np, false); +} +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); #else /* CONFIG_ARM */ -static int __init tegra_init_timer(struct device_node *np) +static int __init tegra20_init_timer(struct device_node *np) { - int ret = 0; + struct timer_of *to; + int err; - ret = tegra_timer_common_init(np, &tegra_to); - if (ret < 0) - goto out; + err = tegra_init_timer(np, true); + if (err) + return err; - tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0); - tegra_to.of_clk.rate = 1000000; /* microsecond timer */ + to = this_cpu_ptr(&tegra_to); sched_clock_register(tegra_read_sched_clock, 32, - timer_of_rate(&tegra_to)); - ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", timer_of_rate(&tegra_to), + timer_of_rate(to)); + err = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", timer_of_rate(to), 300, 32, clocksource_mmio_readl_up); - if (ret) { - pr_err("Failed to register clocksource\n"); - goto out; - } + if (err) + pr_err("Failed to register clocksource: %d\n", err); tegra_delay_timer.read_current_timer = tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = timer_of_rate(&tegra_to); + tegra_delay_timer.freq = timer_of_rate(to); register_current_timer_delay(&tegra_delay_timer); - clockevents_config_and_register(&tegra_to.clkevt, - timer_of_rate(&tegra_to), - 0x1, - 0x1fffffff); - - return ret; -out: - timer_of_cleanup(&tegra_to); - - return ret; + return 0; } static int __init tegra20_init_rtc(struct device_node *np) @@ -383,6 +350,5 @@ static int __init tegra20_init_rtc(struct device_node *np) return 0; } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); #endif -TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer); -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer); From patchwork Sun May 5 16:24:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1095496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="C8YdTckI"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44xrpD3sPGz9s55 for ; Mon, 6 May 2019 02:25:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727772AbfEEQZu (ORCPT ); Sun, 5 May 2019 12:25:50 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:36145 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727593AbfEEQZS (ORCPT ); Sun, 5 May 2019 12:25:18 -0400 Received: by mail-lf1-f65.google.com with SMTP id y10so805046lfl.3; Sun, 05 May 2019 09:25:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=us/x2se0nJ0UbyATJJBtJCUasmh/3ZYo6D/IH6DvFKs=; b=C8YdTckIMGx2Kp80Ysqqq4gCdinvdMjg79t878XH6PRXYvLpTjDzGilTXSZCRZ5Uke EaOcHFYSSs8SrGzJzZA81jhNLRaislaSxVRbMGzlujZmVCBSu+782iL6/kKRrIseZd/8 3i+3HBWhocYFadOKPfzvT3rl7gvqNbHPO1skqEwadvG38+lCuw5Vc4ZS4hoG4AufqLaM b8/AOtgnoYXMgbGnKgCDF3FdiD38wMmyruZgqcR0X2jUYLwSGS/j8AV2q/FMANa7KO5z GSJ9bvexrN4XE9fhytHUulRirotjH8t/vc+cdjGgO/wfLAEyElXO64g9bBGT3SManz5V AcJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=us/x2se0nJ0UbyATJJBtJCUasmh/3ZYo6D/IH6DvFKs=; b=twhpT/SW50epjJChDUbiZgdunMXiLK94VKXdQo+w0XxDxcsYdH5c8LjrEaoQpHa/GE uHhTRSqwiJObd7E/3Y2iVoQKJzI6KqLNJqPhauJC2KwM9Ane9d3q6QSzOFUTfEv7ImF2 3dH6elGU0unn480CUoLLK8bVXFO44elRd9lHw6a5OgMSa9AlgbD7mpkJ90FS7p44aa2l nRN0N/yeTYz/KNYESHv4Tlhx+YUlaRjL68m8ckYeaPOV4zNwDfSSrbvAi8XyvJKoVkhv zvYLxKDPC0T2/PuhUzmM80jQ69OHDLvHVD51Ke8wqqeWYoQz97DWfECQ4vYHwKbstO9Q Ysnw== X-Gm-Message-State: APjAAAV03Pzojb7+aNlh/0zxepnBteCOoqij0G9V1mzpBGPdoyI/Nsri qLvPeqa9A9ZWypyZnF/V9s4= X-Google-Smtp-Source: APXvYqxDZ/uOSYlChjralukCgYUxPm+LHcUmjyXbx0h8gfnjCyGz1iCMi5vXulJa0F3NeqIoszDnRw== X-Received: by 2002:ac2:5446:: with SMTP id d6mr90429lfn.47.1557073516362; Sun, 05 May 2019 09:25:16 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-35-107.pppoe.spdop.ru. [94.29.35.107]) by smtp.gmail.com with ESMTPSA id g13sm1581649lfh.49.2019.05.05.09.25.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 May 2019 09:25:15 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Thomas Gleixner , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/7] clocksource/drivers/tegra: Unify timer code Date: Sun, 5 May 2019 19:24:31 +0300 Message-Id: <20190505162436.23125-3-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190505162436.23125-1-digetx@gmail.com> References: <20190505162436.23125-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra132 is 64bit platform and it has the tegra20-timer hardware unit. Right now the corresponding timer code isn't compiled for ARM64, remove ifdef'iness from the code and compile tegra20-timer for both 32 and 64 bit platforms. Also note that like the older generations, Tegra210 has the microseconds counter. Hence the delay timer and timer_us clocksource are now made available for Tegra210 as well. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 107 +++++++++++++++------------- 1 file changed, 56 insertions(+), 51 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 58e8bb6deac9..42a19a4019a9 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -30,10 +30,6 @@ #include "timer-of.h" -#ifdef CONFIG_ARM -#include -#endif - #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c #define RTC_MILLISECONDS 0x10 @@ -48,25 +44,17 @@ #define TIMER_PCR 0x4 #define TIMER_PCR_INTR_CLR BIT(30) -#ifdef CONFIG_ARM -#define TIMER_CPU0 0x00 /* TIMER1 */ -#define TIMER_CPU2 0x50 /* TIMER3 */ +#define TIMER1_BASE 0x00 +#define TIMER2_BASE 0x08 +#define TIMER3_BASE 0x50 +#define TIMER4_BASE 0x58 +#define TIMER10_BASE 0x90 + #define TIMER1_IRQ_IDX 0 -#define IRQ_IDX_FOR_CPU(cpu) (TIMER1_IRQ_IDX + cpu) -#define TIMER_BASE_FOR_CPU(cpu) \ - (((cpu) & 1) * 8 + ((cpu) < 2 ? TIMER_CPU0 : TIMER_CPU2)) -#else -#define TIMER_CPU0 0x90 /* TIMER10 */ #define TIMER10_IRQ_IDX 10 -#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) -#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) -#endif static u32 usec_config; static void __iomem *timer_reg_base; -#ifdef CONFIG_ARM -static struct delay_timer tegra_delay_timer; -#endif static int tegra_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) @@ -164,7 +152,6 @@ static int tegra_timer_stop(unsigned int cpu) return 0; } -#ifdef CONFIG_ARM static u64 notrace tegra_read_sched_clock(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); @@ -175,6 +162,11 @@ static unsigned long tegra_delay_timer_read_counter_long(void) return readl(timer_reg_base + TIMERUS_CNTR_1US); } +static struct delay_timer tegra_delay_timer = { + .read_current_timer = tegra_delay_timer_read_counter_long, + .freq = 1000000, +}; + static struct timer_of suspend_rtc_to = { .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, }; @@ -199,9 +191,34 @@ static struct clocksource suspend_rtc_clocksource = { .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, }; -#endif -static int tegra_init_timer(struct device_node *np, bool tegra20) +static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20) +{ + if (tegra20) { + switch (cpu) { + case 0: + return TIMER1_BASE; + case 1: + return TIMER2_BASE; + case 2: + return TIMER3_BASE; + default: + return TIMER4_BASE; + } + } + + return TIMER10_BASE + cpu * 8; +} + +static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) +{ + if (tegra20) + return TIMER1_IRQ_IDX + cpu; + + return TIMER10_IRQ_IDX + cpu; +} + +static int __init tegra_init_timer(struct device_node *np, bool tegra20) { struct timer_of *to; int cpu, ret; @@ -252,6 +269,8 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); + unsigned int base = tegra_base_for_cpu(cpu, tegra20); + unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20); /* * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the @@ -260,10 +279,10 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) if (tegra20) cpu_to->of_clk.rate = 1000000; - cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu); + cpu_to = per_cpu_ptr(&tegra_to, cpu); + cpu_to->of_base.base = timer_reg_base + base; cpu_to->clkevt.cpumask = cpumask_of(cpu); - cpu_to->clkevt.irq = - irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); + cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { pr_err("%s: can't map IRQ for CPU%d\n", __func__, cpu); @@ -283,6 +302,16 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) } } + sched_clock_register(tegra_read_sched_clock, 32, 1000000); + + ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", 1000000, + 300, 32, clocksource_mmio_readl_up); + if (ret) + pr_err("failed to register clocksource: %d\n", ret); + + register_current_timer_delay(&tegra_delay_timer); + cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, tegra_timer_stop); @@ -303,39 +332,17 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) return ret; } -#ifdef CONFIG_ARM64 static int __init tegra210_init_timer(struct device_node *np) { return tegra_init_timer(np, false); } TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); -#else /* CONFIG_ARM */ + static int __init tegra20_init_timer(struct device_node *np) { - struct timer_of *to; - int err; - - err = tegra_init_timer(np, true); - if (err) - return err; - - to = this_cpu_ptr(&tegra_to); - - sched_clock_register(tegra_read_sched_clock, 32, - timer_of_rate(to)); - err = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", timer_of_rate(to), - 300, 32, clocksource_mmio_readl_up); - if (err) - pr_err("Failed to register clocksource: %d\n", err); - - tegra_delay_timer.read_current_timer = - tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = timer_of_rate(to); - register_current_timer_delay(&tegra_delay_timer); - - return 0; + return tegra_init_timer(np, true); } +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); static int __init tegra20_init_rtc(struct device_node *np) { @@ -350,5 +357,3 @@ static int __init tegra20_init_rtc(struct device_node *np) return 0; } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); -#endif From patchwork Sun May 5 16:24:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1095495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UCBo8b5K"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44xrp62FDsz9sB8 for ; Mon, 6 May 2019 02:25:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727479AbfEEQZo (ORCPT ); Sun, 5 May 2019 12:25:44 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:40968 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727925AbfEEQZT (ORCPT ); Sun, 5 May 2019 12:25:19 -0400 Received: by mail-lj1-f194.google.com with SMTP id k8so9068578lja.8; Sun, 05 May 2019 09:25:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EyUdd7HrC5y8waWKk3rsytQ58W6hY1rOklTf7qr80Ss=; b=UCBo8b5Kwr9Gc/6O1fuWHNgYRS+5wDY07hS63Ww/AXqaPoMlszvPymYiIBi+hpClIt arCfRKGCY8Wi0WCmtrDTr92u3R0OyfSL0OUcs6BS7uOOmifN9QmSRtsW6AfG+PGgV5yj 8cnq2JaHecyMTdWVlfgZoiEKiZLVvFD8pLx0WypYLAyWC1bIMbV6N7ClTwk5pws2jrqU v7VqFDDECw+fmwDzj5O2fjmYOyHi7DpjDfJDhmK2L05qm+XYFWTY/fl+4sbfh4BGxTEB T2jd3iDqojSHGQKMrVXx4Okft9vaFlCtJ9lqqFIP30lZLTzOHYMIzjG249mit6DiW1/6 4unA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EyUdd7HrC5y8waWKk3rsytQ58W6hY1rOklTf7qr80Ss=; b=YFcbNvpFjM2jGtdpMn9KKDHkhmOS6SF5DCdpuc13J671bqgSvfEAxgjdSNZ0ld9cbR qr1K3G+CBDKlJ2YjGlwyyBA85UN9TFpjn6dYb1y/UkecpleFMg7mNIPIyba3wCz4IyBD 2e7BkAare9rL2RBTTOc73xbJWVbpRlQx0YuIMujfT/0hSFwUTTu4GIjHyt95cgO4JTEJ 2TmZJhcadxmgC83Za0aG8tAftnhKhlPV2Ph8Pp4xpe3IfnCCc2HAAsIiOS0yMBopYHEN TvVOZMg883uCPS4N25aiJ3Z5jDxANUIGsgSsnydMhpJquTSUjYffOOhoJG5YTNafeUA3 bj6Q== X-Gm-Message-State: APjAAAX4bDk3rW/bmHFwwB2cszAuo3VcLHm5eTmoqnsOjGETYtRra4Ad 5pCiSRltooaxt3CQQHLn2tc= X-Google-Smtp-Source: APXvYqx8xQxdH7ASIRU5U2MpdvZfWv/HHfTehI51Dpom1W6PVz9eizPm7oMhKbj0IrCNzgg50dXupA== X-Received: by 2002:a2e:9049:: with SMTP id n9mr471574ljg.168.1557073517451; Sun, 05 May 2019 09:25:17 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-35-107.pppoe.spdop.ru. [94.29.35.107]) by smtp.gmail.com with ESMTPSA id g13sm1581649lfh.49.2019.05.05.09.25.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 May 2019 09:25:16 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Thomas Gleixner , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/7] clocksource/drivers/tegra: Reset hardware state on init Date: Sun, 5 May 2019 19:24:32 +0300 Message-Id: <20190505162436.23125-4-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190505162436.23125-1-digetx@gmail.com> References: <20190505162436.23125-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Reset timer's hardware state to ensure that initially it is in a predictable state. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 42a19a4019a9..b7d1e6221348 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -132,6 +132,9 @@ static int tegra_timer_setup(unsigned int cpu) { struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + writel(0, timer_of_base(to) + TIMER_PTV); + writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); + irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); From patchwork Sun May 5 16:24:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1095492 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VmVCSieg"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44xrnv45bzz9sDn for ; Mon, 6 May 2019 02:25:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727978AbfEEQZX (ORCPT ); Sun, 5 May 2019 12:25:23 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:40313 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727948AbfEEQZV (ORCPT ); Sun, 5 May 2019 12:25:21 -0400 Received: by mail-lf1-f66.google.com with SMTP id o16so7474078lfl.7; Sun, 05 May 2019 09:25:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tpVUDO2/ycyiz3ZOTdaeI/ZMXDWP2S2W90SegzHFcO8=; b=VmVCSiegqnIvXiAI4WM1o2MZiEJPN/N1sT8uPw8uwB7Z4vN9ixZyV7fo0QC4qBNHbh S0IDiA8kd+3epvuuBCqN+yVI5cdjial4zOvUa9LvA56Fa7CzryIbxQmFMIloDtBL+VJO /pgvY91U25IB7/jP/OgbxSpgVcabKHP6QtK7sDqK3glPSjuty1n8zfeHRAb7TELRIsoW V7PZGxUWWZmRktDKGJzdHdWhh/5uG3+5/G1lHcGgSgADMhE5KcZuRF/HfN1QAZrmxm7u f+jO9gLgI0aIUCWm8UfKnRMUBWcul7MCxwx//gO6uko68U155McuqSOoIXu3SOC0YtO7 7SPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tpVUDO2/ycyiz3ZOTdaeI/ZMXDWP2S2W90SegzHFcO8=; b=hA5df0hvCBSPXdD+/HKZdqMWjdYEc0f3Ur91a6OIBUH+6V7GmlP6MUr2QtxlDms+VG zF+E4LJdgs62HXZowHiqBfLrHWZheq1T33Q+cwQgVEfnbiFSEmbeZ9XDi7Cy7pMtms0m h99XJXNo2HITZm1A1BbtYQ9O9E/2CKQ269o4O/Mg5SngMrb+tjg1/qrB6LMt6q0EZXUb T12iil4CwNMB8fHJCZ4VBRoe/WTXvmMC3LezXDHKGj5PyCO6f3wBO0png/IRVmq/eVyk buL3WUwbtPCkBX87men+dB9OHnZrpVS3jK0slQJTmYe5HWy+ZFUE8RlRspwle9n9uuOU Z9Aw== X-Gm-Message-State: APjAAAXNPUKEx2hOQRW/EWJ+sUnGasJ892uQAF550jCykX6VNNikzOl2 KhYcJIlC3YrQBjY5kfVNLTk= X-Google-Smtp-Source: APXvYqyFaztz0dPZl6u0LakoFfmXFJxX+bdXVZi2WhWXStJtrUWogOOakTJ1OT9ODqgs9LBHlccj8A== X-Received: by 2002:a19:7d42:: with SMTP id y63mr10566126lfc.92.1557073518482; Sun, 05 May 2019 09:25:18 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-35-107.pppoe.spdop.ru. [94.29.35.107]) by smtp.gmail.com with ESMTPSA id g13sm1581649lfh.49.2019.05.05.09.25.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 May 2019 09:25:17 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Thomas Gleixner , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/7] clocksource/drivers/tegra: Replace readl/writel with relaxed versions Date: Sun, 5 May 2019 19:24:33 +0300 Message-Id: <20190505162436.23125-5-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190505162436.23125-1-digetx@gmail.com> References: <20190505162436.23125-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The readl/writel functions are inserting memory barrier to ensure that outstanding memory writes are completed, this results in L2 cache syncing being done on Tegra20 and Tegra30 which isn't a very cheap operation. Replace all readl/writel occurrences in the code with the relaxed versions since there is no need for the memory-access syncing. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 35 +++++++++++++++-------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index b7d1e6221348..cdac9e240714 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -61,9 +61,9 @@ static int tegra_timer_set_next_event(unsigned long cycles, { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PTV_EN | - ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ - reg_base + TIMER_PTV); + writel_relaxed(TIMER_PTV_EN | + ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ + reg_base + TIMER_PTV); return 0; } @@ -72,7 +72,7 @@ static int tegra_timer_shutdown(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(0, reg_base + TIMER_PTV); + writel_relaxed(0, reg_base + TIMER_PTV); return 0; } @@ -81,9 +81,9 @@ static int tegra_timer_set_periodic(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PTV_EN | TIMER_PTV_PER | - ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), - reg_base + TIMER_PTV); + writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | + ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), + reg_base + TIMER_PTV); return 0; } @@ -93,7 +93,7 @@ static irqreturn_t tegra_timer_isr(int irq, void *dev_id) struct clock_event_device *evt = (struct clock_event_device *)dev_id; void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); evt->event_handler(evt); return IRQ_HANDLED; @@ -103,12 +103,12 @@ static void tegra_timer_suspend(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); } static void tegra_timer_resume(struct clock_event_device *evt) { - writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); + writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); } static DEFINE_PER_CPU(struct timer_of, tegra_to) = { @@ -132,8 +132,8 @@ static int tegra_timer_setup(unsigned int cpu) { struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); - writel(0, timer_of_base(to) + TIMER_PTV); - writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); + writel_relaxed(0, timer_of_base(to) + TIMER_PTV); + writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); @@ -157,12 +157,12 @@ static int tegra_timer_stop(unsigned int cpu) static u64 notrace tegra_read_sched_clock(void) { - return readl(timer_reg_base + TIMERUS_CNTR_1US); + return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); } static unsigned long tegra_delay_timer_read_counter_long(void) { - return readl(timer_reg_base + TIMERUS_CNTR_1US); + return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); } static struct delay_timer tegra_delay_timer = { @@ -182,8 +182,9 @@ static struct timer_of suspend_rtc_to = { */ static u64 tegra_rtc_read_ms(struct clocksource *cs) { - u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS); - u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS); + void __iomem *reg_base = timer_of_base(&suspend_rtc_to); + u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); + u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); return (u64)s * MSEC_PER_SEC + ms; } @@ -268,7 +269,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) goto out; } - writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); + writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); From patchwork Sun May 5 16:24:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1095490 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Q28sN2rf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44xrnd0kDkz9sB8 for ; Mon, 6 May 2019 02:25:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727968AbfEEQZX (ORCPT ); Sun, 5 May 2019 12:25:23 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:34292 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727958AbfEEQZV (ORCPT ); Sun, 5 May 2019 12:25:21 -0400 Received: by mail-lj1-f196.google.com with SMTP id s7so3662902ljh.1; Sun, 05 May 2019 09:25:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0FSZQiIHMp/OF8rYpDO9NLzid+dz67fJNiFTup4WxAY=; b=Q28sN2rf0yktL0AiaZUsttkvA25LhQe16CQGDLcZ9WLr6/AfBTFTlCPi+9kKwrvi5v 34mRlCos44ZSEOg0NbRWxrt4OhvNTrdVj/mAwnLNhjL4wEN/6gaB8HXVuuCcTBoCT21y JSFoOMiP2Hxd/h0usGdlKPVd81yYVf6LZmchnzsmTmYradudZcD3uSA/X6w2xU9/bYVd EQLhmDLx4VqHauU9USfEVsXpOos7flYM/nULky05BvPThKfMn7xdS3XlTYY+Z52Thxb5 E5+B7PeIuzkgR4qTGemx7Trlc/acfZUJ978zZQzJk9lAEhGDvozibYkEswU2j8yTn/K8 znPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0FSZQiIHMp/OF8rYpDO9NLzid+dz67fJNiFTup4WxAY=; b=LIqqarrHjyV+G5/0CFd9NH/FBx7gudQfF4bwQhPBtRaG3B9CdCsPQUETnr2N+2li/p 9MBTQioznC6quWWRclYZWmkatjBIy/5Bxnj5cfH2w1JIw3nxka5oNq6/dbcKp3lxpU4R ERbiUgyz3jEDkowvbN5EXO2G8hJH/bftN3NJ5xyOdbCwUdaAkXkyc2wQl/kHveqVRqd8 A3fTjiRq5obDNwT+D6csza4XXUGPuhoA0rwAR8BMj5F0JrRd+ykN1zsG3dkbAWCKcXNY +F25VGmX22KhBzYSlWAqRv9q6NF26/vhtvGCHH7rCDLpfcUnEdp/jfn1OjM7FtUlRI1j O6Tw== X-Gm-Message-State: APjAAAUUOPFW2mWmhLx2o7mA2MMUPaxx73mVQvq+I48mq529xAHrqim1 RRs4+fKHnxkLrIYwLR7H1+U= X-Google-Smtp-Source: APXvYqx1E3S1jlWY4CR0ZROMNcFqj5j2JndVWizLf6CbXFae0hsXdMGWLJ85jK05p4i4V9gzrABmpQ== X-Received: by 2002:a2e:7611:: with SMTP id r17mr4674866ljc.95.1557073519478; Sun, 05 May 2019 09:25:19 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-35-107.pppoe.spdop.ru. [94.29.35.107]) by smtp.gmail.com with ESMTPSA id g13sm1581649lfh.49.2019.05.05.09.25.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 May 2019 09:25:18 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Thomas Gleixner , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/7] clocksource/drivers/tegra: Release all IRQ's on request_irq() error Date: Sun, 5 May 2019 19:24:34 +0300 Message-Id: <20190505162436.23125-6-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190505162436.23125-1-digetx@gmail.com> References: <20190505162436.23125-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Release all requested IRQ's on the request error to properly clean up allocated resources. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index cdac9e240714..7c06c0335fe3 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -291,7 +291,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) pr_err("%s: can't map IRQ for CPU%d\n", __func__, cpu); ret = -EINVAL; - goto out; + goto out_irq; } irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); @@ -301,7 +301,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) if (ret) { pr_err("%s: cannot setup irq %d for CPU%d\n", __func__, cpu_to->clkevt.irq, cpu); - ret = -EINVAL; + irq_dispose_mapping(cpu_to->clkevt.irq); + cpu_to->clkevt.irq = 0; goto out_irq; } } From patchwork Sun May 5 16:24:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1095493 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MIlfstXy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44xrp10YWWz9s55 for ; Mon, 6 May 2019 02:25:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727295AbfEEQZj (ORCPT ); Sun, 5 May 2019 12:25:39 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:40316 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727961AbfEEQZX (ORCPT ); Sun, 5 May 2019 12:25:23 -0400 Received: by mail-lf1-f67.google.com with SMTP id o16so7474125lfl.7; Sun, 05 May 2019 09:25:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cI+DDkol8uZ52CrNe3H46aTuu8e/t8qgnJnXk7G/mKY=; b=MIlfstXyyKflVVig9ysOc8fnhxhYY97ZBHKig/Ep+sTyh8me35KF3muGecgQUlHGPq gdMPBv65ZS+U58yZsydhIbiJMZoQ6a0/ysNLRD5P9jOI94/TIFnvuwTGXmkFMVc08zF4 yN0JG4hrRKy0RsFlBJ8PbVg3J9RHkTTMgZb9QY4lSa/uAybMzKITyD8VG5f+XdMN9I2r hvIk6ZZLKY+dmA+0HyfjZHs4nca/YqhJu2CntQquFtWlGHiHqsZlYr7QfBY0PXNlHuMk RFNilnh4nu0a2b1NDDP1k5kLBp/xC30wo8102zz24G6NXhBCi8j3bj+/RsYIEK31zujr G7dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cI+DDkol8uZ52CrNe3H46aTuu8e/t8qgnJnXk7G/mKY=; b=Or9/8y15TNHOX0LUx2pttR0kHc4EUqnmLSGR7KXnU1V3Fn44M8BO5p4CkDTHQuNo/U EHBXTYpcEsXVUWCfmAMoKkTv/Fng8eObVtMeqYTjSh1ycO0PTPtISVmQav3dnCRQ6tBm pUoSlrO+47kYCUWgo1KwdblmpADo0sz77gHOTP4MxLmNbjuQAeIazJ3g1Htp6T4vnUWa z5w1QO3TEZruk5nFdES1z8CXjHW32mgIE7Ee3DoBeW7ZkiB76rQrvR3MHIbtVvVX05/2 UNhHdF0Wv0oVay8M24XVARlTym+xpAWbf9yfAFyKy3UmNC24ea9xdEeKznHoOlxyzsfi NKqw== X-Gm-Message-State: APjAAAW5sCQrmeO7Ae97ppyGmxoPfHI3RKQ1Kv1Bii5dDweu3BRiaWK7 Yc9sjP6tbr20UUNBWHJxy8I= X-Google-Smtp-Source: APXvYqyJGQxlu5pAwvQEHmgJy7pLunQaFOmyrP5RmxKK3OfbhDGMG0uP406LLg8ba1GnUR3xtSGBdA== X-Received: by 2002:a19:9f01:: with SMTP id i1mr10333754lfe.98.1557073520600; Sun, 05 May 2019 09:25:20 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-35-107.pppoe.spdop.ru. [94.29.35.107]) by smtp.gmail.com with ESMTPSA id g13sm1581649lfh.49.2019.05.05.09.25.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 May 2019 09:25:19 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Thomas Gleixner , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/7] clocksource/drivers/tegra: Minor code clean up Date: Sun, 5 May 2019 19:24:35 +0300 Message-Id: <20190505162436.23125-7-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190505162436.23125-1-digetx@gmail.com> References: <20190505162436.23125-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Correct typo and use proper upper casing for acronyms in the comments, use common style for error messages, prepend error messages with "tegra-timer:", add error message for cpuhp_setup_state() failure and clean up whitespaces in the code to fix checkpatch warnings. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 43 ++++++++++++++++------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 7c06c0335fe3..47ef8c9aa0ba 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -15,6 +15,8 @@ * */ +#define pr_fmt(fmt) "tegra-timer: " fmt + #include #include #include @@ -30,13 +32,13 @@ #include "timer-of.h" -#define RTC_SECONDS 0x08 -#define RTC_SHADOW_SECONDS 0x0c -#define RTC_MILLISECONDS 0x10 +#define RTC_SECONDS 0x08 +#define RTC_SHADOW_SECONDS 0x0c +#define RTC_MILLISECONDS 0x10 -#define TIMERUS_CNTR_1US 0x10 -#define TIMERUS_USEC_CFG 0x14 -#define TIMERUS_CNTR_FREEZE 0x4c +#define TIMERUS_CNTR_1US 0x10 +#define TIMERUS_USEC_CFG 0x14 +#define TIMERUS_CNTR_FREEZE 0x4c #define TIMER_PTV 0x0 #define TIMER_PTV_EN BIT(31) @@ -57,7 +59,7 @@ static u32 usec_config; static void __iomem *timer_reg_base; static int tegra_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) + struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); @@ -176,15 +178,17 @@ static struct timer_of suspend_rtc_to = { /* * tegra_rtc_read - Reads the Tegra RTC registers - * Care must be taken that this funciton is not called while the + * Care must be taken that this function is not called while the * tegra_rtc driver could be executing to avoid race conditions * on the RTC shadow register */ static u64 tegra_rtc_read_ms(struct clocksource *cs) { void __iomem *reg_base = timer_of_base(&suspend_rtc_to); + u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); + return (u64)s * MSEC_PER_SEC + ms; } @@ -229,7 +233,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) to = this_cpu_ptr(&tegra_to); ret = timer_of_init(np, to); - if (ret < 0) + if (ret) goto out; timer_reg_base = timer_of_base(to); @@ -288,8 +292,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { - pr_err("%s: can't map IRQ for CPU%d\n", - __func__, cpu); + pr_err("failed to map irq for cpu%d\n", cpu); ret = -EINVAL; goto out_irq; } @@ -299,8 +302,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) IRQF_TIMER | IRQF_NOBALANCING, cpu_to->clkevt.name, &cpu_to->clkevt); if (ret) { - pr_err("%s: cannot setup irq %d for CPU%d\n", - __func__, cpu_to->clkevt.irq, cpu); + pr_err("failed to set up irq for cpu%d: %d\n", + cpu, ret); irq_dispose_mapping(cpu_to->clkevt.irq); cpu_to->clkevt.irq = 0; goto out_irq; @@ -317,11 +320,14 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) register_current_timer_delay(&tegra_delay_timer); - cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, - "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, - tegra_timer_stop); + ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, + "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, + tegra_timer_stop); + if (ret) + pr_err("failed to set up cpu hp state: %d\n", ret); return ret; + out_irq: for_each_possible_cpu(cpu) { struct timer_of *cpu_to; @@ -334,6 +340,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) } out: timer_of_cleanup(to); + return ret; } @@ -357,8 +364,6 @@ static int __init tegra20_init_rtc(struct device_node *np) if (ret) return ret; - clocksource_register_hz(&suspend_rtc_clocksource, 1000); - - return 0; + return clocksource_register_hz(&suspend_rtc_clocksource, 1000); } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); From patchwork Sun May 5 16:24:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1095491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SW1NgwzW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44xrnt70rZz9s9N for ; Mon, 6 May 2019 02:25:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727988AbfEEQZY (ORCPT ); Sun, 5 May 2019 12:25:24 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:34292 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727825AbfEEQZY (ORCPT ); Sun, 5 May 2019 12:25:24 -0400 Received: by mail-lj1-f195.google.com with SMTP id s7so3662940ljh.1; Sun, 05 May 2019 09:25:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BJiWha3xmfpfGUauVHHLrdkEBWwTxWF5yNbhjCCJouw=; b=SW1NgwzW5FOZVKR0o8KAMgxh1OA8ifum4GOaTCPIYc04SlQjVJ8TUJr+I362vdpHWF PB7m9hrcxc3LVy7ediTiCN5s1CsKhp4yO7akJ81WjkXMA3H4mA3J6PRdTmpFxVuTNNcZ pvGn/jasU+dQgGqIWSoIkdnSINtHaKeILbFzBqecW4Za/aRBGgLUJmXhfEAjzrey+cV3 SP93dUisShgXDP1rF6QPexphpMHBuc/OCi6wxmV4oVly0pfT8wWR7NQXSN6RbVZ9r/s7 m2cFPhrJ3r5eQ1U+Egw9LuJ2TtX1lW09vs1et5PXuk03EpeXlILvW9HK12lmJHiy1csv z7GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BJiWha3xmfpfGUauVHHLrdkEBWwTxWF5yNbhjCCJouw=; b=VZ9tQxTLzR11rEKWV2cGsFJab7yfBKRQDyRIZUobjqQZWiGwNk8Potv4szD0qo093E C0W3/xJ9oNqUt7d8C/RMRJTCtW0rzzV73Y/xeMdzVdQr0YAKSpEUL+22m14nZP/GKuwC dM66YjPjOLN2gNV451KA6IZHUpDjV5YHiC4SJ6bSNs761vATnCy37fD1qo8qGkTRo0LE CidqEawX0ib4gxJML5SQY1drKNPL6SkckkpfeWde+s7dTD64wUYcHfXUCI+RuD6QTrs9 Hf2Z8/cC1pkftes0zD9Ve84ICDmT/hHA0+Yh34zytEey3JBw6+Qb5KpmXpZHl8YMmYS+ ok5g== X-Gm-Message-State: APjAAAWIo+6GJpcRi/x7625QDmpGzO2MGLq+kJiC10TT77mVnwstElSN 9Y2o6AFiAfrsX1/mCKtBxuwc9jJZ X-Google-Smtp-Source: APXvYqz8k3mqo3ITBLY8yzWm3ryHGLOMDMrdFYexck9IbRLuYrusEo8C8YSL6TsrbOgqyUkFuITVbQ== X-Received: by 2002:a2e:97d8:: with SMTP id m24mr11047779ljj.192.1557073521658; Sun, 05 May 2019 09:25:21 -0700 (PDT) Received: from localhost.localdomain (ppp94-29-35-107.pppoe.spdop.ru. [94.29.35.107]) by smtp.gmail.com with ESMTPSA id g13sm1581649lfh.49.2019.05.05.09.25.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 May 2019 09:25:21 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Thomas Gleixner , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] clocksource/drivers/tegra: Use SPDX identifier Date: Sun, 5 May 2019 19:24:36 +0300 Message-Id: <20190505162436.23125-8-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190505162436.23125-1-digetx@gmail.com> References: <20190505162436.23125-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Use SPDX tag for the license identification instead of a free form text to aid license-checking automation and for brevity. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 47ef8c9aa0ba..40d9b27d30a3 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -1,18 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * + * Author: Colin Cross */ #define pr_fmt(fmt) "tegra-timer: " fmt