From patchwork Fri May 3 13:47:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw (lists)" X-Patchwork-Id: 1094898 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-500072-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="r+RB2jm1"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44wYND6DmFz9s7T for ; Fri, 3 May 2019 23:47:22 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=WCKV8nI1cnMKj1qDJhiBIrBch1m5tXY+ANJx89n2d4UE2DL9wy 0/ZgzTIddhlmmt/8+8zVHfSF8SDIIncyrwaEUe2NzP3GO9NzLpPJRQvyg6ZmVScb w2CHPjnbFeRQJDaD0jlgY9mxw9/IYseWZtZDnkR9kDfDd+vB0Pvtci1VI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=eSmWrAbOWc6ZESn2ZQnpdBZKCBo=; b=r+RB2jm1yipg5VwrXiux jAsikbd7/ehRkRpKbZn8N7oqEYl2Sd9E2Ltzaym7PK9d+jtCbnf2ZYmsLElBMX58 ttEjAdc1AEaBMzOeX0m8UR+TAGq96ZkmI1+Ts+MS7k80VObLS6H9+vh8R9NNckwm nrGiZYCkxhPzA2+0Fbx5cps= Received: (qmail 109334 invoked by alias); 3 May 2019 13:47:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 109324 invoked by uid 89); 3 May 2019 13:47:13 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-17.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 03 May 2019 13:47:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AB72A374; Fri, 3 May 2019 06:47:08 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.206.226]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2F5F63F5C1; Fri, 3 May 2019 06:47:08 -0700 (PDT) To: gcc-patches From: "Richard Earnshaw (lists)" Subject: [arm] PR target/89400 fix thumb1 unaligned access expansion Openpgp: preference=signencrypt Message-ID: Date: Fri, 3 May 2019 14:47:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 Armv6 has support for unaligned accesses to memory. However, the thumb1 code patterns were trying to use the 32-bit code constraints. One failure mode from this was that the patterns are designed to be compatible with conditional execution and this was then causing an assert in the compiler. The unaligned_loadhis pattern is only used for expanding extv, which in turn is only enabled for systems supporting thumb2. Given that there is no simple expansion for a thumb1 sign-extending load (the instruction has no immediate offset form and requires two registers in the address) it seems simpler to just disable this for thumb1. Fixed thusly: PR target/89400 * config/arm/arm.md (unaligned_loadsi): Add variant for thumb1. Restrict 'all' variant to 32-bit configurations. (unaligned_loadhiu): Likewise. (unaligned_storehi): Likewise. (unaligned_storesi): Likewise. (unaligned_loadhis): Disable when compiling for thumb1. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 0aecd03891c..ae582172ab9 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4483,62 +4483,78 @@ (define_expand "extv_regsi" ; ARMv6+ unaligned load/store instructions (used for packed structure accesses). (define_insn "unaligned_loadsi" - [(set (match_operand:SI 0 "s_register_operand" "=l,r") - (unspec:SI [(match_operand:SI 1 "memory_operand" "Uw,m")] + [(set (match_operand:SI 0 "s_register_operand" "=l,l,r") + (unspec:SI [(match_operand:SI 1 "memory_operand" "m,Uw,m")] UNSPEC_UNALIGNED_LOAD))] "unaligned_access" - "ldr%?\t%0, %1\t@ unaligned" - [(set_attr "arch" "t2,any") - (set_attr "length" "2,4") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,no") + "@ + ldr\t%0, %1\t@ unaligned + ldr%?\t%0, %1\t@ unaligned + ldr%?\t%0, %1\t@ unaligned" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4") + (set_attr "predicable" "no,yes,yes") + (set_attr "predicable_short_it" "no,yes,no") (set_attr "type" "load_4")]) +;; The 16-bit Thumb1 variant of ldrsh requires two registers in the +;; address (there's no immediate format). That's tricky to support +;; here and we don't really need this pattern for that case, so only +;; enable for 32-bit ISAs. (define_insn "unaligned_loadhis" [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extend:SI (unspec:HI [(match_operand:HI 1 "memory_operand" "Uh")] UNSPEC_UNALIGNED_LOAD)))] - "unaligned_access" + "unaligned_access && TARGET_32BIT" "ldrsh%?\t%0, %1\t@ unaligned" [(set_attr "predicable" "yes") (set_attr "type" "load_byte")]) (define_insn "unaligned_loadhiu" - [(set (match_operand:SI 0 "s_register_operand" "=l,r") + [(set (match_operand:SI 0 "s_register_operand" "=l,l,r") (zero_extend:SI - (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,m")] + (unspec:HI [(match_operand:HI 1 "memory_operand" "m,Uw,m")] UNSPEC_UNALIGNED_LOAD)))] "unaligned_access" - "ldrh%?\t%0, %1\t@ unaligned" - [(set_attr "arch" "t2,any") - (set_attr "length" "2,4") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,no") + "@ + ldrh\t%0, %1\t@ unaligned + ldrh%?\t%0, %1\t@ unaligned + ldrh%?\t%0, %1\t@ unaligned" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4") + (set_attr "predicable" "no,yes,yes") + (set_attr "predicable_short_it" "no,yes,no") (set_attr "type" "load_byte")]) (define_insn "unaligned_storesi" - [(set (match_operand:SI 0 "memory_operand" "=Uw,m") - (unspec:SI [(match_operand:SI 1 "s_register_operand" "l,r")] + [(set (match_operand:SI 0 "memory_operand" "=m,Uw,m") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "l,l,r")] UNSPEC_UNALIGNED_STORE))] "unaligned_access" - "str%?\t%1, %0\t@ unaligned" - [(set_attr "arch" "t2,any") - (set_attr "length" "2,4") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,no") + "@ + str\t%1, %0\t@ unaligned + str%?\t%1, %0\t@ unaligned + str%?\t%1, %0\t@ unaligned" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4") + (set_attr "predicable" "no,yes,yes") + (set_attr "predicable_short_it" "no,yes,no") (set_attr "type" "store_4")]) (define_insn "unaligned_storehi" - [(set (match_operand:HI 0 "memory_operand" "=Uw,m") - (unspec:HI [(match_operand:HI 1 "s_register_operand" "l,r")] + [(set (match_operand:HI 0 "memory_operand" "=m,Uw,m") + (unspec:HI [(match_operand:HI 1 "s_register_operand" "l,l,r")] UNSPEC_UNALIGNED_STORE))] "unaligned_access" - "strh%?\t%1, %0\t@ unaligned" - [(set_attr "arch" "t2,any") - (set_attr "length" "2,4") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,no") + "@ + strh\t%1, %0\t@ unaligned + strh%?\t%1, %0\t@ unaligned + strh%?\t%1, %0\t@ unaligned" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4") + (set_attr "predicable" "no,yes,yes") + (set_attr "predicable_short_it" "no,yes,no") (set_attr "type" "store_4")])