From patchwork Fri May 3 01:33:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dong Aisheng X-Patchwork-Id: 1094627 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="tz+kJVAG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44wF5N68qSz9sB8 for ; Fri, 3 May 2019 11:33:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726022AbfECBd0 (ORCPT ); Thu, 2 May 2019 21:33:26 -0400 Received: from mail-eopbgr00070.outbound.protection.outlook.com ([40.107.0.70]:45118 "EHLO EUR02-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725995AbfECBd0 (ORCPT ); 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x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d56d86fb-9fd8-40fe-57ab-08d6cf675409 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600141)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:AM0PR04MB6580; x-ms-traffictypediagnostic: AM0PR04MB6580: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; x-forefront-prvs: 0026334A56 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(136003)(39860400002)(396003)(376002)(346002)(366004)(54534003)(199004)(189003)(478600001)(2351001)(316002)(8676002)(81156014)(305945005)(5660300002)(81166006)(53936002)(99286004)(7736002)(66446008)(36756003)(86362001)(2906002)(37006003)(66946007)(66476007)(66556008)(64756008)(73956011)(8936002)(5640700003)(66066001)(4326008)(186003)(54906003)(85306007)(76176011)(71190400001)(6486002)(256004)(14444005)(11346002)(26005)(2616005)(6506007)(2501003)(68736007)(6862004)(6636002)(25786009)(446003)(44832011)(6512007)(14454004)(102836004)(476003)(3846002)(486006)(6436002)(6116002)(50226002)(386003)(71200400001)(52116002); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB6580; H:AM0PR04MB4211.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: KBKCiLfbvbJCQaKCkO6mtsajhZaLCHv9swQn9+ElxK3o7tBrcPDbAsDchm9iE4Yu+NrgnQp24edT/ZGffzF22QxEKtIpb/tvOzMKG60OXWOIhvFOcJGpOeTr8CqtAXwSA+TKO7WaKMuwodst1WT5Fhe01ZSI7SwYiJiMbAZ/Zt8LkucbYz1sM0UiPidSfr3h5IrZUQDuUuWx32CPxWkzGGjzwHzwVhIKVRLCUFPsmPnlq92q4t2gYYIVrXW/UcwXbQr7PcItbhCNrgQpzrIaslRda5q85/+6TzXICa74sAGKSE++F30+w6mSFMIUk/k14z3PVvx18LuutNPoROxdQQ+AucQvnt4LG2BgU8YEomwPmvMBZLIy+ADXFmtZdBATH3N+rMXvBFEeoBbiqMcoi8cSeO0JtkQXQirXPFt5noI= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d56d86fb-9fd8-40fe-57ab-08d6cf675409 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 May 2019 01:33:22.0901 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6580 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There's a few limitations on the original one cell clock binding (#clock-cells = <1>) that we have to define all clock IDs for device tree to reference. This may cause troubles if we want to use common clock IDs for multi platforms support when the clock of those platforms are mostly the same. e.g. Current clock IDs name are defined with SS prefix. However the device may reside in different SS across CPUs, that means the SS prefix may not valid anymore for a new SoC. Furthermore, the device availability of those clocks may also vary a bit. For such situation, We formerly planned to add all new IDs for each SS and dynamically check availability for different SoC in driver. That can be done but that may involve a lot effort and may result in more changes and duplicated code in driver, also make device tree upstreaming hard which depends on Clock IDs. To relief this situation, we want to move the clock definition into device tree which can fully decouple the dependency of Clock ID definition from device tree. This can make us write a full generic clock driver for SCU based SoCs. No more frequent changes needed in clock driver any more. In the meanwhile, we can also use the existence of clock nodes in device tree to address the device and clock availability differences across different SoCs. For SCU clocks, only two params required. The first one is resource id which is encoded in reg property and the second is clock type index which is encoded in generic clock-indices property they're not continuously. And as we also want to support clock set parent function, 'clocks' property is also used to pass all the possible input parents. Cc: Rob Herring Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Michael Turquette Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng --- ChangeLog: v1->v2: * changed to one cell binding inspired by arm,scpi.txt Documentation/devicetree/bindings/arm/arm,scpi.txt Resource ID is encoded in 'reg' property. Clock type is encoded in generic clock-indices property. Then we don't have to search all the DT nodes to fetch those two value to construct clocks which is relatively low efficiency. * Add required power-domain property as well. --- .../devicetree/bindings/arm/freescale/fsl,scu.txt | 45 ++++++++++++++++++---- include/dt-bindings/firmware/imx/rsrc.h | 17 ++++++++ 2 files changed, 54 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 5d7dbab..2f46e89 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -89,6 +89,27 @@ Required properties: "fsl,imx8qm-clock" "fsl,imx8qxp-clock" followed by "fsl,scu-clk" +- #address-cells: Should be 1. +- #size-cells: Should be 0. + +Sub nodes are required to represent all available SCU clocks within this +hardware subsystem and the following properties are needed: + +- reg: Should contain the Resource ID of this SCU clock. +- #clock-cells: Should be 1. +- clock-indices: Index of all clock types supported by this SCU clock. + The order should match the clock-output-names array. + Refer to for + available clock types supported by SCU. +- clock-output-names: Shall be the corresponding names of the outputs. +- power-domains: Should contain the power domain used by this SCU clock. + +Optional properties: +- clocks: Shall be the input parent clock(s) phandle for the clock. + For multiplexed clocks, the list order must match the hardware + programming order. + +Legacy Clock binding (No sub-nodes which is DEPRECATED): - #clock-cells: Should be 1. Contains the Clock ID value. - clocks: List of clock specifiers, must contain an entry for each required entry in clock-names @@ -144,6 +165,21 @@ lsio_mu1: mailbox@5d1c0000 { #mbox-cells = <2>; }; +conn-scu-clock-controller { + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #address-cells = <1>; + #size-cells = <0>; + + uart0_clk: clock-scu@57 { + reg = <57>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "uart0_clk"; + power-domains = <&pd IMX_SC_R_UART_0>; + }; + ... +} + firmware { scu { compatible = "fsl,imx-scu"; @@ -160,11 +196,6 @@ firmware { &lsio_mu1 1 3 &lsio_mu1 3 3>; - clk: clk { - compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; - #clock-cells = <1>; - }; - iomuxc { compatible = "fsl,imx8qxp-iomuxc"; @@ -192,8 +223,6 @@ serial@5a060000 { ... pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; - clocks = <&clk IMX8QXP_UART0_CLK>, - <&clk IMX8QXP_UART0_IPG_CLK>; - clock-names = "per", "ipg"; + clocks = <&uart0_clk IMX_SC_PM_CLK_PER>; power-domains = <&pd IMX_SC_R_UART_0>; }; diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h index 4e61f64..fbeaca7 100644 --- a/include/dt-bindings/firmware/imx/rsrc.h +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -547,4 +547,21 @@ #define IMX_SC_R_ATTESTATION 545 #define IMX_SC_R_LAST 546 +/* + * Defines for SC PM CLK + */ +#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ +#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */ +#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */ +#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */ +#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */ +#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */ +#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */ +#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */ +#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */ +#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */ +#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ +#define IMX_SC_PM_CLK_PLL 4 /* PLL */ +#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ + #endif /* __DT_BINDINGS_RSCRC_IMX_H */ From patchwork Fri May 3 01:33:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dong Aisheng X-Patchwork-Id: 1094628 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="pQXDeq+m"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44wF5V4RtKz9sB8 for ; Fri, 3 May 2019 11:33:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726128AbfECBdd (ORCPT ); Thu, 2 May 2019 21:33:33 -0400 Received: from mail-eopbgr70088.outbound.protection.outlook.com ([40.107.7.88]:26053 "EHLO EUR04-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725995AbfECBdd (ORCPT ); Thu, 2 May 2019 21:33:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=m+oyjylI89WOdiEJe1vxtVTeRifl01vyRdMgmrLAUBE=; b=pQXDeq+m5y4svZpmJFFlT4lfOvSREcJC1+ld1cYqu+UanjlB9ErK7n+L+Pi0VtraMUf0nHtsbfDnnlX+e99dmDfBoL1RhmKdhh6pH5pjBruQDRscoRylPLQQhOdtMYSGejzhS2CDBQDlNkIvfeXZjq+t7q8GZfpw5g4toHiMLP4= Received: from AM0PR04MB4211.eurprd04.prod.outlook.com (52.134.92.158) by AM0PR04MB4963.eurprd04.prod.outlook.com (20.176.215.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1835.15; Fri, 3 May 2019 01:33:25 +0000 Received: from AM0PR04MB4211.eurprd04.prod.outlook.com ([fe80::c415:3cab:a042:2e13]) by AM0PR04MB4211.eurprd04.prod.outlook.com ([fe80::c415:3cab:a042:2e13%6]) with mapi id 15.20.1856.008; Fri, 3 May 2019 01:33:25 +0000 From: Aisheng Dong To: "aiseng.dong@nxp.com" CC: Aisheng Dong , Rob Herring , Stephen Boyd , Shawn Guo , Sascha Hauer , Michael Turquette , "devicetree@vger.kernel.org" Subject: [PATCH V2 2/2] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree Thread-Topic: [PATCH V2 2/2] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree Thread-Index: AQHVAVAzpBGy5f0kM0GYy1BqD4Xf7Q== Date: Fri, 3 May 2019 01:33:25 +0000 Message-ID: <1556846746-8535-3-git-send-email-aisheng.dong@nxp.com> References: <1556846746-8535-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1556846746-8535-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR04CA0047.apcprd04.prod.outlook.com (2603:1096:202:14::15) To AM0PR04MB4211.eurprd04.prod.outlook.com (2603:10a6:208:5b::30) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4963; H:AM0PR04MB4211.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: kqaYNJhmzKAGJO/glH031+QILg6rliDIHYTNlr6aylHF1RbmTR1cxdVHYBRH/ea2ZoEW+e6bW9Le8aSxLn+Ggm7itmQYkSRtpwqjkA8sIGg2AYxSQzKrNZ2FjpYEvbmOPpn9gJpkuUn0TwN+gEN9O5nrJu9konqpOYNhVNbc+mktjvfwLBe4hCPtys/LFTRXcJ9N/1hHcYI5cV9OKzRvPQL3GWtUvAZHPdQaE4jwCa51lPT6boRBEiyxDC/IkDVQBQjoidBbMcRyChHghofXgNhaq93uzZuKbkP2gr+p/eRFVBRQDVpPcQkphLnj7QrdoRcKo5yclBCggOxJ/9EQJh0JWWzFMhssQa6j7TikN340tzNy59OT02o/JPNvAds9HEnTv2DHHIoBHJSokmdEPbGBNVc0oQceSX5yHNPaQME= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6ae3a45e-a739-4f1b-86c6-08d6cf6755c2 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 May 2019 01:33:25.0754 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4963 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MX8QM and MX8QXP LPCG Clocks are mostly the same except they may reside in different subsystems across CPUs and also vary a bit on the availability. Same as SCU clock, we want to move the clock definition into device tree which can fully decouple the dependency of Clock ID definition from device tree and make us be able to write a fully generic lpcg clock driver. And we can also use the existence of clock nodes in device tree to address the device and clock availability differences across different SoCs. Cc: Rob Herring Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Michael Turquette Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng --- ChangeLog: v1->v2: * Update example * Add power domain property --- .../devicetree/bindings/clock/imx8qxp-lpcg.txt | 34 ++++++++++++++++++---- 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt index 965cfa4..6fc2fd8 100644 --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt @@ -11,6 +11,21 @@ enabled by these control bits, it might still not be running based on the base resource. Required properties: +- compatible: Should be one of: + "fsl,imx8qxp-lpcg" + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg". +- reg: Address and length of the register set. +- #clock-cells: Should be 1. One LPCG supports multiple clocks. +- clocks: Input parent clocks phandle array for each clock. +- bit-offset: An integer array indicating the bit offset for each clock. +- hw-autogate: Boolean array indicating whether supports HW autogate for + each clock. +- clock-output-names: Shall be the corresponding names of the outputs. + NOTE this property must be specified in the same order + as the clock bit-offset and hw-autogate property. +- power-domains: Should contain the power domain used by this clock. + +Legacy binding (DEPRECATED): - compatible: Should be one of: "fsl,imx8qxp-lpcg-adma", "fsl,imx8qxp-lpcg-conn", @@ -33,10 +48,17 @@ Examples: #include -conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; +sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b200000 0x10000>; #clock-cells = <1>; + clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; }; usdhc1: mmc@5b010000 { @@ -44,8 +66,8 @@ usdhc1: mmc@5b010000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; };