From patchwork Mon Apr 29 05:32:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1092412 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=alistair23.me Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44stcZ1Kkqz9s3l for ; Mon, 29 Apr 2019 15:33:50 +1000 (AEST) Received: from localhost ([127.0.0.1]:52376 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hKyvE-0006Pn-3y for incoming@patchwork.ozlabs.org; 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Mon, 29 Apr 2019 05:32:45 +0000 Received: from PSXP216MB0277.KORP216.PROD.OUTLOOK.COM ([fe80::d5cf:d2af:3aea:e2a3]) by PSXP216MB0277.KORP216.PROD.OUTLOOK.COM ([fe80::d5cf:d2af:3aea:e2a3%3]) with mapi id 15.20.1835.018; Mon, 29 Apr 2019 05:32:45 +0000 From: Alistair Francis To: "qemu-devel@nongnu.org" Thread-Topic: [PATCH v1 1/5] armv7m: Allow entry information to be returned Thread-Index: AQHU/kz5MoXWFw84ikmnMMJNVLzLcA== Date: Mon, 29 Apr 2019 05:32:45 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-AU, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR07CA0092.namprd07.prod.outlook.com (2603:10b6:a03:12b::33) To PSXP216MB0277.KORP216.PROD.OUTLOOK.COM (2603:1096:300:a::18) x-incomingtopheadermarker: OriginalChecksum:15E670DBA218DAB19B3684070D6244FA4870A181AB0A568286D579F97E07AC65; UpperCasedChecksum:C89B6D528A49E47541505FC97990DE83E253DEC630FAB7EC35EB2D7466A26649; SizeAsReceived:7537; Count:50 x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.21.0 x-tmn: [nNbDb3OTioxMIxt1Ic59is7dYMpDiUQj+CMrzL1pNyUbwaDMpdNSRmbp+4J++f6M] x-microsoft-original-message-id: <114729bb106dbc14480880ca4b91c3fbe8eb3783.1556515687.git.alistair@alistair23.me> x-ms-publictraffictype: Email x-incomingheadercount: 50 x-eopattributedmessage: 0 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(5050001)(7020095)(20181119110)(201702061078)(5061506573)(5061507331)(1603103135)(2017031320274)(2017031323274)(2017031324274)(2017031322404)(1601125500)(1603101475)(1701031045); SRVR:SG2APC01HT019; x-ms-traffictypediagnostic: SG2APC01HT019: x-microsoft-antispam-message-info: wWFWoVgzGAPioU1lMgiN0MVTbZr1GU5vmo68hQLDbRd1i58+pRys2PltvT9ut5tJfnIWtYWwHOxXH0H/HQhpPXC0cBATpIDqNB3zzUQYRoDFOkqKRi3OiaPZ5ebsvUN+IRiVV3m2F2zBm6K0/i35YK1FXv21MgNfRLmlVUdHk+tb3j9h2gcGuMToFzQrnwz1 MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: c3c6f30f-a90c-43b3-e112-08d6cc641b79 X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Apr 2019 05:32:45.4396 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2APC01HT019 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.92.254.67 Subject: [Qemu-devel] [PATCH v1 1/5] armv7m: Allow entry information to be returned X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Allow the kernel's entry point information to be returned when loading a kernel. Signed-off-by: Alistair Francis --- hw/arm/armv7m.c | 6 +++--- hw/arm/microbit.c | 2 +- hw/arm/mps2-tz.c | 3 ++- hw/arm/mps2.c | 2 +- hw/arm/msf2-som.c | 2 +- hw/arm/musca.c | 3 ++- hw/arm/netduino2.c | 2 +- hw/arm/stellaris.c | 3 ++- include/hw/arm/arm.h | 4 +++- 9 files changed, 16 insertions(+), 11 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index c4b2a9a1f5..a52328f188 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -286,10 +286,10 @@ static void armv7m_reset(void *opaque) cpu_reset(CPU(cpu)); } -void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) +void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size, + uint64_t *entry) { int image_size; - uint64_t entry; uint64_t lowaddr; int big_endian; AddressSpace *as; @@ -311,7 +311,7 @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) if (kernel_filename) { image_size = load_elf_as(kernel_filename, NULL, NULL, NULL, - &entry, &lowaddr, + entry, &lowaddr, NULL, big_endian, EM_ARM, 1, 0, as); if (image_size < 0) { image_size = load_image_targphys_as(kernel_filename, 0, diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index da67bf6d9d..03147750f1 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -58,7 +58,7 @@ static void microbit_init(MachineState *machine) mr, -1); armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, - NRF51_SOC(soc)->flash_size); + NRF51_SOC(soc)->flash_size, NULL); } static void microbit_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index f79f090a4a..f6dc7dce2a 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -613,7 +613,8 @@ static void mps2tz_common_init(MachineState *machine) create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000, + NULL); } static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index e3d698ba6c..55d2273a54 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -328,7 +328,7 @@ static void mps2_common_init(MachineState *machine) system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, - 0x400000); + 0x400000, NULL); } static void mps2_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 2432b5e935..f81be74716 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -92,7 +92,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line); armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, - soc->envm_size); + soc->envm_size, NULL); } static void emcraft_sf2_machine_init(MachineClass *mc) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 23aff43f4b..59460ba090 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -589,7 +589,8 @@ static void musca_init(MachineState *machine) "cfg_sec_resp", 0)); } - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x2000000); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x2000000, + NULL); } static void musca_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index f936017d4a..38a6d8fdd1 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -38,7 +38,7 @@ static void netduino2_init(MachineState *machine) object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, - FLASH_SIZE); + FLASH_SIZE, NULL); } static void netduino2_machine_init(MachineClass *mc) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 05f86749f4..276b1acc46 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1459,7 +1459,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) create_unimplemented_device("hibernation", 0x400fc000, 0x1000); create_unimplemented_device("flash-control", 0x400fd000, 0x1000); - armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); + armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size, + NULL); } /* FIXME: Figure out how to generate these from stellaris_boards. */ diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index ffed39252d..10f7e10d95 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -28,12 +28,14 @@ typedef enum { * @cpu: CPU * @kernel_filename: file to load * @mem_size: mem_size: maximum image size to load + * @entry: location of the kernel's entry point * * Load the guest image for an ARMv7M system. This must be called by * any ARMv7M board. (This is necessary to ensure that the CPU resets * correctly on system reset, as well as for kernel loading.) */ -void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size); +void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size, + uint64_t *entry); /* arm_boot.c */ struct arm_boot_info { From patchwork Mon Apr 29 05:32:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1092413 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=alistair23.me Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44std13ltHz9s3l for ; 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Mon, 29 Apr 2019 05:32:59 +0000 Received: from PSXP216MB0277.KORP216.PROD.OUTLOOK.COM (10.152.250.59) by SG2APC01FT020.mail.protection.outlook.com (10.152.250.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.1835.13 via Frontend Transport; Mon, 29 Apr 2019 05:32:59 +0000 Received: from PSXP216MB0277.KORP216.PROD.OUTLOOK.COM ([fe80::d5cf:d2af:3aea:e2a3]) by PSXP216MB0277.KORP216.PROD.OUTLOOK.COM ([fe80::d5cf:d2af:3aea:e2a3%3]) with mapi id 15.20.1835.018; Mon, 29 Apr 2019 05:32:59 +0000 From: Alistair Francis To: "qemu-devel@nongnu.org" Thread-Topic: [PATCH v1 2/5] hw/misc: Add the STM32F4xx Sysconfig device Thread-Index: AQHU/k0BMFoeC1advEGt/ueaNNAP6A== Date: Mon, 29 Apr 2019 05:32:59 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-AU, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR07CA0085.namprd07.prod.outlook.com (2603:10b6:a03:12b::26) To PSXP216MB0277.KORP216.PROD.OUTLOOK.COM (2603:1096:300:a::18) x-incomingtopheadermarker: OriginalChecksum:CC9C6B26FD2B4856CDDD263752216D868D54C8ADF40B38B190F4C9BCF3667EB6; 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IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/misc/stm32f4xx_syscfg.h" + +#ifndef STM_SYSCFG_ERR_DEBUG +#define STM_SYSCFG_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (STM_SYSCFG_ERR_DEBUG >= lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0) + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void stm32f4xx_syscfg_reset(DeviceState *dev) +{ + STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev); + + s->syscfg_memrmp = 0x00000000; + s->syscfg_pmc = 0x00000000; + s->syscfg_exticr1 = 0x00000000; + s->syscfg_exticr2 = 0x00000000; + s->syscfg_exticr3 = 0x00000000; + s->syscfg_exticr4 = 0x00000000; + s->syscfg_cmpcr = 0x00000000; +} + +static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level) +{ + STM32F4xxSyscfgState *s = opaque; + uint8_t config; + + DB_PRINT("Interupt: GPIO: %d, Line: %d; Level: %d\n", irq / 16, + irq % 16, level); + + config = irq / 16; + + switch (irq % 16) { + case 0: + if ((s->syscfg_exticr1 & 0xF) == config) { + qemu_set_irq(s->gpio_out[0], level); + DB_PRINT("Pulse EXTI: 0\n"); + } + break; + case 1: + if (((s->syscfg_exticr1 & 0xF0) >> 4) == config) { + qemu_set_irq(s->gpio_out[1], level); + DB_PRINT("Pulse EXTI: 1\n"); + } + break; + case 2: + if (((s->syscfg_exticr1 & 0xF00) >> 8) == config) { + qemu_set_irq(s->gpio_out[2], level); + DB_PRINT("Pulse EXTI: 2\n"); + } + break; + case 3: + if (((s->syscfg_exticr1 & 0xF000) >> 12) == config) { + qemu_set_irq(s->gpio_out[3], level); + DB_PRINT("Pulse EXTI: 3\n"); + } + break; + case 4: + if ((s->syscfg_exticr2 & 0xF) == config) { + qemu_set_irq(s->gpio_out[4], level); + DB_PRINT("Pulse EXTI: 4\n"); + } + break; + case 5: + if (((s->syscfg_exticr2 & 0xF0) >> 4) == config) { + qemu_set_irq(s->gpio_out[5], level); + DB_PRINT("Pulse EXTI: 5\n"); + } + break; + case 6: + if (((s->syscfg_exticr2 & 0xF00) >> 8) == config) { + qemu_set_irq(s->gpio_out[6], level); + DB_PRINT("Pulse EXTI: 6\n"); + } + break; + case 7: + if (((s->syscfg_exticr2 & 0xF000) >> 12) == config) { + qemu_set_irq(s->gpio_out[7], level); + DB_PRINT("Pulse EXTI: 7\n"); + } + break; + case 8: + if ((s->syscfg_exticr3 & 0xF) == config) { + qemu_set_irq(s->gpio_out[8], level); + DB_PRINT("Pulse EXTI: 8\n"); + } + break; + case 9: + if (((s->syscfg_exticr3 & 0xF0) >> 4) == config) { + qemu_set_irq(s->gpio_out[9], level); + DB_PRINT("Pulse EXTI: 9\n"); + } + break; + case 10: + if (((s->syscfg_exticr3 & 0xF00) >> 8) == config) { + qemu_set_irq(s->gpio_out[10], level); + DB_PRINT("Pulse EXTI: 10\n"); + } + break; + case 11: + if (((s->syscfg_exticr3 & 0xF000) >> 12) == config) { + qemu_set_irq(s->gpio_out[11], level); + DB_PRINT("Pulse EXTI: 11\n"); + } + break; + case 12: + if ((s->syscfg_exticr4 & 0xF) == config) { + qemu_set_irq(s->gpio_out[12], level); + DB_PRINT("Pulse EXTI: 12\n"); + } + break; + case 13: + if (((s->syscfg_exticr4 & 0xF0) >> 4) == config) { + qemu_set_irq(s->gpio_out[13], level); + DB_PRINT("Pulse EXTI: 13\n"); + } + break; + case 14: + if (((s->syscfg_exticr4 & 0xF00) >> 8) == config) { + qemu_set_irq(s->gpio_out[14], level); + DB_PRINT("Pulse EXTI: 14\n"); + } + break; + case 15: + if (((s->syscfg_exticr4 & 0xF000) >> 12) == config) { + qemu_set_irq(s->gpio_out[15], level); + DB_PRINT("Pulse EXTI: 15\n"); + } + break; + } +} + +static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr, + unsigned int size) +{ + STM32F4xxSyscfgState *s = opaque; + + DB_PRINT("0x%"HWADDR_PRIx"\n", addr); + + switch (addr) { + case SYSCFG_MEMRMP: + return s->syscfg_memrmp; + case SYSCFG_PMC: + return s->syscfg_pmc; + case SYSCFG_EXTICR1: + return s->syscfg_exticr1; + case SYSCFG_EXTICR2: + return s->syscfg_exticr2; + case SYSCFG_EXTICR3: + return s->syscfg_exticr3; + case SYSCFG_EXTICR4: + return s->syscfg_exticr4; + case SYSCFG_CMPCR: + return s->syscfg_cmpcr; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + return 0; + } + + return 0; +} + +static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + STM32F4xxSyscfgState *s = opaque; + uint32_t value = val64; + + DB_PRINT("0x%x, 0x%"HWADDR_PRIx"\n", value, addr); + + switch (addr) { + case SYSCFG_MEMRMP: + qemu_log_mask(LOG_UNIMP, + "%s: Changeing the memory mapping isn't supported " \ + "in QEMU\n", __func__); + return; + case SYSCFG_PMC: + qemu_log_mask(LOG_UNIMP, + "%s: Changeing the memory mapping isn't supported " \ + "in QEMU\n", __func__); + return; + case SYSCFG_EXTICR1: + s->syscfg_exticr1 = (value & 0xFFFF); + return; + case SYSCFG_EXTICR2: + s->syscfg_exticr2 = (value & 0xFFFF); + return; + case SYSCFG_EXTICR3: + s->syscfg_exticr3 = (value & 0xFFFF); + return; + case SYSCFG_EXTICR4: + s->syscfg_exticr4 = (value & 0xFFFF); + return; + case SYSCFG_CMPCR: + s->syscfg_cmpcr = value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } +} + +static const MemoryRegionOps stm32f4xx_syscfg_ops = { + .read = stm32f4xx_syscfg_read, + .write = stm32f4xx_syscfg_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void stm32f4xx_syscfg_init(Object *obj) +{ + STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s, + TYPE_STM32F4XX_SYSCFG, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9); + qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16); +} + +static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32f4xx_syscfg_reset; +} + +static const TypeInfo stm32f4xx_syscfg_info = { + .name = TYPE_STM32F4XX_SYSCFG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F4xxSyscfgState), + .instance_init = stm32f4xx_syscfg_init, + .class_init = stm32f4xx_syscfg_class_init, +}; + +static void stm32f4xx_syscfg_register_types(void) +{ + type_register_static(&stm32f4xx_syscfg_info); +} + +type_init(stm32f4xx_syscfg_register_types) diff --git a/include/hw/misc/stm32f4xx_syscfg.h b/include/hw/misc/stm32f4xx_syscfg.h new file mode 100644 index 0000000000..790f60746f --- /dev/null +++ b/include/hw/misc/stm32f4xx_syscfg.h @@ -0,0 +1,62 @@ +/* + * STM32F4xx SYSCFG + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_STM_SYSCFG_H +#define HW_STM_SYSCFG_H + +#include "hw/sysbus.h" +#include "hw/hw.h" + +#define SYSCFG_MEMRMP 0x00 +#define SYSCFG_PMC 0x04 +#define SYSCFG_EXTICR1 0x08 +#define SYSCFG_EXTICR2 0x0C +#define SYSCFG_EXTICR3 0x10 +#define SYSCFG_EXTICR4 0x14 +#define SYSCFG_CMPCR 0x20 + +#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg" +#define STM32F4XX_SYSCFG(obj) \ + OBJECT_CHECK(STM32F4xxSyscfgState, (obj), TYPE_STM32F4XX_SYSCFG) + +typedef struct { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint32_t syscfg_memrmp; + uint32_t syscfg_pmc; + uint32_t syscfg_exticr1; + uint32_t syscfg_exticr2; + uint32_t syscfg_exticr3; + uint32_t syscfg_exticr4; + uint32_t syscfg_cmpcr; + + qemu_irq irq; + qemu_irq gpio_out[16]; +} STM32F4xxSyscfgState; + +#endif From patchwork Mon Apr 29 05:33:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1092414 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=alistair23.me Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44sth744gdz9s3l for ; Mon, 29 Apr 2019 15:36:54 +1000 (AEST) Received: from localhost ([127.0.0.1]:52437 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hKyy7-00014M-Kt for incoming@patchwork.ozlabs.org; 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Mon, 29 Apr 2019 05:33:12 +0000 Received: from PSXP216MB0277.KORP216.PROD.OUTLOOK.COM ([fe80::d5cf:d2af:3aea:e2a3]) by PSXP216MB0277.KORP216.PROD.OUTLOOK.COM ([fe80::d5cf:d2af:3aea:e2a3%3]) with mapi id 15.20.1835.018; Mon, 29 Apr 2019 05:33:12 +0000 From: Alistair Francis To: "qemu-devel@nongnu.org" Thread-Topic: [PATCH v1 3/5] hw/misc: Add the STM32F4xx EXTI device Thread-Index: AQHU/k0JfWuZ1cs3QEqRXZOMKOZEsw== Date: Mon, 29 Apr 2019 05:33:12 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-AU, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR07CA0081.namprd07.prod.outlook.com (2603:10b6:a03:12b::22) To PSXP216MB0277.KORP216.PROD.OUTLOOK.COM (2603:1096:300:a::18) x-incomingtopheadermarker: OriginalChecksum:1F2B2EA11A11F828326E0E0F8011F90DC5B1960E1C8BA9D8DA097A66CF6DAEAA; UpperCasedChecksum:2226D262328CC1FACD2CE5A9CEE5F7476DB98BF615137205C64BE2488F82A282; SizeAsReceived:7522; Count:50 x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.21.0 x-tmn: [nXNvGuN9CyD/Q9faNQ96pZCuyo669DS2AHDGlEPjO/UFJzvJSi1854Zrlhq0GMHw] x-microsoft-original-message-id: x-ms-publictraffictype: Email x-incomingheadercount: 50 x-eopattributedmessage: 0 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(5050001)(7020095)(20181119110)(201702061078)(5061506573)(5061507331)(1603103135)(2017031320274)(2017031323274)(2017031324274)(2017031322404)(1601125500)(1603101475)(1701031045); SRVR:SG2APC01HT045; x-ms-traffictypediagnostic: SG2APC01HT045: x-microsoft-antispam-message-info: 7dRJ38KmvUTa3xBNWmC8QWow6H1scUc/d1H2qs9d1OaT+WCzrKfQTqsS1M6XSSj7nbHOyo6bnDmX6+6p5FUZIUzOJ6XMIKruBMSskTvAi8LgPsW+9TTlSwjR2BOYeM2S0p6OBNGxxZHyjX/s6urkXPbbxHi5lL8ThbM4yGwxs9dviBhBq67H/tfkFQomqWEy MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: d3694cc2-7ea0-4541-fac6-08d6cc642b95 X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Apr 2019 05:33:12.5634 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2APC01HT045 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.92.254.70 Subject: [Qemu-devel] [PATCH v1 3/5] hw/misc: Add the STM32F4xx EXTI device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- default-configs/arm-softmmu.mak | 1 + hw/misc/Kconfig | 3 + hw/misc/Makefile.objs | 1 + hw/misc/stm32f4xx_exti.c | 175 +++++++++++++++++++++++++++++++ include/hw/misc/stm32f4xx_exti.h | 57 ++++++++++ 5 files changed, 237 insertions(+) create mode 100644 hw/misc/stm32f4xx_exti.c create mode 100644 include/hw/misc/stm32f4xx_exti.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index c5cfdb857d..8eb57de211 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -97,6 +97,7 @@ CONFIG_STM32F2XX_ADC=y CONFIG_STM32F2XX_SPI=y CONFIG_STM32F205_SOC=y CONFIG_STM32F4XX_SYSCFG=y +CONFIG_STM32F4XX_EXTI=y CONFIG_NRF51_SOC=y CONFIG_CMSDK_APB_TIMER=y diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index c6ff39aeeb..3748b5f11a 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -83,6 +83,9 @@ config STM32F2XX_SYSCFG config STM32F4XX_SYSCFG bool +config STM32F4XX_EXTI + bool + config MIPS_ITU bool diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 1413b1f232..74c7ca6c05 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -58,6 +58,7 @@ obj-$(CONFIG_ZYNQ) += zynq_slcr.o obj-$(CONFIG_ZYNQ) += zynq-xadc.o obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o +obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) += mips_cpc.o obj-$(CONFIG_MIPS_ITU) += mips_itu.o diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c new file mode 100644 index 0000000000..b31f06cdca --- /dev/null +++ b/hw/misc/stm32f4xx_exti.c @@ -0,0 +1,175 @@ +/* + * STM32F4XX EXTI + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/log.h" +#include "hw/misc/stm32f4xx_exti.h" + +#ifndef STM_EXTI_ERR_DEBUG +#define STM_EXTI_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (STM_EXTI_ERR_DEBUG >= lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0) + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +#define NUM_GPIO_EVENT_IN_LINES 16 +#define NUM_INTERRUPT_OUT_LINES 16 + +static void stm32f4xx_exti_reset(DeviceState *dev) +{ + STM32F4xxExtiState *s = STM32F4XX_EXTI(dev); + + s->exti_imr = 0x00000000; + s->exti_emr = 0x00000000; + s->exti_rtsr = 0x00000000; + s->exti_ftsr = 0x00000000; + s->exti_swier = 0x00000000; + s->exti_pr = 0x00000000; +} + +static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level) +{ + STM32F4xxExtiState *s = opaque; + + DB_PRINT("Set EXTI: %d to %d\n", irq, level); + + if (level) { + qemu_irq_pulse(s->irq[irq]); + s->exti_pr |= 1 << irq; + } +} + +static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr, + unsigned int size) +{ + STM32F4xxExtiState *s = opaque; + + DB_PRINT("0x%x\n", (uint) addr); + + switch (addr) { + case EXTI_IMR: + return s->exti_imr; + case EXTI_EMR: + return s->exti_emr; + case EXTI_RTSR: + return s->exti_rtsr; + case EXTI_FTSR: + return s->exti_ftsr; + case EXTI_SWIER: + return s->exti_swier; + case EXTI_PR: + return s->exti_pr; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32F4XX_exti_read: Bad offset %x\n", (int)addr); + return 0; + } + return 0; +} + +static void stm32f4xx_exti_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + STM32F4xxExtiState *s = opaque; + uint32_t value = (uint32_t) val64; + + DB_PRINT("0x%x, 0x%x\n", value, (uint) addr); + + switch (addr) { + case EXTI_IMR: + s->exti_imr = value; + return; + case EXTI_EMR: + s->exti_emr = value; + return; + case EXTI_RTSR: + s->exti_rtsr = value; + return; + case EXTI_FTSR: + s->exti_ftsr = value; + return; + case EXTI_SWIER: + s->exti_swier = value; + return; + case EXTI_PR: + /* This bit is cleared by writing a 1 to it */ + s->exti_pr &= ~value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32F4XX_exti_write: Bad offset %x\n", (int)addr); + } +} + +static const MemoryRegionOps stm32f4xx_exti_ops = { + .read = stm32f4xx_exti_read, + .write = stm32f4xx_exti_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void stm32f4xx_exti_init(Object *obj) +{ + STM32F4xxExtiState *s = STM32F4XX_EXTI(obj); + int i; + + s->irq = g_new0(qemu_irq, NUM_INTERRUPT_OUT_LINES); + for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) { + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); + } + + memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s, + TYPE_STM32F4XX_EXTI, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq, + NUM_GPIO_EVENT_IN_LINES); +} + +static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32f4xx_exti_reset; +} + +static const TypeInfo stm32f4xx_exti_info = { + .name = TYPE_STM32F4XX_EXTI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F4xxExtiState), + .instance_init = stm32f4xx_exti_init, + .class_init = stm32f4xx_exti_class_init, +}; + +static void stm32f4xx_exti_register_types(void) +{ + type_register_static(&stm32f4xx_exti_info); +} + +type_init(stm32f4xx_exti_register_types) diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h new file mode 100644 index 0000000000..a9a4c86ef7 --- /dev/null +++ b/include/hw/misc/stm32f4xx_exti.h @@ -0,0 +1,57 @@ +/* + * STM32F4XX EXTI + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_STM_EXTI_H +#define HW_STM_EXTI_H + +#include "hw/sysbus.h" +#include "hw/hw.h" + +#define EXTI_IMR 0x00 +#define EXTI_EMR 0x04 +#define EXTI_RTSR 0x08 +#define EXTI_FTSR 0x0C +#define EXTI_SWIER 0x10 +#define EXTI_PR 0x14 + +#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti" +#define STM32F4XX_EXTI(obj) \ + OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI) + +typedef struct { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t exti_imr; + uint32_t exti_emr; + uint32_t exti_rtsr; + uint32_t exti_ftsr; + uint32_t exti_swier; + uint32_t exti_pr; + + qemu_irq *irq; +} STM32F4xxExtiState; + +#endif From patchwork Mon Apr 29 05:33:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1092415 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 29 Apr 2019 05:33:25 +0000 From: Alistair Francis To: "qemu-devel@nongnu.org" Thread-Topic: [PATCH v1 4/5] hw/arm: Add the STM32F4xx SoC Thread-Index: AQHU/k0RVI9NwWTYLUizgcdh/byezg== Date: Mon, 29 Apr 2019 05:33:25 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-AU, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR07CA0077.namprd07.prod.outlook.com (2603:10b6:a03:12b::18) To PSXP216MB0277.KORP216.PROD.OUTLOOK.COM (2603:1096:300:a::18) x-incomingtopheadermarker: OriginalChecksum:0AD8B502FA002EBA79EEA9A4A480F60A8702902A0E6F45E0290DF07DB089B264; UpperCasedChecksum:7604A17E449530C7847D7AC6D24F83DB2A0538D424F96B9A317498915F049CC5; SizeAsReceived:7518; Count:50 x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.21.0 x-tmn: [SophLUWdZev7efa/Fdxd5RqoFG+2UiCYSbgmybmUXmGeJHbW09r1wtvp+rAUlPM1] x-microsoft-original-message-id: x-ms-publictraffictype: Email x-incomingheadercount: 50 x-eopattributedmessage: 0 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(5050001)(7020095)(20181119110)(201702061078)(5061506573)(5061507331)(1603103135)(2017031320274)(2017031323274)(2017031324274)(2017031322404)(1601125500)(1603101475)(1701031045); SRVR:SG2APC01HT019; x-ms-traffictypediagnostic: SG2APC01HT019: x-microsoft-antispam-message-info: yQc554e2QhQcarFWKyC5Hif7nYq4+M+o6QKG1dsN8W9SRwhYijEPOzIaGrNtO/BWxxJABfJWDM6T9fINixzp8a67XYJMLVUMakJbT2f6tPL7Wo3HgK8vCvoYIEnYfdrhgvHFAiIMpXkiMEXlAJnlsSnHShqbqZR8wSkAoItK6Kw8xK13EhWVGafclj0aL3Vx MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: 54b92de9-73d8-401d-feb2-08d6cc64335f X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Apr 2019 05:33:25.6944 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2APC01HT019 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.92.254.64 Subject: [Qemu-devel] [PATCH v1 4/5] hw/arm: Add the STM32F4xx SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- MAINTAINERS | 8 + default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 3 + hw/arm/Makefile.objs | 1 + hw/arm/stm32f405_soc.c | 292 ++++++++++++++++++++++++++++++++ include/hw/arm/stm32f405_soc.h | 70 ++++++++ 6 files changed, 375 insertions(+) create mode 100644 hw/arm/stm32f405_soc.c create mode 100644 include/hw/arm/stm32f405_soc.h diff --git a/MAINTAINERS b/MAINTAINERS index dabbfccf9c..c9772735cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -803,6 +803,14 @@ F: hw/adc/* F: hw/ssi/stm32f2xx_spi.c F: include/hw/*/stm32*.h +STM32F405 +M: Alistair Francis +M: Peter Maydell +S: Maintained +F: hw/arm/stm32f405_soc.c +F: hw/misc/stm32f4xx_syscfg.c +F: hw/misc/stm32f4xx_exti.c + Netduino 2 M: Alistair Francis M: Peter Maydell diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 8eb57de211..e079f10624 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -98,6 +98,7 @@ CONFIG_STM32F2XX_SPI=y CONFIG_STM32F205_SOC=y CONFIG_STM32F4XX_SYSCFG=y CONFIG_STM32F4XX_EXTI=y +CONFIG_STM32F405_SOC=y CONFIG_NRF51_SOC=y CONFIG_CMSDK_APB_TIMER=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index d298fbdc89..3a98bce15a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -62,6 +62,9 @@ config RASPI config STM32F205_SOC bool +config STM32F405_SOC + bool + config XLNX_ZYNQMP_ARM bool diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index fa57c7c770..36c3ff54c3 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -26,6 +26,7 @@ obj-$(CONFIG_STRONGARM) += strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o +obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c new file mode 100644 index 0000000000..83adec51a2 --- /dev/null +++ b/hw/arm/stm32f405_soc.c @@ -0,0 +1,292 @@ +/* + * STM32F405 SoC + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" +#include "hw/arm/stm32f405_soc.h" +#include "hw/misc/unimp.h" + +#define SYSCFG_ADD 0x40013800 +static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, + 0x40004C00, 0x40005000, 0x40011400, + 0x40007800, 0x40007C00 }; +/* At the moment only Timer 2 to 5 are modelled */ +static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, + 0x40000800, 0x40000C00 }; +#define ADC_ADDR 0x40012000 +static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, + 0x40013400, 0x40015000, 0x40015400 }; +#define EXTI_ADDR 0x40013C00 + +#define SYSCFG_IRQ 71 +static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; +static const int timer_irq[] = { 28, 29, 30, 50 }; +#define ADC_IRQ 18 +static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; +static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, + 40, 40, 40, 40, 40} ; + + +static void stm32f405_soc_initfn(Object *obj) +{ + STM32F405State *s = STM32F405_SOC(obj); + int i; + + sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), + TYPE_ARMV7M); + + sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), + TYPE_STM32F4XX_SYSCFG); + + for (i = 0; i < STM_NUM_USARTS; i++) { + sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], + sizeof(s->usart[i]), TYPE_STM32F2XX_USART); + } + + for (i = 0; i < STM_NUM_TIMERS; i++) { + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], + sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); + } + + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); + + for (i = 0; i < STM_NUM_ADCS; i++) { + sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), + TYPE_STM32F2XX_ADC); + } + + for (i = 0; i < STM_NUM_SPIS; i++) { + sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), + TYPE_STM32F2XX_SPI); + } + + sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti), + TYPE_STM32F4XX_EXTI); +} + +static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) +{ + STM32F405State *s = STM32F405_SOC(dev_soc); + DeviceState *dev, *armv7m; + SysBusDevice *busdev; + Error *err = NULL; + int i; + + MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *sram = g_new(MemoryRegion, 1); + MemoryRegion *flash = g_new(MemoryRegion, 1); + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); + + memory_region_init_ram(flash, NULL, "STM32F405.flash", FLASH_SIZE, + &error_fatal); + memory_region_init_alias(flash_alias, NULL, "STM32F405.flash.alias", + flash, 0, FLASH_SIZE); + + memory_region_set_readonly(flash, true); + memory_region_set_readonly(flash_alias, true); + + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); + memory_region_add_subregion(system_memory, 0, flash_alias); + + memory_region_init_ram(sram, NULL, "STM32F405.sram", SRAM_SIZE, + &error_fatal); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + + armv7m = DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 96); + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_bit(armv7m, "enable-bitband", true); + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), + "memory", &error_abort); + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + /* System configuration controller */ + dev = DEVICE(&s->syscfg); + object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, SYSCFG_ADD); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); + + /* Attach UART (uses USART registers) and USART controllers */ + for (i = 0; i < STM_NUM_USARTS; i++) { + dev = DEVICE(&(s->usart[i])); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, usart_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); + } + + /* Timer 2 to 5 */ + for (i = 0; i < STM_NUM_TIMERS; i++) { + dev = DEVICE(&(s->timer[i])); + qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, timer_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); + } + + /* ADC device, the IRQs are ORed together */ + object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, + "num-lines", &err); + object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, + qdev_get_gpio_in(armv7m, ADC_IRQ)); + + dev = DEVICE(&(s->adc[i])); + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, ADC_ADDR); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); + + /* SPI devices */ + for (i = 0; i < STM_NUM_SPIS; i++) { + dev = DEVICE(&(s->spi[i])); + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, spi_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); + } + + /* EXTI device */ + dev = DEVICE(&s->exti); + object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, EXTI_ADDR); + for (i = 0; i < 16; i++) { + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); + } + for (i = 0; i < 16; i++) { + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); + } + + create_unimplemented_device("timer[6]", 0x40001000, 0x400 - 1); + create_unimplemented_device("timer[7]", 0x40001400, 0x400 - 1); + create_unimplemented_device("timer[12]", 0x40001800, 0x400 - 1); + create_unimplemented_device("timer[13]", 0x40001C00, 0x400 - 1); + create_unimplemented_device("timer[14]", 0x40002000, 0x400 - 1); + create_unimplemented_device("RTC and BKP", 0x40002800, 0x400 - 1); + create_unimplemented_device("WWDG", 0x40002C00, 0x400 - 1); + create_unimplemented_device("IWDG", 0x40003000, 0x400 - 1); + create_unimplemented_device("I2S2ext", 0x40003000, 0x400 - 1); + create_unimplemented_device("I2S3ext", 0x40004000, 0x400 - 1); + create_unimplemented_device("I2C1", 0x40005400, 0x400 - 1); + create_unimplemented_device("I2C2", 0x40005800, 0x400 - 1); + create_unimplemented_device("I2C3", 0x40005C00, 0x400 - 1); + create_unimplemented_device("CAN1", 0x40006400, 0x400 - 1); + create_unimplemented_device("CAN2", 0x40006800, 0x400 - 1); + create_unimplemented_device("PWR", 0x40007000, 0x400 - 1); + create_unimplemented_device("DAC", 0x40007400, 0x400 - 1); + create_unimplemented_device("timer[1]", 0x40010000, 0x400 - 1); + create_unimplemented_device("timer[8]", 0x40010400, 0x400 - 1); + create_unimplemented_device("SDIO", 0x40012C00, 0x400 - 1); + create_unimplemented_device("timer[9]", 0x40014000, 0x400 - 1); + create_unimplemented_device("timer[10]", 0x40014400, 0x400 - 1); + create_unimplemented_device("timer[11]", 0x40014800, 0x400 - 1); + create_unimplemented_device("GPIOA", 0x40020000, 0x400 - 1); + create_unimplemented_device("GPIOB", 0x40020400, 0x400 - 1); + create_unimplemented_device("GPIOC", 0x40020800, 0x400 - 1); + create_unimplemented_device("GPIOD", 0x40020C00, 0x400 - 1); + create_unimplemented_device("GPIOE", 0x40021000, 0x400 - 1); + create_unimplemented_device("GPIOF", 0x40021400, 0x400 - 1); + create_unimplemented_device("GPIOG", 0x40021800, 0x400 - 1); + create_unimplemented_device("GPIOH", 0x40021C00, 0x400 - 1); + create_unimplemented_device("GPIOI", 0x40022000, 0x400 - 1); + create_unimplemented_device("CRC", 0x40023000, 0x400 - 1); + create_unimplemented_device("RCC", 0x40023800, 0x400 - 1); + create_unimplemented_device("Flash Int", 0x40023C00, 0x400 - 1); + create_unimplemented_device("BKPSRAM", 0x40024000, 0x400 - 1); + create_unimplemented_device("DMA1", 0x40026000, 0x400 - 1); + create_unimplemented_device("DMA2", 0x40026400, 0x400 - 1); + create_unimplemented_device("Ethernet", 0x40028000, 0x1400 - 1); + create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000 - 1); + create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000 - 1); + create_unimplemented_device("DCMI", 0x50050000, 0x400 - 1); + create_unimplemented_device("RNG", 0x50060800, 0x400 - 1); +} + +static Property stm32f405_soc_properties[] = { + DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), + DEFINE_PROP_END_OF_LIST(), +}; + +static void stm32f405_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = stm32f405_soc_realize; + dc->props = stm32f405_soc_properties; +} + +static const TypeInfo stm32f405_soc_info = { + .name = TYPE_STM32F405_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F405State), + .instance_init = stm32f405_soc_initfn, + .class_init = stm32f405_soc_class_init, +}; + +static void stm32f405_soc_types(void) +{ + type_register_static(&stm32f405_soc_info); +} + +type_init(stm32f405_soc_types) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h new file mode 100644 index 0000000000..f0aec53d32 --- /dev/null +++ b/include/hw/arm/stm32f405_soc.h @@ -0,0 +1,70 @@ +/* + * STM32F405 SoC + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_ARM_STM32F405_SOC_H +#define HW_ARM_STM32F405_SOC_H + +#include "hw/misc/stm32f4xx_syscfg.h" +#include "hw/timer/stm32f2xx_timer.h" +#include "hw/char/stm32f2xx_usart.h" +#include "hw/adc/stm32f2xx_adc.h" +#include "hw/misc/stm32f4xx_exti.h" +#include "hw/or-irq.h" +#include "hw/ssi/stm32f2xx_spi.h" +#include "hw/arm/armv7m.h" + +#define TYPE_STM32F405_SOC "stm32f405-soc" +#define STM32F405_SOC(obj) \ + OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) + +#define STM_NUM_USARTS 7 +#define STM_NUM_TIMERS 4 +#define STM_NUM_ADCS 6 +#define STM_NUM_SPIS 6 + +#define FLASH_BASE_ADDRESS 0x08000000 +#define FLASH_SIZE (1024 * 1024) +#define SRAM_BASE_ADDRESS 0x20000000 +#define SRAM_SIZE (192 * 1024) + +typedef struct STM32F405State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + char *cpu_type; + + ARMv7MState armv7m; + + STM32F4xxSyscfgState syscfg; + STM32F4xxExtiState exti; + STM32F2XXUsartState usart[STM_NUM_USARTS]; + STM32F2XXTimerState timer[STM_NUM_TIMERS]; + STM32F2XXADCState adc[STM_NUM_ADCS]; + STM32F2XXSPIState spi[STM_NUM_SPIS]; + + qemu_or_irq *adc_irqs; +} STM32F405State; + +#endif From patchwork Mon Apr 29 05:33:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1092416 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=alistair23.me Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44stkx5x1qz9s7T for ; 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Mon, 29 Apr 2019 05:33:39 +0000 Received: from PSXP216MB0277.KORP216.PROD.OUTLOOK.COM (10.152.252.56) by PU1APC01FT057.mail.protection.outlook.com (10.152.253.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1835.13 via Frontend Transport; Mon, 29 Apr 2019 05:33:39 +0000 Received: from PSXP216MB0277.KORP216.PROD.OUTLOOK.COM ([fe80::d5cf:d2af:3aea:e2a3]) by PSXP216MB0277.KORP216.PROD.OUTLOOK.COM ([fe80::d5cf:d2af:3aea:e2a3%3]) with mapi id 15.20.1835.018; Mon, 29 Apr 2019 05:33:38 +0000 From: Alistair Francis To: "qemu-devel@nongnu.org" Thread-Topic: [PATCH v1 5/5] hw/arm: Add the Netduino Plus 2 Thread-Index: AQHU/k0ZzptDvPD+1U6L6aru7zHWWg== Date: Mon, 29 Apr 2019 05:33:38 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-AU, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR02CA0008.namprd02.prod.outlook.com (2603:10b6:a02:ee::21) To PSXP216MB0277.KORP216.PROD.OUTLOOK.COM (2603:1096:300:a::18) x-incomingtopheadermarker: OriginalChecksum:83938E20C9C607DF476504A32348826778B06D6CD084A164A6DCAB55D7EBB26C; UpperCasedChecksum:45CABC4A613EFF97A9E519FCAA54B8CC6E443192B66534A1A0F7A22D3E93DDE9; SizeAsReceived:7502; Count:50 x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.21.0 x-tmn: [sCbaDkStg/yD3WsutGwZ2Yk1TJgxYJwLgSoq7ShJFyPHjbL8XeeHCwlSXMlC6dDK] x-microsoft-original-message-id: x-ms-publictraffictype: Email x-incomingheadercount: 50 x-eopattributedmessage: 0 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(5050001)(7020095)(20181119110)(201702061078)(5061506573)(5061507331)(1603103135)(2017031320274)(2017031323274)(2017031324274)(2017031322404)(1601125500)(1603101475)(1701031045); SRVR:PU1APC01HT070; x-ms-traffictypediagnostic: PU1APC01HT070: x-microsoft-antispam-message-info: Yagh8Ed8By98yEhvD/zvroBgmsdWDOfmTcFqPrYj3RtrS0t2A2h4G2Rac8ifH1FIkdJc7XOZhE4YrCDgb3d3jwB9uMRj85rtk2HRsM941VuiywpwiGdESkY67u3ccaqsOqSDL/Dt5vJlVdnDvEnJNniW/t5xWnn4B4EqyxA71+tfY1/OgfFyK7hQJaNJRKHH MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: 019bf201-c930-4992-58c1-08d6cc643b45 X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Apr 2019 05:33:38.9025 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: PU1APC01HT070 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.92.255.63 Subject: [Qemu-devel] [PATCH v1 5/5] hw/arm: Add the Netduino Plus 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- MAINTAINERS | 6 +++ default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 3 ++ hw/arm/Makefile.objs | 1 + hw/arm/netduinoplus2.c | 77 +++++++++++++++++++++++++++++++++ 5 files changed, 88 insertions(+) create mode 100644 hw/arm/netduinoplus2.c diff --git a/MAINTAINERS b/MAINTAINERS index c9772735cf..9b0af5a0b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -817,6 +817,12 @@ M: Peter Maydell S: Maintained F: hw/arm/netduino2.c +Netduino Plus 2 +M: Alistair Francis +M: Peter Maydell +S: Maintained +F: hw/arm/netduinoplus2.c + SmartFusion2 M: Subbaraya Sundeep M: Peter Maydell diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index e079f10624..1e2c82f201 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -46,6 +46,7 @@ CONFIG_A15MPCORE=y CONFIG_ARM_V7M=y CONFIG_NETDUINO2=y +CONFIG_NETDUINOPLUS2=y CONFIG_ARM_GIC=y CONFIG_ARM_TIMER=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3a98bce15a..13fc779308 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -26,6 +26,9 @@ config MUSICPAL config NETDUINO2 bool +config NETDUINOPLUS2 + bool + config NSERIES bool diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 36c3ff54c3..1f216f4d93 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_INTEGRATOR) += integratorcp.o obj-$(CONFIG_MAINSTONE) += mainstone.o obj-$(CONFIG_MUSICPAL) += musicpal.o obj-$(CONFIG_NETDUINO2) += netduino2.o +obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o obj-$(CONFIG_NSERIES) += nseries.o obj-$(CONFIG_OMAP) += omap_sx1.o palm.o obj-$(CONFIG_PXA2XX) += gumstix.o spitz.o tosa.o z2.o diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c new file mode 100644 index 0000000000..1f585cf09f --- /dev/null +++ b/hw/arm/netduinoplus2.c @@ -0,0 +1,77 @@ +/* + * Netduino Plus 2 Machine Model + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "qemu/error-report.h" +#include "hw/arm/stm32f405_soc.h" +#include "hw/arm/arm.h" + +typedef struct ARMV7MResetArgs { + ARMCPU *cpu; + uint32_t reset_sp; + uint32_t reset_pc; +} ARMV7MResetArgs; + +static void armv7m_reset(void *opaque) +{ + ARMV7MResetArgs *args = opaque; + + cpu_reset(CPU(args->cpu)); + + args->cpu->env.regs[13] = args->reset_sp & 0xFFFFFFFC; + args->cpu->env.thumb = args->reset_pc & 1; + args->cpu->env.regs[15] = args->reset_pc & ~1; +} + +static void netduinoplus2_init(MachineState *machine) +{ + DeviceState *dev; + ARMV7MResetArgs reset_args; + uint64_t entry; + + dev = qdev_create(NULL, TYPE_STM32F405_SOC); + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + FLASH_SIZE, &entry); + + reset_args = (ARMV7MResetArgs) { + .cpu = ARM_CPU(first_cpu), + .reset_pc = entry, + .reset_sp = (SRAM_BASE_ADDRESS + (SRAM_SIZE * 2) / 3), + }; + qemu_register_reset(armv7m_reset, + g_memdup(&reset_args, sizeof(reset_args))); +} + +static void netduinoplus2_machine_init(MachineClass *mc) +{ + mc->desc = "Netduino Plus 2 Machine"; + mc->init = netduinoplus2_init; +} + +DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)