From patchwork Fri Apr 26 12:40:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajat Srivastava X-Patchwork-Id: 1091524 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44rDGC3BXLz9s7T for ; Fri, 26 Apr 2019 22:42:11 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D7F03C21EFF; Fri, 26 Apr 2019 12:42:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 511C8C21C57; Fri, 26 Apr 2019 12:42:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 09409C21C57; Fri, 26 Apr 2019 12:42:00 +0000 (UTC) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lists.denx.de (Postfix) with ESMTPS id 92FC1C21C4A for ; Fri, 26 Apr 2019 12:42:00 +0000 (UTC) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id BF8522002B5; Fri, 26 Apr 2019 14:41:59 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id ED21E200068; Fri, 26 Apr 2019 14:41:56 +0200 (CEST) Received: from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id D43D4402AB; Fri, 26 Apr 2019 20:41:52 +0800 (SGT) From: Rajat Srivastava To: u-boot@lists.denx.de, vigneshr@ti.com, jagan@openedev.com Date: Fri, 26 Apr 2019 18:10:44 +0530 Message-Id: <20190426124044.13341-1-rajat.srivastava@nxp.com> X-Mailer: git-send-email 2.17.1 X-Virus-Scanned: ClamAV using ClamSMTP Cc: Rajat Srivastava Subject: [U-Boot] [PATCH v2] fsl_qspi: Improve QSPI driver to incorporate 4 byte commands X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Previously, the SPI framework supported only 3-byte opcodes but the FSL QSPI controller used to deal with flashes that work with 4-byte opcodes. As a workaround to resolve this, for every 3-byte opcodes sent by framework FSL QSPI driver used to explicitly send corresponding 4-byte opcodes. Now the framework has been updated to send 4-byte opcodes and FSL QSPI driver needs correction. This change will be applicable for the following defconfig where we disable CONFIG_FLASH_BAR: LS1088A, LS1046A, LS1043A, LS1012A, LS2088A defconfigs Signed-off-by: Ashish Kumar Signed-off-by: Rajat Srivastava --- Changes in v2: - Update commit message - Reduce patchset to one patch - This patch is no more applicable: https://patchwork.ozlabs.org/patch/1090122/ drivers/spi/fsl_qspi.c | 45 +++++++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 14 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 1598c4f698..217005f525 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -26,7 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUFFER_SIZE 0x40 #endif -#define OFFSET_BITS_MASK GENMASK(23, 0) +#define OFFSET_BITS_MASK GENMASK(27, 0) +#define OFFSET_BITS_MASK_24 GENMASK(23, 0) #define FLASH_STATUS_WEL 0x02 @@ -754,7 +755,8 @@ static void qspi_op_erase(struct fsl_qspi_priv *priv) while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) ; - if (priv->cur_seqid == QSPI_CMD_SE) { + if ((priv->cur_seqid == QSPI_CMD_SE_4B) || + (priv->cur_seqid == QSPI_CMD_SE)) { qspi_write32(priv->flags, ®s->ipcr, (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); } else if (priv->cur_seqid == QSPI_CMD_BE_4K) { @@ -775,31 +777,44 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, u32 txbuf; WATCHDOG_RESET(); - if (dout) { if (flags & SPI_XFER_BEGIN) { priv->cur_seqid = *(u8 *)dout; - memcpy(&txbuf, dout, 4); + if (FSL_QSPI_FLASH_SIZE > SZ_16M && bytes > 4) + memcpy(&txbuf, dout + 1, 4); + else + memcpy(&txbuf, dout, 4); } if (flags == SPI_XFER_END) { priv->sf_addr = wr_sfaddr; - qspi_op_write(priv, (u8 *)dout, bytes); - return 0; + if (priv->cur_seqid == QSPI_CMD_PP || + priv->cur_seqid == QSPI_CMD_PP_4B || + priv->cur_seqid == QSPI_CMD_WRAR) { + qspi_op_write(priv, (u8 *)dout, bytes); + return 0; + } } - if (priv->cur_seqid == QSPI_CMD_FAST_READ || - priv->cur_seqid == QSPI_CMD_RDAR) { + if ((priv->cur_seqid == QSPI_CMD_FAST_READ) || + (priv->cur_seqid == QSPI_CMD_FAST_READ_4B)) { priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + } else if (priv->cur_seqid == QSPI_CMD_RDAR) { + priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK_24; } else if ((priv->cur_seqid == QSPI_CMD_SE) || - (priv->cur_seqid == QSPI_CMD_BE_4K)) { + priv->cur_seqid == QSPI_CMD_SE_4B) { priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; qspi_op_erase(priv); + } else if (priv->cur_seqid == QSPI_CMD_BE_4K) { + priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK_24; + qspi_op_erase(priv); } else if (priv->cur_seqid == QSPI_CMD_PP || - priv->cur_seqid == QSPI_CMD_WRAR) { + priv->cur_seqid == QSPI_CMD_PP_4B) { wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; + } else if (priv->cur_seqid == QSPI_CMD_WRAR) { + wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK_24; } else if ((priv->cur_seqid == QSPI_CMD_BRWR) || - (priv->cur_seqid == QSPI_CMD_WREAR)) { + (priv->cur_seqid == QSPI_CMD_WREAR)) { #ifdef CONFIG_SPI_FLASH_BAR wr_sfaddr = 0; #endif @@ -807,7 +822,8 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, } if (din) { - if (priv->cur_seqid == QSPI_CMD_FAST_READ) { + if ((priv->cur_seqid == QSPI_CMD_FAST_READ) || + (priv->cur_seqid == QSPI_CMD_FAST_READ_4B)) { #ifdef CONFIG_SYS_FSL_QSPI_AHB qspi_ahb_read(priv, din, bytes); #else @@ -815,10 +831,11 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, #endif } else if (priv->cur_seqid == QSPI_CMD_RDAR) { qspi_op_read(priv, din, bytes); - } else if (priv->cur_seqid == QSPI_CMD_RDID) + } else if (priv->cur_seqid == QSPI_CMD_RDID) { qspi_op_rdid(priv, din, bytes); - else if (priv->cur_seqid == QSPI_CMD_RDSR) + } else if (priv->cur_seqid == QSPI_CMD_RDSR) { qspi_op_rdsr(priv, din, bytes); + } #ifdef CONFIG_SPI_FLASH_BAR else if ((priv->cur_seqid == QSPI_CMD_BRRD) || (priv->cur_seqid == QSPI_CMD_RDEAR)) {