From patchwork Tue Apr 23 08:27:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1089163 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="N7JGJtN8"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44pGn00nJrz9sNp for ; Tue, 23 Apr 2019 18:28:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726995AbfDWI23 (ORCPT ); Tue, 23 Apr 2019 04:28:29 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:2675 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725955AbfDWI22 (ORCPT ); Tue, 23 Apr 2019 04:28:28 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 23 Apr 2019 01:28:24 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 23 Apr 2019 01:28:27 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 23 Apr 2019 01:28:27 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Apr 2019 08:28:27 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 23 Apr 2019 08:28:26 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 23 Apr 2019 01:28:26 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH V4 07/16] dt-bindings: PCI: designware: Add binding for CDM register check Date: Tue, 23 Apr 2019 13:57:21 +0530 Message-ID: <20190423082730.370-8-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com> References: <20190423082730.370-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1556008104; bh=xTl5RIwgjaCZu0twYuvvVohSzfNXHEAMQmXhnEV2rEg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=N7JGJtN8rdAS6d3a3svku+sUtIhmXzDvjmg5V6md3CncLICEZSC/kjFzsq2/w6Om7 elP3JHLmF9So7lonU2Zu8ESp/jhRLgZzI1rE5pqA6ZZdMp0Co6XwhwFt+XDyOYV27n xaiWP8WwIMiaZwjOQaSDU31juMsGNuqOMDmoTi25HI99ncLpTGNi+lLSBFoV57HhJ1 hST144j9fjQVNORGrNJbb+veUOYeqPn7UCV5M/tjB9+eOZHJnE65il/I8xjFAxHe9k Vtmu4SfxzWM7MT3D96O420Qtx9kWs8A3SYeRB55cXTNsv+ZjrdCJt/9aEGIPxbUmrP DSKoG3obqMsTQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to enable CDM (Configuration Dependent Module) registers check for any data corruption. CDM registers include standard PCIe configuration space registers, Port Logic registers and iATU and DMA registers. Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook Version 4.90a Signed-off-by: Vidya Sagar --- Changes since [v3]: * None Changes since [v2]: * Changed flag name from 'cdm-check' to 'enable-cdm-check' * Added info about Port Logic and DMA registers being part of CDM Changes since [v1]: * This is a new patch in v2 series Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 5561a1c060d0..85b872c42a9f 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -34,6 +34,11 @@ Optional properties: - clock-names: Must include the following entries: - "pcie" - "pcie_bus" +- enable-cdm-check: This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. RC mode: - num-viewport: number of view ports configured in hardware. If a platform does not specify it, the driver assumes 2. From patchwork Tue Apr 23 08:27:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1089168 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="i0P1u3ey"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44pGnF0H5Pz9sNp for ; Tue, 23 Apr 2019 18:28:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727068AbfDWI2m (ORCPT ); Tue, 23 Apr 2019 04:28:42 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6683 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725955AbfDWI2l (ORCPT ); Tue, 23 Apr 2019 04:28:41 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 23 Apr 2019 01:28:16 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 23 Apr 2019 01:28:40 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 23 Apr 2019 01:28:40 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Apr 2019 08:28:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 23 Apr 2019 08:28:40 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 23 Apr 2019 01:28:40 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH V4 09/16] Documentation/devicetree: Add PCIe supports-clkreq property Date: Tue, 23 Apr 2019 13:57:23 +0530 Message-ID: <20190423082730.370-10-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com> References: <20190423082730.370-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1556008096; bh=ghDB46m7MQmbP30Yt7OzC1k71/KVBendJlvfWTbSp8c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=i0P1u3eyL6JjGNP7BjoeJ12e3hRokt8xbbi6D+8a0geXCClzNljaoQf5nY5j5lLPv E6E4R0N6ia5KY5Bg1f5jKq6pj2Jfe4q8Q28LmhQa+fl9UpsA9wvqAu0I6AHp5iawc5 DHrVEtwNnRGqOYhUTr6JmfT+6Tp98q+c/ayI+hVkod+kpbhYujMnmpmTYdoi8FhvQh TkGQrFv1bNANf5L+JmjgDFNkBAfm73vuA/s6OviIB5HcEMve2nmuZxnRcdJSIG6GII q6Zu5G9qN47NeuRFOv7g9bUaiKXKT1zHBDZ4EHjorEqbL4B/VwKPhH5rOicDxMDRX/ V7k95sTe3xWfw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some host controllers need to know the existence of clkreq signal routing to downstream devices to be able to advertise low power features like ASPM L1 substates. Without clkreq signal routing being present, enabling ASPM L1 sub states might lead to downstream devices falling off the bus. Hence a new device tree property 'supports-clkreq' is added to make such host controllers aware of clkreq signal routing to downstream devices. Signed-off-by: Vidya Sagar --- Changes since [v3]: * Rebased on top of linux-next top of the tree Changes since [v2]: * None Changes since [v1]: * This is a new patch in v2 series Documentation/devicetree/bindings/pci/pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 92c01db610df..d132f9efeb3e 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -24,6 +24,11 @@ driver implementation may support the following properties: unsupported link speed, for instance, trying to do training for unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are invalid. +- supports-clkreq: + If present this property specifies that CLKREQ signal routing exists from + root port to downstream device and host bridge drivers can do programming + which depends on CLKREQ signal existence. For example, programming root port + not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. PCI-PCI Bridge properties ------------------------- From patchwork Tue Apr 23 08:27:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1089172 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="llJQTQ/j"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44pGnM6QVMz9sNp for ; Tue, 23 Apr 2019 18:28:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727111AbfDWI2u (ORCPT ); Tue, 23 Apr 2019 04:28:50 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:3439 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727105AbfDWI2u (ORCPT ); Tue, 23 Apr 2019 04:28:50 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 23 Apr 2019 01:28:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 23 Apr 2019 01:28:47 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 23 Apr 2019 01:28:47 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Apr 2019 08:28:47 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Apr 2019 08:28:46 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 23 Apr 2019 08:28:46 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 23 Apr 2019 01:28:46 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH V4 10/16] dt-bindings: PCI: tegra: Add device tree support for T194 Date: Tue, 23 Apr 2019 13:57:24 +0530 Message-ID: <20190423082730.370-11-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com> References: <20190423082730.370-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1556008133; bh=0FOMvqqBDS+DddA+4zOu8VeOZWTLJr1tRx3t9/pD5b4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=llJQTQ/j7XkWk3BOVbo8jU9aCFVmD5FXW9/ZmUfkjRl6S2gP7Q9jY9Zpulg8GJLJT nku4NYwE5QsphNg6GYmmhMTTVRxLoSIy5bCtY1fGTUiT1Q8e1NccdeLr/9RnQGPP6m IYIuOWjFPcROizR94WctbEnQBrEqCHsY7kuMvAwoeXlFbe//tcDpyaZhUoj+5t+87w 4DjqlnO8h8XwR40rEcWYzepTtc5Mke7VkkvZUySJNk79UrKAi1MLIiiU6wbRFY7NGE J1yR6e9N9hW2Mni6Mp7NXHueLO+vpmBLHpCqkaF1JLlErEL1+kcg5PJh+bWprLCUUu z05o+ieKmqsAQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Tegra194 PCIe controllers. These controllers are based on Synopsys DesignWare core IP. Signed-off-by: Vidya Sagar --- Changes since [v3]: * None Changes since [v2]: * Using only 'Cx' (x-being controller number) format to represent a controller * Changed to 'value: description' format where applicable * Changed 'nvidia,init-speed' to 'nvidia,init-link-speed' * Provided more documentation for 'nvidia,init-link-speed' property * Changed 'nvidia,pex-wake' to 'nvidia,wake-gpios' Changes since [v1]: * Added documentation for 'power-domains' property * Removed 'window1' and 'window2' properties * Removed '_clk' and '_rst' from clock and reset names * Dropped 'pcie' from phy-names * Added entry for BPMP-FW handle * Removed offsets for some of the registers and added them in code and would be pickedup based on controller ID * Changed 'nvidia,max-speed' to 'max-link-speed' and is made as an optional * Changed 'nvidia,disable-clock-request' to 'supports-clkreq' with inverted operation * Added more documentation for 'nvidia,update-fc-fixup' property * Removed 'nvidia,enable-power-down' and 'nvidia,plat-gpios' properties * Added '-us' to all properties that represent time in microseconds * Moved P2U documentation to a separate file .../bindings/pci/nvidia,tegra194-pcie.txt | 187 ++++++++++++++++++ 1 file changed, 187 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt new file mode 100644 index 000000000000..208dff126108 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -0,0 +1,187 @@ +NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) + +This PCIe host controller is based on the Synopsis Designware PCIe IP +and thus inherits all the common properties defined in designware-pcie.txt. + +Required properties: +- compatible: For Tegra19x, must contain "nvidia,tegra194-pcie". +- device_type: Must be "pci" +- power-domains: A phandle to the node that controls power to the respective + PCIe controller and a specifier name for the PCIe controller. Following are + the specifiers for the different PCIe controllers + TEGRA194_POWER_DOMAIN_PCIEX8B: C0 + TEGRA194_POWER_DOMAIN_PCIEX1A: C1 + TEGRA194_POWER_DOMAIN_PCIEX1A: C2 + TEGRA194_POWER_DOMAIN_PCIEX1A: C3 + TEGRA194_POWER_DOMAIN_PCIEX4A: C4 + TEGRA194_POWER_DOMAIN_PCIEX8A: C5 + these specifiers are defined in + "include/dt-bindings/power/tegra194-powergate.h" file. +- reg: A list of physical base address and length for each set of controller + registers. Must contain an entry for each entry in the reg-names property. +- reg-names: Must include the following entries: + "appl": Controller's application logic registers + "config": As per the definition in designware-pcie.txt + "atu_dma": iATU and DMA registers. This is where the iATU (internal Address + Translation Unit) registers of the PCIe core are made available + fow SW access. + "dbi": The aperture where root port's own configuration registers are + available +- interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. +- interrupt-names: Must include the following entries: + "intr": The Tegra interrupt that is asserted for controller interrupts + "msi": The Tegra interrupt that is asserted when an MSI is received +- bus-range: Range of bus numbers associated with this controller +- #address-cells: Address representation for root ports (must be 3) + - cell 0 specifies the bus and device numbers of the root port: + [23:16]: bus number + [15:11]: device number + - cell 1 denotes the upper 32 address bits and should be 0 + - cell 2 contains the lower 32 address bits and is used to translate to the + CPU address space +- #size-cells: Size representation for root ports (must be 2) +- ranges: Describes the translation of addresses for root ports and standard + PCI regions. The entries must be 7 cells each, where the first three cells + correspond to the address as described for the #address-cells property + above, the fourth and fifth cells are for the physical CPU address to + translate to and the sixth and seventh cells are as described for the + #size-cells property above. + - Entries setup the mapping for the standard I/O, memory and + prefetchable PCI regions. The first cell determines the type of region + that is setup: + - 0x81000000: I/O memory region + - 0x82000000: non-prefetchable memory region + - 0xc2000000: prefetchable memory region + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- #interrupt-cells: Size representation for interrupts (must be 1) +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - core +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + - core_apb + - core +- phys: Must contain a phandle to P2U PHY for each entry in phy-names. +- phy-names: Must include an entry for each active lane. + "p2u-N": where N ranges from 0 to one less than the total number of lanes +- nvidia,bpmp: Must contain a phandle to BPMP controller node. +- nvidia,controller-id : Controller specific ID + 0: C0 + 1: C1 + 2: C2 + 3: C3 + 4: C4 + 5: C5 +- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals + +Optional properties: +- max-link-speed: Limits controllers max speed to this value. For more info, + please refer to Documentation/devicetree/bindings/pci/pci.txt file. +- nvidia,init-link-speed: Limits controllers init speed to this value. It means + that link is brought up to the speed specified by this property initially by + hardware (provided connected end point also supports that). Since the + controller continues to advertise maximum supported link speed set up + through max-link-speed property (Gen-4 if max-link-speed is not present) in + its configuration space, software can take link the desired speed at a later + point of time by spec defined speed change mechanism. + 1: Gen-1 (2.5 GT/s) + 2: Gen-2 (5 GT/s) + 3: Gen-3 (8 GT/s) + 4: Gen-4 (16 GT/s) +- nvidia,disable-aspm-states: Controls advertisement of ASPM states + bit-0 to '1': Disables advertisement of ASPM-L0s + bit-1 to '1': Disables advertisement of ASPM-L1. This also disables + advertisement of ASPM-L1.1 and ASPM-L1.2 + bit-2 to '1': Disables advertisement of ASPM-L1.1 + bit-3 to '1': Disables advertisement of ASPM-L1.2 +- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt +- nvidia,update-fc-fixup: This is a boolean property and needs to be present to + improve perf when a platform is designed in such a way that it satisfies at + least one of the following conditions thereby enabling root port to + exchange optimum number of FC (Flow Control) credits with downstream devices + 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) + 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and + a) speed is Gen-2 and MPS is 256B + b) speed is >= Gen-3 with any MPS +- "nvidia,wake-gpios": Add PEX_WAKE GPIO pin. It contains phandle to GPIO + controller followed by GPIO specifier. + Refer ../gpio/nvidia,tegra186-gpio.txt for more info. +- "nvidia,aspm-cmrt-us": Common Mode Restore time for proper operation of ASPM + to be specified in microseconds +- "nvidia,aspm-pwr-on-t-us": Power On time for proper operation of ASPM to be + specified in microseconds +- "nvidia,aspm-l0s-entrance-latency-us": ASPM L0s entrance latency to be + specified in microseconds + +Examples: +========= + +Tegra194: +-------- + +SoC DTSI: + + pcie@14180000 { + compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ + 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ + 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */ + reg-names = "appl", "config", "atu_dma"; + + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + linux,pci-domain = <0>; + + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; + clock-names = "core"; + + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_0>; + reset-names = "core_apb", "core"; + + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 72 0x04>; + + nvidia,bpmp = <&bpmp>; + + supports-clkreq; + nvidia,disable-aspm-states = <0xf>; + nvidia,controller-id = <0>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ + 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */ + 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */ + }; + +Board DTS: + + pcie@14180000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, + <&p2u_hsio_5>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; From patchwork Tue Apr 23 08:27:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1089175 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="J4QWw+fV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44pGnV0s9Yz9sBp for ; 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Tue, 23 Apr 2019 08:28:53 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 23 Apr 2019 01:28:53 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH V4 11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block Date: Tue, 23 Apr 2019 13:57:25 +0530 Message-ID: <20190423082730.370-12-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com> References: <20190423082730.370-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1556008110; bh=e4y3GVwYyoc5tTHi1u0vhFYjXSAjhOmxVmDxHjTavBk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=J4QWw+fV0RvnybZU6GbmU1AMWq1RkubFo89y3LcGoDtoNnxn2ywPZMcRwjQtxPtxl GwGPzUJQOK7LicSAoj3Nv961zzlqqxpdt2VOiaA6CWGjpNuVhRjf99+frOwwXoCd4z 83RAej1WJUgA449HBWHDPVHHh/lSh19FuFGxw9TthidoCC/BRGbzXRhbVqi0Ed1evR wpNfCqikiSSbYDbaO7pvFPte6ejYz5r6D95Kx1tOjeVA7RssiyQwD9mAPIkQVa3/8I 6qPHFlUc/XpMjZo+9aK9sBA5HOJ1mjOCukvg3ZCoJW+jutDAL6RollZyTGMv6dagWq 4rFlPS7vB3FpA== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue module instantiated one for each PCIe lane between Synopsys Designware core based PCIe IP and Universal PHY block. --- Changes since [v3]: * None Changes since [v2]: * Changed node label to reflect new format that includes either 'hsio' or 'nvhs' in its name to reflect which UPHY brick they belong to Changes since [v1]: * This is a new patch in v2 series .../bindings/phy/phy-tegra194-p2u.txt | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt new file mode 100644 index 000000000000..8b543cba483b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt @@ -0,0 +1,28 @@ +NVIDIA Tegra194 P2U binding + +Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High +Speed) each interfacing with 12 and 8 P2U instances respectively. +A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE +interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe +lane. + +Required properties: +- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u". +- reg: Should be the physical address space and length of respective each P2U + instance. +- reg-names: Must include the entry "ctl". + +Required properties for PHY port node: +- #phy-cells: Defined by generic PHY bindings. Must be 0. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Example: + +p2u_hsio_0: p2u@3e10000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e10000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; +};