From patchwork Tue Apr 23 05:48:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ran Wang X-Patchwork-Id: 1089069 X-Patchwork-Delegate: prabhakar@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="unYg+yO3"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44pCFw474hz9sB3 for ; Tue, 23 Apr 2019 15:49:56 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 4B6EDC21E50; Tue, 23 Apr 2019 05:49:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 74DB8C21DFB; Tue, 23 Apr 2019 05:49:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EEBFEC21E35; Tue, 23 Apr 2019 05:48:19 +0000 (UTC) Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80081.outbound.protection.outlook.com [40.107.8.81]) by lists.denx.de (Postfix) with ESMTPS id 29E10C21DF3 for ; Tue, 23 Apr 2019 05:48:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uA/yuRYvb9vPsEtaNATNswSMSmkmPNSM75ymHZyWpoE=; b=unYg+yO3U+fR5GNkTR0N76TI0JMZBWGt6uSxsC0H9kva39TRPM9vPLvYyq2jWcxS5SJ0InUugFGrP3H8K+BfDILS5cRGrROASZsq4n80EZ/SWpf+vv1cW63bS0qlIyrQJYgKPJj2cfJ47VgTC4ArIS+o73haz79BIWs/tvxDsl8= Received: from HE1PR0402MB2874.eurprd04.prod.outlook.com (10.175.30.147) by HE1PR0402MB2795.eurprd04.prod.outlook.com (10.175.35.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1813.18; Tue, 23 Apr 2019 05:48:16 +0000 Received: from HE1PR0402MB2874.eurprd04.prod.outlook.com ([fe80::3925:cd0b:355a:c587]) by HE1PR0402MB2874.eurprd04.prod.outlook.com ([fe80::3925:cd0b:355a:c587%2]) with mapi id 15.20.1813.017; Tue, 23 Apr 2019 05:48:16 +0000 From: Ran Wang To: Albert Aribaud , Prabhakar Kushwaha Thread-Topic: [PATCH] armv8: Add workaround for USB erratum A-050106 Thread-Index: AQHU+ZglJnUasgLkGUKbyPWwxCI62A== Date: Tue, 23 Apr 2019 05:48:16 +0000 Message-ID: <20190423054943.13168-1-ran.wang_1@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK0PR01CA0043.apcprd01.prod.exchangelabs.com (2603:1096:203:3e::31) To HE1PR0402MB2874.eurprd04.prod.outlook.com (2603:10a6:3:d7::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=ran.wang_1@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a7825c36-8e4b-418b-fecb-08d6c7af47f7 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600141)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:HE1PR0402MB2795; x-ms-traffictypediagnostic: HE1PR0402MB2795: x-microsoft-antispam-prvs: x-forefront-prvs: 0016DEFF96 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(39860400002)(396003)(346002)(376002)(136003)(189003)(199004)(52116002)(4326008)(14454004)(3846002)(6436002)(53936002)(6636002)(66066001)(478600001)(6512007)(7736002)(6486002)(305945005)(6116002)(97736004)(68736007)(71190400001)(71200400001)(50226002)(54906003)(316002)(2906002)(186003)(5660300002)(1076003)(8936002)(36756003)(73956011)(25786009)(14444005)(66946007)(66556008)(64756008)(66476007)(66446008)(26005)(2616005)(486006)(81156014)(8676002)(81166006)(102836004)(86362001)(256004)(99286004)(386003)(6506007)(110136005)(476003); DIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR0402MB2795; H:HE1PR0402MB2874.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 8uNK/BKncJeqc8YvB6k74CxkvsTtLJc9pSssa5eVvhbGod8AElCQpZFzr8KrmGe4xil6m8kHb2KYti93vziFiAFTNLZbzlczoVFNH06BHx2eK0xZ1NccgR/cIYEyx8n0DuCDqVYfyBxc45ZAY8jIdwv41MV/8vaCNQTJWgxF9PYE0jH6Dn7xiRfF+/ip2qphZ+JZEs7ZgcnNv7dQPdEelZTAg4CYpmyeixeCA3lgA4nxL2ZYCWlZ1baeFWq9tqweRhQSn8x94HQfLDEVlnMXV5adCz0z8iv5DmCyrjo7eZ/m95rRrGeTaPXnKQM+FGIcJVeJthkXDLtjI9daWUk2Mv1OwpZOY6rUD3fAmycpOoqSItlKw0DYiGgTaoL3Mep0yNOU80JgkJZZyz0go6lqt4bhLOzndsVirX6Boz64Idg= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a7825c36-8e4b-418b-fecb-08d6c7af47f7 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Apr 2019 05:48:16.3866 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB2795 Cc: "u-boot@lists.denx.de" , York Sun , Ran Wang Subject: [U-Boot] [PATCH] armv8: Add workaround for USB erratum A-050106 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar to erratum A-009007, but this one is for LX2160A, and the register value is different. Signed-off-by: Ran Wang --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 13 ++++++++++++- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 5 +++++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f48481f465..f99b9d1a7a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -191,6 +191,7 @@ config ARCH_LX2160A select SYS_FSL_DDR_VER_50 select SYS_FSL_EC1 select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A050106 select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_SEC select SYS_FSL_HAS_CCN508 @@ -335,6 +336,9 @@ config SYS_FSL_ERRATUM_A009008 config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798" +config SYS_FSL_ERRATUM_A050106 + bool "Workaround for USB PHY erratum A050106" + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 06f3edb302..040d74dab5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -139,7 +139,8 @@ static void erratum_a008997(void) out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LX2160A) #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -171,6 +172,15 @@ static void erratum_a009007(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ } +static void erratum_a050106(void) +{ +#if defined(CONFIG_ARCH_LX2160A) + void __iomem *dcsr = (void __iomem *)DCSR_BASE; + + PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); + PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2); +#endif +} #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -323,6 +333,7 @@ void fsl_lsch3_early_init_f(void) erratum_a009798(); erratum_a008997(); erratum_a009007(); + erratum_a050106(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 9fab88ab2f..572765628a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -209,8 +209,13 @@ #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C #define USB_PHY_RX_EQ_VAL_1 0x0000 #define USB_PHY_RX_EQ_VAL_2 0x0080 +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) #define USB_PHY_RX_EQ_VAL_3 0x0380 #define USB_PHY_RX_EQ_VAL_4 0x0b80 +#elif defined(CONFIG_ARCH_LX2160A) +#define USB_PHY_RX_EQ_VAL_3 0x0080 +#define USB_PHY_RX_EQ_VAL_4 0x0880 +#endif #define TP_ITYP_AV 0x00000001 /* Initiator available */ #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */