From patchwork Tue Apr 16 17:10:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 1086429 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="sSsTiJC4"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=synopsys.com header.i=@synopsys.com header.b="IgwByiYB"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44kBhZ4PmGz9s71 for ; Wed, 17 Apr 2019 03:10:38 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Wk824y9GKrt6qfG1ziKxKBt05tv2zi5AbLh6Tv4Ud/8=; b=sSsTiJC4pg0nZs5L1eYrnzmjMs w8QFZSlnaP6jx6bJTajPgk2iCf8edyZ3FUoxQ6WDEikeKke6gHtgJWj64g4SOV5K5dAmel5nrHOGw S+zDzAFbrG2vWM9dOvRApdfad3E1u1j7TgGSHMqN4mPd4ayAuHcJZ7MvmOrgxt0/aiZWPMUwJYuFG RE1o75ZGex2P90E1gohrkWmqH2/spZ3OBvQ4BQx2Pynefj+OcOcxIsw5yw6A2ug1jviN1UGdB1y45 c8DpKpjn1guvzyjYUob/1UG6vg7fzvDTnquA4BaqEHNJ/3I+fzhw7sRay6lbKdwrhSjra5VKTBJBA 5vBIK87g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hGRbQ-0005Db-6G; Tue, 16 Apr 2019 17:10:36 +0000 Received: from us01smtprelay-2.synopsys.com ([198.182.60.111] helo=smtprelay.synopsys.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hGRbN-0005C2-J9 for linux-snps-arc@lists.infradead.org; Tue, 16 Apr 2019 17:10:34 +0000 Received: from mailhost.synopsys.com (dc8-mailhost2.synopsys.com [10.13.135.210]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtprelay.synopsys.com (Postfix) with ESMTPS id DD71E10C0C43; Tue, 16 Apr 2019 10:10:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1555434632; bh=Q+2zH/VJWu8Mx6TcS34UmuCucpecWbteZfQxWLZCXvo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IgwByiYBrPgzjy+z8VAlEUfqoncQnQMFEP5/J/1eO25OY0EthV1H0P0aTjmesY9zS 2rUGGVcSD+/uMv1phEZKFeLGGLTy9GcYUVHL8WF4Xf9tsWC7TJaLL1h6BaZEwlkK9T elAL/EdIMHg/M/X6ntR00nY6tEaFvSjdEah37gBLtdQUUf0hL922Ux3kcJjUMoM9+g bp7zqOw6bSKAM2bJ7W1upEkVznZ8gbKmZSIaOTBWpSDcZG7eCi/iljBnPbmkD17IT7 wBFHMwcr87VOTbM9prVjw11Ri2t+snJ7zjji3+2EIgYCC/6xYixPJ+lltG6PmHaiUC X5XFf2Tnvn02g== Received: from paltsev-e7480.internal.synopsys.com (paltsev-e7480.internal.synopsys.com [10.121.8.106]) by mailhost.synopsys.com (Postfix) with ESMTP id A4F1AA023C; Tue, 16 Apr 2019 17:10:31 +0000 (UTC) From: Eugeniy Paltsev To: linux-snps-arc@lists.infradead.org, Vineet Gupta Subject: [PATCH 1/3] ARC: cache: declare cache-related defines via ARC_MAX_CACHE_SHIFT Date: Tue, 16 Apr 2019 20:10:19 +0300 Message-Id: <20190416171021.20049-2-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.14.5 In-Reply-To: <20190416171021.20049-1-Eugeniy.Paltsev@synopsys.com> References: <20190416171021.20049-1-Eugeniy.Paltsev@synopsys.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190416_101033_646751_E9065966 X-CRM114-Status: UNSURE ( 8.46 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [198.182.60.111 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Brodkin , Eugeniy Paltsev , linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org * Declare all cache-related defines where we need maximum cache line size (like SMP_CACHE_BYTES, ARCH_DMA_MINALIGN, etc...) via one common ARC_MAX_CACHE_SHIFT define. * Move all cache-related defines outside '#ifdef __ASSEMBLY__' guard to make them visible from ASM code. This is prerequisite for autodetecting cache line size in runtime. Signed-off-by: Eugeniy Paltsev --- arch/arc/include/asm/cache.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 2ad77fb43639..f1642634aab0 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -9,6 +9,12 @@ #ifndef __ARC_ASM_CACHE_H #define __ARC_ASM_CACHE_H +/* Largest line length for either L1 or L2 is 128 bytes (2^7) */ +#define ARC_MAX_CACHE_SHIFT 7 +#define ARC_MAX_CACHE_BYTES (1 << (ARC_MAX_CACHE_SHIFT)) +#define SMP_CACHE_BYTES ARC_MAX_CACHE_BYTES +#define ARCH_DMA_MINALIGN ARC_MAX_CACHE_BYTES + /* In case $$ not config, setup a dummy number for rest of kernel */ #ifndef CONFIG_ARC_CACHE_LINE_SHIFT #define L1_CACHE_SHIFT 6 @@ -47,10 +53,7 @@ : "r"(data), "r"(ptr)); \ }) -/* Largest line length for either L1 or L2 is 128 bytes */ -#define SMP_CACHE_BYTES 128 -#define cache_line_size() SMP_CACHE_BYTES -#define ARCH_DMA_MINALIGN SMP_CACHE_BYTES +#define cache_line_size() ARC_MAX_CACHE_BYTES /* * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses From patchwork Tue Apr 16 17:10:20 2019 Content-Type: text/plain; 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Tue, 16 Apr 2019 17:10:33 +0000 (UTC) From: Eugeniy Paltsev To: linux-snps-arc@lists.infradead.org, Vineet Gupta Subject: [PATCH 2/3] ARC: cache: check cache configuration on each CPU Date: Tue, 16 Apr 2019 20:10:20 +0300 Message-Id: <20190416171021.20049-3-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.14.5 In-Reply-To: <20190416171021.20049-1-Eugeniy.Paltsev@synopsys.com> References: <20190416171021.20049-1-Eugeniy.Paltsev@synopsys.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190416_101034_642025_057E40E4 X-CRM114-Status: GOOD ( 14.46 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [198.182.60.111 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Brodkin , Eugeniy Paltsev , linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org ARC kernel code assumes that all cores have same cache config but as of today we check cache configuration only on master CPU. Fix that and check cache configuration on each CPU. Also while I'm at it, split cache_init_master() for two parts: * checks/setups related to master L1 caches * the rest of cache checks/setups which need to be done once (like IOC / SLC / dma callbacks setup) Both of these changes are prerequisites for autodetecting cache line size in runtime. Signed-off-by: Eugeniy Paltsev --- arch/arc/mm/cache.c | 66 +++++++++++++++++++++++++++++++++++------------------ 1 file changed, 44 insertions(+), 22 deletions(-) diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c index 4135abec3fb0..1036bd56f518 100644 --- a/arch/arc/mm/cache.c +++ b/arch/arc/mm/cache.c @@ -1208,27 +1208,43 @@ noinline void __init arc_ioc_setup(void) __dc_enable(); } +#if IS_ENABLED(CONFIG_ARC_HAS_ICACHE) || IS_ENABLED(CONFIG_ARC_HAS_DCACHE) +static void arc_l1_line_check(unsigned int line_len, const char *cache_name) +{ + if (!line_len) + panic("%s support enabled but non-existent cache\n", + cache_name); + + if (line_len != L1_CACHE_BYTES) + panic("%s line size [%u] != expected [%u]", + cache_name, line_len, L1_CACHE_BYTES); +} +#endif /* IS_ENABLED(CONFIG_ARC_HAS_ICACHE) || IS_ENABLED(CONFIG_ARC_HAS_DCACHE) */ + /* - * Cache related boot time checks/setups only needed on master CPU: - * - Geometry checks (kernel build and hardware agree: e.g. L1_CACHE_BYTES) - * Assume SMP only, so all cores will have same cache config. A check on - * one core suffices for all - * - IOC setup / dma callbacks only need to be done once + * Cache related boot time checks needed on every CPU. */ -void __init arc_cache_init_master(void) +static void arc_l1_cache_check(unsigned int cpu) { - unsigned int __maybe_unused cpu = smp_processor_id(); + if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) + arc_l1_line_check(cpuinfo_arc700[cpu].icache.line_len, "ICache"); + + if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) + arc_l1_line_check(cpuinfo_arc700[cpu].dcache.line_len, "DCache"); +} +/* + * L1 Cache related boot time checks/setups needed on master CPU: + * This checks/setups are done in assumption that all CPU have same cache + * configuration (we validate this in arc_cache_check()): + * - Geometry checks + * - L1 cache line loop callbacks + */ +void __init arc_l1_cache_init_master(unsigned int cpu) +{ if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; - if (!ic->line_len) - panic("cache support enabled but non-existent cache\n"); - - if (ic->line_len != L1_CACHE_BYTES) - panic("ICache line [%d] != kernel Config [%d]", - ic->line_len, L1_CACHE_BYTES); - /* * In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG * pair to provide vaddr/paddr respectively, just as in MMU v3 @@ -1242,13 +1258,6 @@ void __init arc_cache_init_master(void) if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; - if (!dc->line_len) - panic("cache support enabled but non-existent cache\n"); - - if (dc->line_len != L1_CACHE_BYTES) - panic("DCache line [%d] != kernel Config [%d]", - dc->line_len, L1_CACHE_BYTES); - /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ if (is_isa_arcompact()) { int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); @@ -1271,6 +1280,14 @@ void __init arc_cache_init_master(void) */ BUILD_BUG_ON_MSG(L1_CACHE_BYTES > SMP_CACHE_BYTES, "SMP_CACHE_BYTES must be >= any cache line length"); +} + +/* + * Cache related boot time checks/setups needed on master CPU: + * - IOC setup / SLC setup / dma callbacks only need to be done once + */ +void __init arc_cache_init_master(void) +{ if (is_isa_arcv2() && (l2_line_sz > SMP_CACHE_BYTES)) panic("L2 Cache line [%d] > kernel Config [%d]\n", l2_line_sz, SMP_CACHE_BYTES); @@ -1301,11 +1318,16 @@ void __init arc_cache_init_master(void) void __ref arc_cache_init(void) { - unsigned int __maybe_unused cpu = smp_processor_id(); + unsigned int cpu = smp_processor_id(); char str[256]; pr_info("%s", arc_cache_mumbojumbo(0, str, sizeof(str))); + if (!cpu) + arc_l1_cache_init_master(cpu); + + arc_l1_cache_check(cpu); + if (!cpu) arc_cache_init_master(); From patchwork Tue Apr 16 17:10:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 1086432 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Authentication-Results: ozlabs.org; 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Tue, 16 Apr 2019 10:10:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1555434636; bh=zV3bLuswEzbFq98ePW3iRGLKvVhtVlUfXfWKRFePagI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WoDriALpYRdbe+xmipXoTM2v7OYNYXMBaYDFL2sCPmUrms3CJBc8cP9AnqTHqPhXw +iYepBFtu9UMRSFv90EAtNUF6VZnNHV31cbwwM6KHXmesd49Y25fY1NqFuav8eFAVR ZvFlJvALrgestXSNrEu4cr0qXdzQd2BNmNsgCuUQd5F7IdhF177bI+de+aSvtBrDz/ PuR3znYo+7UOPoNY8uF2AJ2cwLLYVg+B17TaJ49CZAUdnK/WPP1B4hltoiOj6XbXNH lRiHn2RJiL3LkTwFXN9kyXwN780OLFnizlF1D/Gnixg3f8AEL4fj7d+A7b3uKe7zPm 6151mfxaJI69A== Received: from paltsev-e7480.internal.synopsys.com (paltsev-e7480.internal.synopsys.com [10.121.8.106]) by mailhost.synopsys.com (Postfix) with ESMTP id C80C9A023C; Tue, 16 Apr 2019 17:10:34 +0000 (UTC) From: Eugeniy Paltsev To: linux-snps-arc@lists.infradead.org, Vineet Gupta Subject: [PATCH 3/3] ARC: cache: allow to autodetect L1 cache line size Date: Tue, 16 Apr 2019 20:10:21 +0300 Message-Id: <20190416171021.20049-4-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.14.5 In-Reply-To: <20190416171021.20049-1-Eugeniy.Paltsev@synopsys.com> References: <20190416171021.20049-1-Eugeniy.Paltsev@synopsys.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190416_101036_533996_3366135B X-CRM114-Status: GOOD ( 21.00 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [198.182.60.111 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Brodkin , Eugeniy Paltsev , linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org One step to "build once run anywhere" Allow to autodetect L1 I/D caches line size in runtime instead of relying on value provided via Kconfig. This is controlled via CONFIG_ARC_CACHE_LINE_AUTODETECT Kconfig option which is disabled by default. * In case of this option disabled there is no overhead in compare with current implementation. * In case of this option enabled there is some overhead in both speed and code size: - we use cache line size stored in the global variable instead of compile time available define, so compiler can't do some optimizations. - we align all cache related buffers by maximum possible cache line size. Nevertheless it isn't significant because we mostly use SMP_CACHE_BYTES or ARCH_DMA_MINALIGN to align stuff (they are equal to maximum possible cache line size) Main change is the split L1_CACHE_BYTES for two separate defines: * L1_CACHE_BYTES >= real L1 I$/D$ line size. Available at compile time. Used for alligning stuff. * CACHEOPS_L1_LINE_SZ == real L1 I$/D$ line size. Available at run time. Used in operations with cache lines/regions. Signed-off-by: Eugeniy Paltsev --- arch/arc/Kconfig | 10 +++++ arch/arc/include/asm/cache.h | 9 ++++- arch/arc/lib/memset-archs.S | 8 +++- arch/arc/mm/cache.c | 89 ++++++++++++++++++++++++++++++++++---------- 4 files changed, 94 insertions(+), 22 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index c781e45d1d99..e7eb5ff1485d 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -215,10 +215,20 @@ menuconfig ARC_CACHE if ARC_CACHE +config ARC_CACHE_LINE_AUTODETECT + bool "Detect cache lines length automatically in runtime" + depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE + help + ARC has configurable cache line length. Enable this option to detect + all cache lines length automatically in runtime to make kernel image + runnable on HW with different cache lines configuration. + If you don't know what the above means, leave this setting alone. + config ARC_CACHE_LINE_SHIFT int "Cache Line Length (as power of 2)" range 5 7 default "6" + depends on !ARC_CACHE_LINE_AUTODETECT help Starting with ARC700 4.9, Cache line length is configurable, This option specifies "N", with Line-len = 2 power N diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index f1642634aab0..0ff8e19008e4 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -15,15 +15,22 @@ #define SMP_CACHE_BYTES ARC_MAX_CACHE_BYTES #define ARCH_DMA_MINALIGN ARC_MAX_CACHE_BYTES +#if IS_ENABLED(CONFIG_ARC_CACHE_LINE_AUTODETECT) +/* + * This must be used for aligning only. In case of cache line autodetect it is + * only safe to use maximum possible value here. + */ +#define L1_CACHE_SHIFT ARC_MAX_CACHE_SHIFT +#else /* In case $$ not config, setup a dummy number for rest of kernel */ #ifndef CONFIG_ARC_CACHE_LINE_SHIFT #define L1_CACHE_SHIFT 6 #else #define L1_CACHE_SHIFT CONFIG_ARC_CACHE_LINE_SHIFT #endif +#endif /* IS_ENABLED(CONFIG_ARC_CACHE_LINE_AUTODETECT) */ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1)) /* * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF) diff --git a/arch/arc/lib/memset-archs.S b/arch/arc/lib/memset-archs.S index b3373f5c88e0..4baeeea29482 100644 --- a/arch/arc/lib/memset-archs.S +++ b/arch/arc/lib/memset-archs.S @@ -16,9 +16,15 @@ * line lengths (32B and 128B) you should rewrite code carefully checking * we don't call any prefetchw/prealloc instruction for L1 cache lines which * don't belongs to memset area. + * + * TODO: FIXME: as for today we chose not optimized memset implementation if we + * enable ARC_CACHE_LINE_AUTODETECT option (as we don't know L1 cache line + * size in compile time). + * One possible way to fix this is to declare memset as a function pointer and + * update it when we discover actual cache line size. */ -#if L1_CACHE_SHIFT == 6 +#if (!IS_ENABLED(CONFIG_ARC_CACHE_LINE_AUTODETECT)) && (L1_CACHE_SHIFT == 6) .macro PREALLOC_INSTR reg, off prealloc [\reg, \off] diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c index 1036bd56f518..8d006c1d12a1 100644 --- a/arch/arc/mm/cache.c +++ b/arch/arc/mm/cache.c @@ -25,6 +25,22 @@ #define USE_RGN_FLSH 1 #endif +/* + * Cache line defines and real L1 I$/D$ line size relations: + * + * L1_CACHE_BYTES >= real L1 I$/D$ line size. Available at compile time. + * CACHEOPS_L1_LINE_SZ == real L1 I$/D$ line size. Available at run time. + */ +#if IS_ENABLED(CONFIG_ARC_CACHE_LINE_AUTODETECT) +#define CACHEOPS_L1_LINE_SZ l1_line_sz +#define CACHEOPS_L1_LINE_MASK l1_line_mask +#else +#define CACHEOPS_L1_LINE_SZ L1_CACHE_BYTES +#define CACHEOPS_L1_LINE_MASK (~((CACHEOPS_L1_LINE_SZ) - 1)) +#endif /* IS_ENABLED(CONFIG_ARC_CACHE_LINE_AUTODETECT) */ + +static unsigned int l1_line_sz; +static unsigned long l1_line_mask; static int l2_line_sz; static int ioc_exists; int slc_enable = 1, ioc_enable = 1; @@ -256,19 +272,19 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr, * -@sz will be integral multiple of line size (being page sized). */ if (!full_page) { - sz += paddr & ~CACHE_LINE_MASK; - paddr &= CACHE_LINE_MASK; - vaddr &= CACHE_LINE_MASK; + sz += paddr & ~CACHEOPS_L1_LINE_MASK; + paddr &= CACHEOPS_L1_LINE_MASK; + vaddr &= CACHEOPS_L1_LINE_MASK; } - num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); + num_lines = DIV_ROUND_UP(sz, CACHEOPS_L1_LINE_SZ); /* MMUv2 and before: paddr contains stuffed vaddrs bits */ paddr |= (vaddr >> PAGE_SHIFT) & 0x1F; while (num_lines-- > 0) { write_aux_reg(aux_cmd, paddr); - paddr += L1_CACHE_BYTES; + paddr += CACHEOPS_L1_LINE_SZ; } } @@ -302,11 +318,11 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr, * -@sz will be integral multiple of line size (being page sized). */ if (!full_page) { - sz += paddr & ~CACHE_LINE_MASK; - paddr &= CACHE_LINE_MASK; - vaddr &= CACHE_LINE_MASK; + sz += paddr & ~CACHEOPS_L1_LINE_MASK; + paddr &= CACHEOPS_L1_LINE_MASK; + vaddr &= CACHEOPS_L1_LINE_MASK; } - num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); + num_lines = DIV_ROUND_UP(sz, CACHEOPS_L1_LINE_SZ); /* * MMUv3, cache ops require paddr in PTAG reg @@ -328,11 +344,11 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr, while (num_lines-- > 0) { if (!full_page) { write_aux_reg(aux_tag, paddr); - paddr += L1_CACHE_BYTES; + paddr += CACHEOPS_L1_LINE_SZ; } write_aux_reg(aux_cmd, vaddr); - vaddr += L1_CACHE_BYTES; + vaddr += CACHEOPS_L1_LINE_SZ; } } @@ -372,11 +388,11 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr, * -@sz will be integral multiple of line size (being page sized). */ if (!full_page) { - sz += paddr & ~CACHE_LINE_MASK; - paddr &= CACHE_LINE_MASK; + sz += paddr & ~CACHEOPS_L1_LINE_MASK; + paddr &= CACHEOPS_L1_LINE_MASK; } - num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); + num_lines = DIV_ROUND_UP(sz, CACHEOPS_L1_LINE_SZ); /* * For HS38 PAE40 configuration @@ -396,7 +412,7 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr, while (num_lines-- > 0) { write_aux_reg(aux_cmd, paddr); - paddr += L1_CACHE_BYTES; + paddr += CACHEOPS_L1_LINE_SZ; } } @@ -422,14 +438,14 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr, if (!full_page) { /* for any leading gap between @paddr and start of cache line */ - sz += paddr & ~CACHE_LINE_MASK; - paddr &= CACHE_LINE_MASK; + sz += paddr & ~CACHEOPS_L1_LINE_MASK; + paddr &= CACHEOPS_L1_LINE_MASK; /* * account for any trailing gap to end of cache line * this is equivalent to DIV_ROUND_UP() in line ops above */ - sz += L1_CACHE_BYTES - 1; + sz += CACHEOPS_L1_LINE_SZ - 1; } if (is_pae40_enabled()) { @@ -1215,14 +1231,21 @@ static void arc_l1_line_check(unsigned int line_len, const char *cache_name) panic("%s support enabled but non-existent cache\n", cache_name); - if (line_len != L1_CACHE_BYTES) + /* + * In case of CONFIG_ARC_CACHE_LINE_AUTODETECT disabled we check + * that cache line size is equal to provided via Kconfig, + * in case of CONFIG_ARC_CACHE_LINE_AUTODETECT enabled we check + * that cache line size is equal for every L1 (I/D) cache on every cpu. + */ + if (line_len != CACHEOPS_L1_LINE_SZ) panic("%s line size [%u] != expected [%u]", - cache_name, line_len, L1_CACHE_BYTES); + cache_name, line_len, CACHEOPS_L1_LINE_SZ); } #endif /* IS_ENABLED(CONFIG_ARC_HAS_ICACHE) || IS_ENABLED(CONFIG_ARC_HAS_DCACHE) */ /* * Cache related boot time checks needed on every CPU. + * NOTE: This function expects 'l1_line_sz' to be set. */ static void arc_l1_cache_check(unsigned int cpu) { @@ -1239,12 +1262,28 @@ static void arc_l1_cache_check(unsigned int cpu) * configuration (we validate this in arc_cache_check()): * - Geometry checks * - L1 cache line loop callbacks + * - l1_line_sz / l1_line_mask setup */ void __init arc_l1_cache_init_master(unsigned int cpu) { + /* + * 'l1_line_sz' programing model: + * We simplify programing of 'l1_line_sz' as we assume that we don't + * support case where CPU have different cache configuration. + * 1. Assign to 'l1_line_sz' length of any (I/D) L1 cache line of + * master CPU. + * 2. Validate 'l1_line_sz' length itself. + * 3. Check that both L1 I$/D$ lines on each CPU are equal to + * 'l1_line_sz' (or to value provided via Kconfig in case of + * CONFIG_ARC_CACHE_LINE_AUTODETECT is disabled). This is done in + * arc_cache_check() which is called for each CPU. + */ + if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; + l1_line_sz = ic->line_len; + /* * In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG * pair to provide vaddr/paddr respectively, just as in MMU v3 @@ -1258,6 +1297,8 @@ void __init arc_l1_cache_init_master(unsigned int cpu) if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; + l1_line_sz = dc->line_len; + /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ if (is_isa_arcompact()) { int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); @@ -1274,6 +1315,14 @@ void __init arc_l1_cache_init_master(unsigned int cpu) } } + if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE) || + IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { + if (l1_line_sz != 32 && l1_line_sz != 64 && l1_line_sz != 128) + panic("L1 cache line sz [%u] unsupported\n", l1_line_sz); + + l1_line_mask = ~(l1_line_sz - 1); + } + /* * Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger * or equal to any cache line length.