From patchwork Tue Apr 16 12:57:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086297 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="RKFUdtwE"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k59933f2z9s71 for ; Tue, 16 Apr 2019 23:01:33 +1000 (AEST) Received: from localhost ([127.0.0.1]:36314 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNiM-0006uO-Tl for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:01:30 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34259) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNes-0004MJ-Jw for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:57:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNep-00010k-Kz for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:57:53 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:44709) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNeo-0000zR-04 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:57:50 -0400 Received: by mail-wr1-x442.google.com with SMTP id y7so26891092wrn.11 for ; Tue, 16 Apr 2019 05:57:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oi+/NMTgWcniQ1uRjJ9edfUCRKrBUoRB3Mi7KKBbAVI=; b=RKFUdtwEX2Jd/yW0RWC4jOR3ZIXgW0xHANLvgIA7VoFGH89Ev9CSnzAeqFP+F1ISqp T1J49VMgozfR9y8fYsj6GshFPt38dRNtirdH3l4AIUL97l1FiZT2QSeSsiS+Z5mO0F9Q 14o+k8bo+mQdEfJsuePghsBiBTE8xEKCewAtWrcGxJTTE+E+r3yI9fUl+gqExegOR2AI 5hkPjbmQANE12RaSXrXtnmCY8o35v9wY6Ru8ThqWvcQxQ4kddRiNhJFjW1XeJ0ctZ4aM aB9RblAyHG2MiAFJ1vaidRZJ63VV6+XJ0wr/pZLIt5xr+Bvg/GNRGYRxtBaSKr00e0BE hxoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oi+/NMTgWcniQ1uRjJ9edfUCRKrBUoRB3Mi7KKBbAVI=; b=BkgestdmbGGUy0sjT+xud+9tS2qn6QQCCKqXR1LWyJ4qH7JT/Jt2NnpLp2MJDbRuaN 8HLEGOIYhJLCqK+7RjIlSX7bQeaQ7LclVGItiQhJehj5YrvjEKaMyjo09PrFP7rHODkW +11dD1Bs0nyfvoHViX045msken5UilGox1uEc7m2UTVb0bVaph6Qw5cQo3hBfmrdBauV 5hOflMnE2TGqDGPfSGPcYJpL95T7bCuXes7i5po9M90F5Cr+j50wqVPer+iM6I0GlwVB E7Ox9xxjp1PLIrj7mOfA6Hdlq9QQD58q/BJZ2hneBEjh+/1O0mvHVz2tX3Bi3Rh8zKra F8+g== X-Gm-Message-State: APjAAAXrMTSxnF13VFofjPED98EFDW5ZqD9Btoq0qK1ciqSxfA82QJx/ EqWWHU5eRzgFNAWQUtMCF1gpNg== X-Google-Smtp-Source: APXvYqxgPQTRRISEjbj2a67tkJPzukDp/ed70jr6b2hBxpnwxQhchsItRAFtkgFrLB7AP3AzXR9FOA== X-Received: by 2002:a5d:448b:: with SMTP id j11mr18982199wrq.218.1555419469079; Tue, 16 Apr 2019 05:57:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.57.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:57:48 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:19 +0100 Message-Id: <20190416125744.27770-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 01/26] target/arm: Make sure M-profile FPSCR RES0 bits are not settable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Enforce that for M-profile various FPSCR bits which are RES0 there but have defined meanings on A-profile are never settable. This ensures that M-profile code can't enable the A-profile behaviour (notably vector length/stride handling) by accident. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/vfp_helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 2468fc16294..7a46d991486 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -105,6 +105,14 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) val &= ~FPCR_FZ16; } + if (arm_feature(env, ARM_FEATURE_M)) { + /* + * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits + * and also for the trapped-exception-handling bits IxE. + */ + val &= 0xf7c0009f; + } + /* * We don't implement trapped exception handling, so the * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) From patchwork Tue Apr 16 12:57:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086300 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UbcPRQfM"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5Dk1r7Nz9s3l for ; Tue, 16 Apr 2019 23:04:38 +1000 (AEST) Received: from localhost ([127.0.0.1]:36345 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNlM-0000yJ-6q for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:04:36 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34341) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNf0-0004TX-Jp for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNex-00014z-7X for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:00 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:40150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNet-00010w-Cw for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:57:57 -0400 Received: by mail-wm1-x343.google.com with SMTP id z24so25490158wmi.5 for ; Tue, 16 Apr 2019 05:57:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Cdsm6rjvWmI4e6EeMdiLshilhoveyvisAWdYOPDLvS8=; b=UbcPRQfMjFKcki+y5mz4nyoIqifqrFfEvVWwpycZV2t0/2oKu0Lz5rb66YOk8dVH6k H+gynXOiulmANFAe2qguw+VjG2W66JVSYZ9qRXku0v6Xq8o/Y1RWFMdE9WsZEqCEQZ4v RkJbFT2htqCrk12xUiZjBmZ7EKSwIUkzmlK6Q7XJon+Ae9Yma0+CNogP+8rb1d9sk81F wtx4EtltNb5oA1JWEyYhsKsVEW5RwwEjm13xaFOje8hCZXd9l8rS0H7Rq22UDbFAQmOa MQJs7Q270tXx3lT37sWvIVPM8LeyvngaBB0ZgBLkT/pjldDazV7f1NfBXkpHDn9jglOP nU+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cdsm6rjvWmI4e6EeMdiLshilhoveyvisAWdYOPDLvS8=; b=QtEWlMIaTqI2Oz60Q16J8Fd1dREgXTUq46pZDqwM9w5txOo38gMiEIkitkFkIKNg2h mG2S/D/xh3KVH/MIXrcIT/nd30DxquYncxRdABwBdELBJPIIxJQUap2lmvwR9jUu8CFB NUbzbFBbJ96MFj6pbFOZf0hbRFcJLZi1sA3DNvygJc0fzLr6Iuwi6kGZYZ+4XUpHQr9x GFwjueyuXtMDuQKFZr+3s6JLi0MAX2fFiRJ9Af6cTa2jzzU6/PwAUUu96HKrWsKetz7S 5uSY1oknipOrNkGJmQrdZVNbPw4AaQpux3jMXjKZQHTlGZLAeZ57Tinc37AiQm9y+pE9 927Q== X-Gm-Message-State: APjAAAX6TCE0/LvjlgJmoVPwljMS7YvfevoKw+yCbbBDAmR347qOQe8K 0ZJ4Yjo3QZQ9ynmth+mHlzTsp88RkaI= X-Google-Smtp-Source: APXvYqwtHpIDl6ni7Lp1l92UaDb4/A9szvAO3aPUVBFX7k8h0YuFc9ho1JyDM6b/e8Xi+bU1t408AA== X-Received: by 2002:a1c:eb07:: with SMTP id j7mr25520428wmh.138.1555419471361; Tue, 16 Apr 2019 05:57:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.57.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:57:49 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:20 +0100 Message-Id: <20190416125744.27770-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 02/26] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" For M-profile the MVFR* ID registers are memory mapped, in the range we implement via the NVIC. Allow them to be read. (If the CPU has no FPU, these registers are defined to be RAZ.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/armv7m_nvic.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index ab822f42514..45d72f86bdf 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1222,6 +1222,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) return 0; } return cpu->env.v7m.sfar; + case 0xf40: /* MVFR0 */ + return cpu->isar.mvfr0; + case 0xf44: /* MVFR1 */ + return cpu->isar.mvfr1; + case 0xf48: /* MVFR2 */ + return cpu->isar.mvfr2; default: bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); From patchwork Tue Apr 16 12:57:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086294 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="CrRywhlh"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k56Y4f6hz9s0W for ; Tue, 16 Apr 2019 22:59:17 +1000 (AEST) Received: from localhost ([127.0.0.1]:36254 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNgB-0004ww-Gn for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 08:59:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34340) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNf0-0004TW-Ji for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNex-00014u-7T for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:00 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:36436) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNet-00011p-E1 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:57:57 -0400 Received: by mail-wr1-x442.google.com with SMTP id y13so26977229wrd.3 for ; Tue, 16 Apr 2019 05:57:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=01ihWTYepPx72GUDfGATzFEgCIYunLwUx5AdBGmnpVM=; b=CrRywhlhrwOhN22S3x+q9ZQ3G8UrTSgfdhFktdecNvXuEGLQqdhFLLxzbqZ6VzUTdu ksrm+y2tha6K/e38IIOILs+JxyRxIDvNvQ2pbAldW5Zv0N6FWrw16hacBF+4SOwXTNpo FT3YeCEo50JwWnX8IMSggdIdNnG85R11uK8OyfN8fkuBJte4ECc/kUBYiL/XDZqAlwxY 9RaiSXZRpAihQwPU9S1e9uyAWZaC87j3AlOqFJWB5ZV7QXEsIilOZxip9vWetB/PkXem IIJeFUyCato6NQCxxIuyYWeuGF+NPf5RwZMiUjjX7W1mHDlx65WFSm9J61GEj31h+Of+ PY0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=01ihWTYepPx72GUDfGATzFEgCIYunLwUx5AdBGmnpVM=; b=GB3HDHnxNPra/ey1d4mMGSzmE91rW2vMSyUzUwc7fZVbmdh85lelWXNiccGoEzv+gQ MrMgdkVRg4VuDseKW/b0nErQOQXdqMrYoUj9NXkxRwLGrcAGM9MEKdBPoy6M9LccaJl/ 8te/OT2EqQukdKP+dAwm5OUXD2rjoJUjHGYJqf/WYLA0xAL5kkWRuZ06iO41E2C6oQSt uCHwe6pL0CEVxyNRtA1d99RkSELrcCvgUEWbzxXNocPSaG1OyzJVYA8foLegBnDRJbgi Hbo9xwzdhB2WOTbJRwiJ7ApiPpZJLy32eXjL2y7I4SBzJIkRlipfsJs2MRdyEuqfgOb3 6EuQ== X-Gm-Message-State: APjAAAX3femC7zeH1FPIGrJDBedByaLoQgm/CmSPhcP8B0LaD55TJKnd eTF1pr6uoMv0o/ltW/tqrHZ6vw== X-Google-Smtp-Source: APXvYqzA7qD2iXJ9J7EVMHE3pvmYtOS319MmJlE7IoHCwGypPL7Pi3tipdJCbPZRSC5CEOj5JlqrSA== X-Received: by 2002:adf:e78e:: with SMTP id n14mr29629175wrm.14.1555419473612; Tue, 16 Apr 2019 05:57:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.57.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:57:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:21 +0100 Message-Id: <20190416125744.27770-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 03/26] target/arm: Implement dummy versions of M-profile FP-related registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The M-profile floating point support has three associated config registers: FPCAR, FPCCR and FPDSCR. It also makes the registers CPACR and NSACR have behaviour other than reads-as-zero. Add support for all of these as simple reads-as-written registers. We will hook up actual functionality later. The main complexity here is handling the FPCCR register, which has a mix of banked and unbanked bits. Note that we don't share storage with the A-profile cpu->cp15.nsacr and cpu->cp15.cpacr_el1, though the behaviour is quite similar, for two reasons: * the M profile CPACR is banked between security states * it preserves the invariant that M profile uses no state inside the cp15 substruct Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 34 ++++++++++++ hw/intc/armv7m_nvic.c | 125 ++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 5 ++ target/arm/machine.c | 16 ++++++ 4 files changed, 180 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d4d2836923d..c8d78bd5b52 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -533,6 +533,11 @@ typedef struct CPUARMState { uint32_t scr[M_REG_NUM_BANKS]; uint32_t msplim[M_REG_NUM_BANKS]; uint32_t psplim[M_REG_NUM_BANKS]; + uint32_t fpcar[M_REG_NUM_BANKS]; + uint32_t fpccr[M_REG_NUM_BANKS]; + uint32_t fpdscr[M_REG_NUM_BANKS]; + uint32_t cpacr[M_REG_NUM_BANKS]; + uint32_t nsacr; } v7m; /* Information associated with an exception about to be taken: @@ -1577,6 +1582,35 @@ FIELD(V7M_CSSELR, LEVEL, 1, 3) */ FIELD(V7M_CSSELR, INDEX, 0, 4) +/* v7M FPCCR bits */ +FIELD(V7M_FPCCR, LSPACT, 0, 1) +FIELD(V7M_FPCCR, USER, 1, 1) +FIELD(V7M_FPCCR, S, 2, 1) +FIELD(V7M_FPCCR, THREAD, 3, 1) +FIELD(V7M_FPCCR, HFRDY, 4, 1) +FIELD(V7M_FPCCR, MMRDY, 5, 1) +FIELD(V7M_FPCCR, BFRDY, 6, 1) +FIELD(V7M_FPCCR, SFRDY, 7, 1) +FIELD(V7M_FPCCR, MONRDY, 8, 1) +FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) +FIELD(V7M_FPCCR, UFRDY, 10, 1) +FIELD(V7M_FPCCR, RES0, 11, 15) +FIELD(V7M_FPCCR, TS, 26, 1) +FIELD(V7M_FPCCR, CLRONRETS, 27, 1) +FIELD(V7M_FPCCR, CLRONRET, 28, 1) +FIELD(V7M_FPCCR, LSPENS, 29, 1) +FIELD(V7M_FPCCR, LSPEN, 30, 1) +FIELD(V7M_FPCCR, ASPEN, 31, 1) +/* These bits are banked. Others are non-banked and live in the M_REG_S bank */ +#define R_V7M_FPCCR_BANKED_MASK \ + (R_V7M_FPCCR_LSPACT_MASK | \ + R_V7M_FPCCR_USER_MASK | \ + R_V7M_FPCCR_THREAD_MASK | \ + R_V7M_FPCCR_MMRDY_MASK | \ + R_V7M_FPCCR_SPLIMVIOL_MASK | \ + R_V7M_FPCCR_UFRDY_MASK | \ + R_V7M_FPCCR_ASPEN_MASK) + /* * System register ID fields. */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 45d72f86bdf..5eb438f5409 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1077,6 +1077,16 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) } case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; + case 0xd88: /* CPACR */ + if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + return 0; + } + return cpu->env.v7m.cpacr[attrs.secure]; + case 0xd8c: /* NSACR */ + if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + return 0; + } + return cpu->env.v7m.nsacr; /* TODO: Implement debug registers. */ case 0xd90: /* MPU_TYPE */ /* Unified MPU; if the MPU is not present this value is zero */ @@ -1222,6 +1232,43 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) return 0; } return cpu->env.v7m.sfar; + case 0xf34: /* FPCCR */ + if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + return 0; + } + if (attrs.secure) { + return cpu->env.v7m.fpccr[M_REG_S]; + } else { + /* + * NS can read LSPEN, CLRONRET and MONRDY. It can read + * BFRDY and HFRDY if AIRCR.BFHFNMINS != 0; + * other non-banked bits RAZ. + * TODO: MONRDY should RAZ/WI if DEMCR.SDME is set. + */ + uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; + uint32_t mask = R_V7M_FPCCR_LSPEN_MASK | + R_V7M_FPCCR_CLRONRET_MASK | + R_V7M_FPCCR_MONRDY_MASK; + + if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { + mask |= R_V7M_FPCCR_BFRDY_MASK | R_V7M_FPCCR_HFRDY_MASK; + } + + value &= mask; + + value |= cpu->env.v7m.fpccr[M_REG_NS]; + return value; + } + case 0xf38: /* FPCAR */ + if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + return 0; + } + return cpu->env.v7m.fpcar[attrs.secure]; + case 0xf3c: /* FPDSCR */ + if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + return 0; + } + return cpu->env.v7m.fpdscr[attrs.secure]; case 0xf40: /* MVFR0 */ return cpu->isar.mvfr0; case 0xf44: /* MVFR1 */ @@ -1475,6 +1522,18 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK; } break; + case 0xd88: /* CPACR */ + if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + /* We implement only the Floating Point extension's CP10/CP11 */ + cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20); + } + break; + case 0xd8c: /* NSACR */ + if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + /* We implement only the Floating Point extension's CP10/CP11 */ + cpu->env.v7m.nsacr = value & (3 << 10); + } + break; case 0xd90: /* MPU_TYPE */ return; /* RO */ case 0xd94: /* MPU_CTRL */ @@ -1703,6 +1762,72 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } break; } + case 0xf34: /* FPCCR */ + if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + /* Not all bits here are banked. */ + uint32_t fpccr_s; + + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* Don't allow setting of bits not present in v7M */ + value &= (R_V7M_FPCCR_LSPACT_MASK | + R_V7M_FPCCR_USER_MASK | + R_V7M_FPCCR_THREAD_MASK | + R_V7M_FPCCR_HFRDY_MASK | + R_V7M_FPCCR_MMRDY_MASK | + R_V7M_FPCCR_BFRDY_MASK | + R_V7M_FPCCR_MONRDY_MASK | + R_V7M_FPCCR_LSPEN_MASK | + R_V7M_FPCCR_ASPEN_MASK); + } + value &= ~R_V7M_FPCCR_RES0_MASK; + + if (!attrs.secure) { + /* Some non-banked bits are configurably writable by NS */ + fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; + if (!(fpccr_s & R_V7M_FPCCR_LSPENS_MASK)) { + uint32_t lspen = FIELD_EX32(value, V7M_FPCCR, LSPEN); + fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, LSPEN, lspen); + } + if (!(fpccr_s & R_V7M_FPCCR_CLRONRETS_MASK)) { + uint32_t cor = FIELD_EX32(value, V7M_FPCCR, CLRONRET); + fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, CLRONRET, cor); + } + if ((s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + uint32_t hfrdy = FIELD_EX32(value, V7M_FPCCR, HFRDY); + uint32_t bfrdy = FIELD_EX32(value, V7M_FPCCR, BFRDY); + fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, HFRDY, hfrdy); + fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, BFRDY, bfrdy); + } + /* TODO MONRDY should RAZ/WI if DEMCR.SDME is set */ + { + uint32_t monrdy = FIELD_EX32(value, V7M_FPCCR, MONRDY); + fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, MONRDY, monrdy); + } + + /* + * All other non-banked bits are RAZ/WI from NS; write + * just the banked bits to fpccr[M_REG_NS]. + */ + value &= R_V7M_FPCCR_BANKED_MASK; + cpu->env.v7m.fpccr[M_REG_NS] = value; + } else { + fpccr_s = value; + } + cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; + } + break; + case 0xf38: /* FPCAR */ + if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + value &= ~7; + cpu->env.v7m.fpcar[attrs.secure] = value; + } + break; + case 0xf3c: /* FPDSCR */ + if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + value &= 0x07c00000; + cpu->env.v7m.fpdscr[attrs.secure] = value; + } + break; case 0xf50: /* ICIALLU */ case 0xf58: /* ICIMVAU */ case 0xf5c: /* DCIMVAC */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 41557821974..3f9c81e7e9e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -282,6 +282,11 @@ static void arm_cpu_reset(CPUState *s) env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; } + if (arm_feature(env, ARM_FEATURE_VFP)) { + env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; + env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | + R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; + } /* Unlike A/R profile, M profile defines the reset LR value */ env->regs[14] = 0xffffffff; diff --git a/target/arm/machine.c b/target/arm/machine.c index b2925496148..09567d4fc66 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -305,6 +305,21 @@ static const VMStateDescription vmstate_m_v8m = { } }; +static const VMStateDescription vmstate_m_fp = { + .name = "cpu/m/fp", + .version_id = 1, + .minimum_version_id = 1, + .needed = vfp_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS), + VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS), + VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS), + VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS), + VMSTATE_UINT32(env.v7m.nsacr, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m = { .name = "cpu/m", .version_id = 4, @@ -330,6 +345,7 @@ static const VMStateDescription vmstate_m = { &vmstate_m_scr, &vmstate_m_other_sp, &vmstate_m_v8m, + &vmstate_m_fp, NULL } }; From patchwork Tue Apr 16 12:57:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="c4f+R1n+"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5B303nSz9s5c for ; Tue, 16 Apr 2019 23:02:19 +1000 (AEST) Received: from localhost ([127.0.0.1]:36322 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNj7-0007Zi-1O for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:02:17 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNf2-0004Vf-II for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNez-00016M-1k for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:02 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:34507) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNev-00012p-9x for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:57:59 -0400 Received: by mail-wr1-x444.google.com with SMTP id p10so26959475wrq.1 for ; Tue, 16 Apr 2019 05:57:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6cCVRnIqDr1YlxNV4JvcQbdEHcgddBmMkialjOjujLk=; b=c4f+R1n+jjnEslMRaVeRaR6ItZ5Mw1u+NmUqBlFdCRt0wh83Y76IWliCl2MB5evha/ VdLNuhgxNjWwmmlkSA3m5/B/I/4d9yJz1NxhNHjOhIxOkC2EaPInzU+TrXG/O34GlqfM ZmxEJhCi94tuUOGnsZIQZJlZ1Pn4v3PvIoyzXDJDepjoRQ9vD+2Ua5OLQW4yTPBPwz7o dppuCApRJ6d+8kybhp004Z1gJ+037lSjr9XpmUXakMzbBhwNWEzA2R+dWtMe6TAhVq/6 MBCCp6gnRZ64THuI4ZT0wswx8szE3/HrpuX8Nw2L0nZq3G8msGk2bucTUAGjcbeBT7Wp GESw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6cCVRnIqDr1YlxNV4JvcQbdEHcgddBmMkialjOjujLk=; b=meQZJ2jB1NhzNycOBYkI1FrLs2hSxptiob176sz+4dsTZO7zm2Jcg3JhXZ/U7Wcklx Qk1adRpSyI1BNl6k+3ahBLOgFBD3PZRZ65lqd4hY24eKWod8jvoKjyp60fN4ds0/nQ+W vt62IkKPdlcGrK7k9cCtxaOqSGRtUQyF8ySQfJU9fRaGd0nW051D+gey61ip0+CgjPZr 4ykzhK/imP6Ff3/UU/sE34JJfQQ7badkTcVNL3FR0IINwMHnMRnavsB5KnI1jRyVPOZj X/O/i271Cpo0avaN3EiZp+1GvmLMEqDQqii3HqXT3njIomv/egjx3LoWY6o8gemCeI/w hp+w== X-Gm-Message-State: APjAAAXzdDU1kafTCVuzBjMNX5L2j4UOB0gTrUO9sjK9iWWOLWaujBVR fM+Za4aDWv3NvTjha/sycTxXWQ== X-Google-Smtp-Source: APXvYqxCheZt7DalEk/3eS6/S984Feaz4yZqP3+I7clWmS1jeCRDFgKgatHvtt6l97CZTdxlrxHq2Q== X-Received: by 2002:adf:b6a4:: with SMTP id j36mr50713225wre.55.1555419475203; Tue, 16 Apr 2019 05:57:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.57.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:57:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:22 +0100 Message-Id: <20190416125744.27770-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 04/26] target/arm: Disable most VFP sysregs for M-profile X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The only "system register" that M-profile floating point exposes via the VMRS/VMRS instructions is FPSCR, and it does not have the odd special case for rd==15. Add a check to ensure we only expose FPSCR. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d408e4d7ef4..d56488ec847 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3512,12 +3512,27 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) } } } else { /* !dp */ + bool is_sysreg; + if ((insn & 0x6f) != 0x00) return 1; rn = VFP_SREG_N(insn); + + is_sysreg = extract32(insn, 21, 1); + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* + * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. + * Writes to R15 are UNPREDICTABLE; we choose to undef. + */ + if (is_sysreg && (rd == 15 || (rn >> 1) != ARM_VFP_FPSCR)) { + return 1; + } + } + if (insn & ARM_CP_RW_BIT) { /* vfp->arm */ - if (insn & (1 << 21)) { + if (is_sysreg) { /* system register */ rn >>= 1; @@ -3584,7 +3599,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) } } else { /* arm->vfp */ - if (insn & (1 << 21)) { + if (is_sysreg) { rn >>= 1; /* system register */ switch (rn) { From patchwork Tue Apr 16 12:57:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086304 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="SFSebnJU"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5JP1yvQz9s3l for ; Tue, 16 Apr 2019 23:07:48 +1000 (AEST) Received: from localhost ([127.0.0.1]:36407 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNoQ-0003on-RT for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:07:46 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNf9-0004dL-52 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNf7-0001CQ-9B for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:11 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41749) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNf6-00013V-R3 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:09 -0400 Received: by mail-wr1-x443.google.com with SMTP id r4so26905548wrq.8 for ; Tue, 16 Apr 2019 05:57:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aQ6wGPLx3WRt+frxzRIZZzBI6Q8JRULb0Aj0I2glCjQ=; b=SFSebnJUN/iho+FW5EGiA9RNR+U2xEAyxH+PqywlPZ6RuQZA+uj8OamWP0T0+JSy/x 1K8xn131gaWUzhse5YsoPxHFyoz94XWqQCIkLOdryUMd/LnJ0Qx+Gg5J1zmlp0pp/dlB 48+qqlDaotJGJbGYllYWY+BrLsBSGIAme/wRSF37wQXVPmA9seipxy95ZCjmoXKY+JOH 5G/FHS+wqj/hbgdseEXE0+MnakC8Hw7PQyWYrIhd0oDGOjiGblljgHKbfNy2k4hvP/FX 1nmCQ3D95FhGwjE7+jAfLzIQNeD9airzZHOvEiBaQCZjck6eJtwa5EOvax4FFreuOVcT nQ1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aQ6wGPLx3WRt+frxzRIZZzBI6Q8JRULb0Aj0I2glCjQ=; b=LU8VYB2j+CPVVdL3zh0mbL96QdLcpRtwhBGkjHSeHD+MdJhS4AYKu6x4uKDW2J/B90 1k68St3so5wCUaOspQ6BAiDOXOGnRw2InEFbgekaUcxtyhHTm1aoqIVFU+6MWag9+5Pu gskhpDof4EkZxnUjs5Yt11Z254rlmAbBdT/VDKtjvSDxwQUodcS1qXUW0HeC056KKKRp E3Wfegh7M7NZa9Qgzva6RaRjOxHB00GFem6+K+WYoiXvv1AyGImlldecb9YfAi9BUp5H 99KImIZqWdp7g7LQofqG7UNVnX0OZv3sQWLA1M5K2mdIuflDZILu5Bs3c6vNn0z2ANAD un6w== X-Gm-Message-State: APjAAAVQ7qCm4e5MmqlUYPeq7oG8FR/i3X54tuTjmB+U6o4KN/LJwRZP xtrdYZWFPP54F3yIcYiF6Zxz9A== X-Google-Smtp-Source: APXvYqz7h1pvT/Dlfv5dqqti7wugzUL4Gl0MpCjw2NO6V91Kj5zU9eKqoi4YaOlPoV2AYbeLDihasw== X-Received: by 2002:adf:efc1:: with SMTP id i1mr51644628wrp.199.1555419476820; Tue, 16 Apr 2019 05:57:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.57.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:57:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:23 +0100 Message-Id: <20190416125744.27770-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 05/26] target/arm: Honour M-profile FP enable bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Like AArch64, M-profile floating point has no FPEXC enable bit to gate floating point; so always set the VFPEN TB flag. M-profile also has CPACR and NSACR similar to A-profile; they behave slightly differently: * the CPACR is banked between Secure and Non-Secure * if the NSACR forces a trap then this is taken to the Secure state, not the Non-Secure state Honour the CPACR and NSACR settings. The NSACR handling requires us to borrow the exception.target_el field (usually meaningless for M profile) to distinguish the NOCP UsageFault taken to Secure state from the more usual fault taken to the current security state. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++--- target/arm/translate.c | 10 ++++++-- 2 files changed, 60 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a36f4b3d699..27e5f98bc73 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7561,6 +7561,25 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, return target_el; } +/* + * Return true if the v7M CPACR permits access to the FPU for the specified + * security state and privilege level. + */ +static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv) +{ + switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { + case 0: + case 2: /* UNPREDICTABLE: we treat like 0 */ + return false; + case 1: + return is_priv; + case 3: + return true; + default: + g_assert_not_reached(); + } +} + static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, ARMMMUIdx mmu_idx, bool ignfault) { @@ -8820,9 +8839,23 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK; break; case EXCP_NOCP: - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); - env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; + { + /* + * NOCP might be directed to something other than the current + * security state if this fault is because of NSACR; we indicate + * the target security state using exception.target_el. + */ + int target_secstate; + + if (env->exception.target_el == 3) { + target_secstate = M_REG_S; + } else { + target_secstate = env->v7m.secure; + } + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, target_secstate); + env->v7m.cfsr[target_secstate] |= R_V7M_CFSR_NOCP_MASK; break; + } case EXCP_INVSTATE: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; @@ -12756,6 +12789,22 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } + if (arm_feature(env, ARM_FEATURE_M)) { + /* CPACR can cause a NOCP UsageFault taken to current security state */ + if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { + return 1; + } + + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { + if (!extract32(env->v7m.nsacr, 10, 1)) { + /* FP insns cause a NOCP UsageFault taken to Secure */ + return 3; + } + } + + return 0; + } + /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: * 0, 2 : trap EL0 and EL1/PL1 accesses * 1 : trap only EL0 accesses @@ -12943,7 +12992,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1)) { + || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); diff --git a/target/arm/translate.c b/target/arm/translate.c index d56488ec847..bb539111179 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3398,8 +3398,14 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) * for attempts to execute invalid vfp/neon encodings with FP disabled. */ if (s->fp_excp_el) { - gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), + s->fp_excp_el); + } else { + gen_exception_insn(s, 4, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), + s->fp_excp_el); + } return 0; } From patchwork Tue Apr 16 12:57:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086295 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="yPmVw9Vm"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k57R2Ry4z9s0W for ; Tue, 16 Apr 2019 23:00:03 +1000 (AEST) Received: from localhost ([127.0.0.1]:36268 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNgv-0005hs-3X for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:00:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNf4-0004Y9-Pc for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNf2-00018x-SK for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:06 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:47023) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNf0-00014I-TY for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:04 -0400 Received: by mail-wr1-x443.google.com with SMTP id t17so26886014wrw.13 for ; Tue, 16 Apr 2019 05:57:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xc3UIGC5SvjlHs9DchEFUCKpsleMW6NB4iU50Hc4tGE=; b=yPmVw9Vm2MHaue//8t6SPQ/AQlQsCrh3+Bv5D8HFaaVR9Q1mganklBEN6OVfzObcbR erJvWHQzigC05an4Luo9d0uLxauQBDxXae8bZw6LlUsJ6qNXoNTeSk9/tOkpYZv2y4v1 T1HRBkaA5U27N5fB6MLiC1ZZmMBlLORsIE6tE748XMLXZlsQ2cmlYW3fw8xMyhz6V1Qr BXA9YaMGAYn0ofaZf10bRfcYGncJsU5ZkgKUzkfTO7Km9pQppcWQllSZEoq9IWuJNbJj 8K/g8dj9cdhw76SQyK0KqNw39BuisLx3pwVZzQDvRASaPFNjKBpGKojYL4KRzBTlgY7w PeRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xc3UIGC5SvjlHs9DchEFUCKpsleMW6NB4iU50Hc4tGE=; b=ebqgsEfG+Arz5LMc5nGxGCq+EIDTkBvICV/2gxsAWu1/scHUawMGIRTT0U/5JE0F6g R8cOYBiWFQZEAMna5v/5vOcqzzG5JcucRLEpsNILwKCv6tc7+Fxnq5xcC6MQEePFeuwR dPNJxQgQuJusffEA4MhaNL9Yqsp1Q9ltLUtvf4+kb2BXU5Ikg6SSL3oMc5NDd6OkbdSD GCxyZG1F/XTf5Cfp7u7DMyW6jRWRuSg0IerhjuCQo6fkrAVScGnKXiJjLxEYH79ThDc6 0lkne7x4vhMo3WTlOQuVf4wnyacZVB9h/97BdiQqHzJXQj4mbRGaA912FNzTOdKr/AZe mKHg== X-Gm-Message-State: APjAAAVBC9Vi458XfFzm80VJaw2MpJJoiAuCyEgiyJOSmxYkOnT8PwzC nUH2D1yvlyIO32jsy/MsihpDDA== X-Google-Smtp-Source: APXvYqw2gRjMcAiAtTv/ngrhodkBRKGqmi38Qa5NLwWPjn4DTQHv2oXotLLVIPu5709074X1U+0J0w== X-Received: by 2002:adf:de07:: with SMTP id b7mr23886402wrm.196.1555419478176; Tue, 16 Apr 2019 05:57:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.57.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:57:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:24 +0100 Message-Id: <20190416125744.27770-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 06/26] target/arm: Decode FP instructions for M profile X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Correct the decode of the M-profile "coprocessor and floating-point instructions" space: * op0 == 0b11 is always unallocated * if the CPU has an FPU then all insns with op1 == 0b101 are floating point and go to disas_vfp_insn() For the moment we leave VLLDM and VLSTM as NOPs; in a later commit we will fill in the proper implementation for the case where an FPU is present. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index bb539111179..d280b3a9a3a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11727,10 +11727,19 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 6: case 7: case 14: case 15: /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { - /* We don't currently implement M profile FP support, - * so this entire space should give a NOCP fault, with - * the exception of the v8M VLLDM and VLSTM insns, which - * must be NOPs in Secure state and UNDEF in Nonsecure state. + /* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */ + if (extract32(insn, 24, 2) == 3) { + goto illegal_op; /* op0 = 0b11 : unallocated */ + } + + /* + * Decode VLLDM and VLSTM first: these are nonstandard because: + * * if there is no FPU then these insns must NOP in + * Secure state and UNDEF in Nonsecure state + * * if there is an FPU then these insns do not have + * the usual behaviour that disas_vfp_insn() provides of + * being controlled by CPACR/NSACR enable bits or the + * lazy-stacking logic. */ if (arm_dc_feature(s, ARM_FEATURE_V8) && (insn & 0xffa00f00) == 0xec200a00) { @@ -11744,6 +11753,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Just NOP since FP support is not implemented */ break; } + if (arm_dc_feature(s, ARM_FEATURE_VFP) && + ((insn >> 8) & 0xe) == 10) { + /* FP, and the CPU supports it */ + if (disas_vfp_insn(s, insn)) { + goto illegal_op; + } + break; + } + /* All other insns: NOCP */ gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), default_exception_el(s)); From patchwork Tue Apr 16 12:57:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086305 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="XwUfkKGk"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5JY4rVbz9s3l for ; Tue, 16 Apr 2019 23:07:56 +1000 (AEST) Received: from localhost ([127.0.0.1]:36409 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNoX-0003u8-7O for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:07:53 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNf7-0004bS-GD for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNf6-0001B8-F8 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:09 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38193) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNf3-00015u-2K for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:06 -0400 Received: by mail-wm1-x343.google.com with SMTP id w15so25304725wmc.3 for ; Tue, 16 Apr 2019 05:58:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kMVdzvD/XiERD9we9lBIjwqedh398KDiYXQYlDS231U=; b=XwUfkKGkrXVJMk+vO1201fkwjDMcyWw5SXhBM5FV06Y5VvZluX5LaJ+gsW1nymTKsi lrxrIO1Fv3fP3ffGmubHBc4DlOabh6Y6Z/+jft6eEedpdVYMGxkhINvXTV7WIDpa434Z cXmoFArG9pBeT1uG3W3GONGvaZg0zyB7uotL3dWv+6hYYjIZzK/9fs9ny0lyYY5+cGY0 n36DACKlJ8GPRIzlekJk/wV6xJDV1v1TgX3h/QSp068JBx5D55V+2COWoXr4Y14oHoui GCwhHrkRXF0vaM+X9Oqa+pUY1Rkvq1C49AXo/pyVfrwjkXmHJWKwC0bRMAYzhNjSUWce uxwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kMVdzvD/XiERD9we9lBIjwqedh398KDiYXQYlDS231U=; b=Cudqho5CV+Af4bEDVbYHDe5nxFamVVi3rp5LnxaSXfeLCnVhZcOSbNayGFQcwkWlnL TeA9N15fVRg0PY4bXso148oAQOA8701a0EPQCZhYpBhqfQALNSnmmAMRAXo90/laYROI 3juFsGeynnDk1HSf/23Kcdx4P8nD5AKQq0S3AgtRvQbSkCbKyh/08iHoaDOBkJkzwRGt EgovNvEafAQvBqYftktbNgRNRcHCCpHCA5xeewyDdA6n4IP3g+ooUXG/16BcnD18H7cl 1Qfird8a/6r2C/6QRTaFsUrTSgBErYWut17C4MJoKG7yAlAjhJe2EdF7o7K7mUEvl2P7 1eQw== X-Gm-Message-State: APjAAAVVNn9RAtr5uNx4sqUIvrXR5zDUZpQw2r5nDMnxM0FMc/E8veeB 6hv3ZkL01dpN04eHdxMqz8VN+g== X-Google-Smtp-Source: APXvYqwVYcJvOus7BS4rYoWjWtoUaJ9oX4u68pNhz+cb91nM2UAIJT9xtrHg2pPLP5hEIPL+RLDI/Q== X-Received: by 2002:a7b:c92f:: with SMTP id h15mr26435726wml.115.1555419480496; Tue, 16 Apr 2019 05:58:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.57.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:57:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:25 +0100 Message-Id: <20190416125744.27770-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 07/26] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" If the floating point extension is present, then the SG instruction must clear the CONTROL_S.SFPA bit. Implement this. (On a no-FPU system the bit will always be zero, so we don't need to make the clearing of the bit conditional on ARM_FEATURE_VFP.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 27e5f98bc73..b4f1609a1c6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8809,6 +8809,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32 ", executing it\n", env->regs[15]); env->regs[14] &= ~1; + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; switch_v7m_security_state(env, true); xpsr_write(env, 0, XPSR_IT); env->regs[15] += 4; From patchwork Tue Apr 16 12:57:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086301 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UCxrSCP0"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5F04B0Bz9s5c for ; Tue, 16 Apr 2019 23:04:52 +1000 (AEST) Received: from localhost ([127.0.0.1]:36347 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNla-0001BM-G3 for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:04:50 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34505) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNf8-0004cs-Mb for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNf6-0001Bk-Oy for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:10 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:44711) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNf6-00017t-Ea for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:08 -0400 Received: by mail-wr1-x442.google.com with SMTP id y7so26892221wrn.11 for ; Tue, 16 Apr 2019 05:58:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FJePOyZA9Q3WiPn2k7ahGOza/ZX3bYrlq3y5WZmHrm8=; b=UCxrSCP0eboG54fxzgq65yS18UP31ZSBcboUV8nMm2G9k2XUGj7s8gq9Q9NtIjzq94 4DCyBggg0BKfLwtJFNiytIcIuhBN+7Rpjt5svYgPHLJqJtl8AWp8R4pWsVDqP2w38SXq ua9Rufc8OiECFQwTH3mMmxMZYvqWPDku/ryXgWbW1SnT0ptgP9jkNHmt+w9SO/oQ9gRp wQ1cmyQLhOBE4pE31iNmPscs4Z5j4nawFqSHRXgg14IYjmYVwK3agPBCet0ZkO7HhFSL 68WucII1TcFTeLuzaB36FkvCzBfvVYuSeDSFCTHYfbmfAOjp2MPI6dMABPlCEJwgVo9g ByYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FJePOyZA9Q3WiPn2k7ahGOza/ZX3bYrlq3y5WZmHrm8=; b=nRL0UCOD8xbNPO4LE70pvy3brksSwOU2ZKWQrADY6q7IhgNqKhHT2MAZHDp4s1Lez+ gpQW/kL8NsRW0QvYcAJ7wMoAZ9PeW4r3vpfk4LjOp/v+O2iL6RZcxGCxsOnjqqrH01IJ JgKNmgier7RroqLrP4y2FEpaOzDOPIGKJMuK6SFUMoD0XerHDhFnCKR+CFPNXrvegeNw xyVGsDC+K9VpB5qXekLm5csuJsExjf9s3oxwZ+0JtfgXGpVoF99p8uhLvf5OReWfiM5D n8t6ul9LqR5Kwn4ZsyKEeI2l5t3Bj4b9ku+QVA63KviIf7U0GNiaZDfKYABjU/hBGk7u iFlw== X-Gm-Message-State: APjAAAVrUzjwMDKtAnsPY/pn5uPGs6O9hLksuZMVx6jqtol+fgkk3cHI 8l3RHhdh0nTswZG876c3n+Np1Q== X-Google-Smtp-Source: APXvYqw9l4wnEmEtIMaZZC/0sVVLC8/pgvpe2hqJK05P9azhdTK9PxwD+fTc47rGerYAw6xKNNJUQw== X-Received: by 2002:adf:e951:: with SMTP id m17mr42025658wrn.287.1555419482909; Tue, 16 Apr 2019 05:58:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:26 +0100 Message-Id: <20190416125744.27770-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 08/26] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The M-profile CONTROL register has two bits -- SFPA and FPCA -- which relate to floating-point support, and should be RES0 otherwise. Handle them correctly in the MSR/MRS register access code. Neither is banked between security states, so they are stored in v7m.control[M_REG_S] regardless of current security state. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b4f1609a1c6..297eb38fef0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12032,7 +12032,14 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return xpsr_read(env) & mask; break; case 20: /* CONTROL */ - return env->v7m.control[env->v7m.secure]; + { + uint32_t value = env->v7m.control[env->v7m.secure]; + if (!env->v7m.secure) { + /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */ + value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; + } + return value; + } case 0x94: /* CONTROL_NS */ /* We have to handle this here because unprivileged Secure code * can read the NS CONTROL register. @@ -12040,7 +12047,8 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) if (!env->v7m.secure) { return 0; } - return env->v7m.control[M_REG_NS]; + return env->v7m.control[M_REG_NS] | + (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK); } if (el == 0) { @@ -12146,9 +12154,13 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) */ uint32_t mask = extract32(maskreg, 8, 4); uint32_t reg = extract32(maskreg, 0, 8); + int cur_el = arm_current_el(env); - if (arm_current_el(env) == 0 && reg > 7) { - /* only xPSR sub-fields may be written by unprivileged */ + if (cur_el == 0 && reg > 7 && reg != 20) { + /* + * only xPSR sub-fields and CONTROL.SFPA may be written by + * unprivileged code + */ return; } @@ -12207,6 +12219,15 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK; env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK; } + /* + * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0, + * RES0 if the FPU is not present, and is stored in the S bank + */ + if (arm_feature(env, ARM_FEATURE_VFP) && + extract32(env->v7m.nsacr, 10, 1)) { + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; + env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK; + } return; case 0x98: /* SP_NS */ { @@ -12309,21 +12330,41 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) env->v7m.faultmask[env->v7m.secure] = val & 1; break; case 20: /* CONTROL */ - /* Writing to the SPSEL bit only has an effect if we are in + /* + * Writing to the SPSEL bit only has an effect if we are in * thread mode; other bits can be updated by any privileged code. * write_v7m_control_spsel() deals with updating the SPSEL bit in * env->v7m.control, so we only need update the others. * For v7M, we must just ignore explicit writes to SPSEL in handler * mode; for v8M the write is permitted but will have no effect. + * All these bits are writes-ignored from non-privileged code, + * except for SFPA. */ - if (arm_feature(env, ARM_FEATURE_V8) || - !arm_v7m_is_handler_mode(env)) { + if (cur_el > 0 && (arm_feature(env, ARM_FEATURE_V8) || + !arm_v7m_is_handler_mode(env))) { write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); } - if (arm_feature(env, ARM_FEATURE_M_MAIN)) { + if (cur_el > 0 && arm_feature(env, ARM_FEATURE_M_MAIN)) { env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; } + if (arm_feature(env, ARM_FEATURE_VFP)) { + /* + * SFPA is RAZ/WI from NS or if no FPU. + * FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present. + * Both are stored in the S bank. + */ + if (env->v7m.secure) { + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; + env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_SFPA_MASK; + } + if (cur_el > 0 && + (env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_SECURITY) || + extract32(env->v7m.nsacr, 10, 1))) { + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; + env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK; + } + } break; default: bad_reg: From patchwork Tue Apr 16 12:57:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086296 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="e0Ilpe1N"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5971m1sz9s4Y for ; Tue, 16 Apr 2019 23:01:31 +1000 (AEST) Received: from localhost ([127.0.0.1]:36311 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNiL-0006tU-7Y for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:01:29 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNf8-0004cf-IM for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNf6-0001Bt-VT for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:10 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:36135) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNf6-00019V-KM for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:08 -0400 Received: by mail-wm1-x329.google.com with SMTP id h18so25326435wml.1 for ; Tue, 16 Apr 2019 05:58:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BFL/4mmLnGxA0smTiBCKZfrdKeTsfE6ZtDY8NLO49os=; b=e0Ilpe1NU8SWZ4EcFHTIQOONo+Vj7nYG75Oum+SzAr3zQfR5WwR9fkNbHE7r29s+pH oNnXCH/bHBS95C5VsCeXYTYVT7RAnRjDTQXdry0QwixKSit9jHCpKt0Chh97TY+16MqV kSz54y2buvyI5iR6cWQ4rG7Ff5yaoMz1dHzZKak0zzUVic+ku0oFv32ku53zzUfc+BfE MoKzbmfbtDnA7q4uoxTURYsz9Yj+EJEquh2dSosSK8K2J/JfZ5GGCiJVYV8WYeNCQAzO jiWvAQCAwTNib5RK9ADU8hbWniprDy7KzXyGzKbSjz/NKMyWITE9SD9Rg8tAmKDsBHrf clQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BFL/4mmLnGxA0smTiBCKZfrdKeTsfE6ZtDY8NLO49os=; b=dDvsKX18/oVOwLg+rQTMLsZo2HQIThsO9Ep8TlEDw/AR8AnNlNGQtIRnynclAM99UM b58hrZyx+IzZFThiIdT94aitYDGZZEtJ0nNiBM8e5dnH6/AXop1ayGwqW19AgMm2q+lD dn2JK/hmCaU9Sc7t29k6yD3fmWOq7pPUg0yFV+5BJieOsPergksYUp0qaPZwXzAZBjqi cOzf0gOGyB81dpv/LrHVDjve+4+7jZp3m94U2qolpB+3E+beBBuRfiSWgvSpxHnxVxa5 TkwCEPeO8KEbFYR7N3DV8Vh4lh6ae+uC9zAiuR/dltX7VIgcK650m5mgvvJdUGqf/ey0 drQw== X-Gm-Message-State: APjAAAWRUFl5WyspKHpIA7Rj+iAG9Im3NDe6SXDcX8ceTP7z3N0acm4D GSQvVDDIdLzQGw2QYG54yOfQtg== X-Google-Smtp-Source: APXvYqxSUXTBSAtxr7EyxlwJXcDSCBKJw/Gw/OU8s7s/Hcte2ShcoY/EwYvSyhFdzthzFWm5cHrnlQ== X-Received: by 2002:a1c:cfcb:: with SMTP id f194mr25672482wmg.51.1555419485136; Tue, 16 Apr 2019 05:58:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:27 +0100 Message-Id: <20190416125744.27770-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 Subject: [Qemu-devel] [PATCH 09/26] target/arm/helper: don't return early for STKOF faults during stacking X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Currently the code in v7m_push_stack() which detects a violation of the v8M stack limit simply returns early if it does so. This is OK for the current integer-only code, but won't work for the floating point handling we're about to add. We need to continue executing the rest of the function so that we check for other exceptions like not having permission to use the FPU and so that we correctly set the FPCCR state if we are doing lazy stacking. Refactor to avoid the early return. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 297eb38fef0..a2222f84803 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8187,7 +8187,7 @@ static bool v7m_push_stack(ARMCPU *cpu) * should ignore further stack faults trying to process * that derived exception.) */ - bool stacked_ok; + bool stacked_ok = true, limitviol = false; CPUARMState *env = &cpu->env; uint32_t xpsr = xpsr_read(env); uint32_t frameptr = env->regs[13]; @@ -8218,7 +8218,14 @@ static bool v7m_push_stack(ARMCPU *cpu) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); env->regs[13] = limit; - return true; + /* + * We won't try to perform any further memory accesses but + * we must continue through the following code to check for + * permission faults during FPU state preservation, and we + * must update FPCCR if lazy stacking is enabled. + */ + limitviol = true; + stacked_ok = false; } } @@ -8227,7 +8234,7 @@ static bool v7m_push_stack(ARMCPU *cpu) * (which may be taken in preference to the one we started with * if it has higher priority). */ - stacked_ok = + stacked_ok = stacked_ok && v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, false) && v7m_stack_write(cpu, frameptr + 4, env->regs[1], mmu_idx, false) && v7m_stack_write(cpu, frameptr + 8, env->regs[2], mmu_idx, false) && @@ -8237,8 +8244,14 @@ static bool v7m_push_stack(ARMCPU *cpu) v7m_stack_write(cpu, frameptr + 24, env->regs[15], mmu_idx, false) && v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, false); - /* Update SP regardless of whether any of the stack accesses failed. */ - env->regs[13] = frameptr; + /* + * If we broke a stack limit then SP was already updated earlier; + * otherwise we update SP regardless of whether any of the stack + * accesses failed or we took some other kind of fault. + */ + if (!limitviol) { + env->regs[13] = frameptr; + } return !stacked_ok; } From patchwork Tue Apr 16 12:57:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086299 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="nM9l7XCc"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5Cp20bdz9s3l for ; Tue, 16 Apr 2019 23:03:50 +1000 (AEST) Received: from localhost ([127.0.0.1]:36336 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNka-0000MS-51 for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:03:48 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34521) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNf9-0004dN-5P for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNf7-0001C6-2s for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:11 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:40152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNf6-0001Ai-O7 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:08 -0400 Received: by mail-wm1-x341.google.com with SMTP id z24so25491371wmi.5 for ; Tue, 16 Apr 2019 05:58:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=o6hagmVvoqqJ0XtX75gSSLbFcTrXtyoSJl24uehJGoY=; b=nM9l7XCc7gjhpeHvgu+2rSd3D+u1riAjplh5a0iOHP1PF007LI+WLvRwY2g7z2JUrw EgbRnZbmJaWmMx/k/vFPLnT0CCI7kSKVBeMcPEuJ8opB5qFaVPSmYxgQbOlfrlwsrR5o adwoCgte+R+1OuS6q2y8e3OGXHHMU+iMxftRXHir0iyeOm7UeYXhZ8EPkhTEcVQWpdQ5 Wh+oFGTqvUd2nPBjMez4HFcFihu0DmMtRbmFKxCrd/dWT6FhEb56FpjPMcd9Yc+bKrbc 1Dogx5jksBuBMT6v5U4xqUmIE4VsnYoUJCMMBMR5wV2T/agNgkeK8NxtOH4G/nKkqo7T X3pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o6hagmVvoqqJ0XtX75gSSLbFcTrXtyoSJl24uehJGoY=; b=J+MXuGDapQy18T14kTx/NIGlEIU7zc25r96ybWKKhn1JmF+KCLQ4InPep4zMiM9OKg x4uqvnfgIAWUHxFgVorr02i2UC+X3pYrsXYVl6qaCFVhQ/BAZu36Vnra8J435whQczmj TSOfyqTJqHv5fKY9JQkzQLL0/VvBQPWubG0GG6zmxZWvXkLYPRZYjX2dGxeeta5boDdT O+80CqJX1TWBdcVDr4QXKw7557Z3ozezRnKN/ZmWlY3w7TU6ACQlrGKybd82mSd5aWJf aHWoGWRkyXQHoN0kdxqqbWYOGEV/2Hx8suIHdJRCHfg//psEBoiL3NyekEFBb7jZNwiz 7zLA== X-Gm-Message-State: APjAAAWBQMTcYO2595791lcYcITk1BO+XAIfNMCp3O71U1MOe+vT6bNa 1RZ7PcXnyxDllUOKrMYtQaDggg== X-Google-Smtp-Source: APXvYqwuK/toMq2uHlf7IyhOlZ2Fnyz4B5Gf2gTS5ejcFd51fMLXplVndsNzOIbdUV/DgYqYARu6/w== X-Received: by 2002:a1c:804c:: with SMTP id b73mr25470401wmd.116.1555419487425; Tue, 16 Apr 2019 05:58:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:28 +0100 Message-Id: <20190416125744.27770-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 10/26] target/arm: Handle floating point registers in exception entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Handle floating point registers in exception entry. This corresponds to the FP-specific parts of the pseudocode functions ActivateException() and PushStack(). We defer the code corresponding to UpdateFPCCR() to a later patch. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 98 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 95 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a2222f84803..7b2174a5e61 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8172,6 +8172,9 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, switch_v7m_security_state(env, targets_secure); write_v7m_control_spsel(env, 0); arm_clear_exclusive(env); + /* Clear SFPA and FPCA (has no effect if no FPU) */ + env->v7m.control[M_REG_S] &= + ~(R_V7M_CONTROL_FPCA_MASK | R_V7M_CONTROL_SFPA_MASK); /* Clear IT bits */ env->condexec_bits = 0; env->regs[14] = lr; @@ -8192,6 +8195,20 @@ static bool v7m_push_stack(ARMCPU *cpu) uint32_t xpsr = xpsr_read(env); uint32_t frameptr = env->regs[13]; ARMMMUIdx mmu_idx = arm_mmu_idx(env); + uint32_t framesize; + bool nsacr_cp10 = extract32(env->v7m.nsacr, 10, 1); + + if ((env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) && + (env->v7m.secure || nsacr_cp10)) { + if (env->v7m.secure && + env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK) { + framesize = 0xa8; + } else { + framesize = 0x68; + } + } else { + framesize = 0x20; + } /* Align stack pointer if the guest wants that */ if ((frameptr & 4) && @@ -8200,7 +8217,13 @@ static bool v7m_push_stack(ARMCPU *cpu) xpsr |= XPSR_SPREALIGN; } - frameptr -= 0x20; + xpsr &= ~XPSR_SFPA; + if (env->v7m.secure && + (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { + xpsr |= XPSR_SFPA; + } + + frameptr -= framesize; if (arm_feature(env, ARM_FEATURE_V8)) { uint32_t limit = v7m_sp_limit(env); @@ -8244,6 +8267,73 @@ static bool v7m_push_stack(ARMCPU *cpu) v7m_stack_write(cpu, frameptr + 24, env->regs[15], mmu_idx, false) && v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, false); + if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) { + /* FPU is active, try to save its registers */ + bool fpccr_s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + bool lspact = env->v7m.fpccr[fpccr_s] & R_V7M_FPCCR_LSPACT_MASK; + + if (lspact && arm_feature(env, ARM_FEATURE_M_SECURITY)) { + qemu_log_mask(CPU_LOG_INT, + "...SecureFault because LSPACT and FPCA both set\n"); + env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + } else if (!env->v7m.secure && !nsacr_cp10) { + qemu_log_mask(CPU_LOG_INT, + "...Secure UsageFault with CFSR.NOCP because " + "NSACR.CP10 prevents stacking FP regs\n"); + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, M_REG_S); + env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; + } else { + if (!(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPEN_MASK)) { + /* Lazy stacking disabled, save registers now */ + int i; + bool cpacr_pass = v7m_cpacr_pass(env, env->v7m.secure, + arm_current_el(env) != 0); + + if (stacked_ok && !cpacr_pass) { + /* + * Take UsageFault if CPACR forbids access. The pseudocode + * here does a full CheckCPEnabled() but we know the NSACR + * check can never fail as we have already handled that. + */ + qemu_log_mask(CPU_LOG_INT, + "...UsageFault with CFSR.NOCP because " + "CPACR.CP10 prevents stacking FP regs\n"); + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + env->v7m.secure); + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; + stacked_ok = false; + } + + for (i = 0; i < ((framesize == 0xa8) ? 32 : 16); i += 2) { + uint64_t dn = *aa32_vfp_dreg(env, i / 2); + uint32_t faddr = frameptr + 0x20 + 4 * i; + uint32_t slo = extract64(dn, 0, 32); + uint32_t shi = extract64(dn, 32, 32); + + if (i >= 16) { + faddr += 8; /* skip the slot for the FPSCR */ + } + stacked_ok = stacked_ok && + v7m_stack_write(cpu, faddr, slo, mmu_idx, false) && + v7m_stack_write(cpu, faddr + 4, shi, mmu_idx, false); + } + stacked_ok = stacked_ok && + v7m_stack_write(cpu, frameptr + 0x60, + vfp_get_fpscr(env), mmu_idx, false); + if (cpacr_pass) { + for (i = 0; i < ((framesize == 0xa8) ? 32 : 16); i += 2) { + *aa32_vfp_dreg(env, i / 2) = 0; + } + vfp_set_fpscr(env, 0); + } + } else { + /* Lazy stacking enabled, save necessary info to stack later */ + /* TODO : equivalent of UpdateFPCCR() pseudocode */ + } + } + } + /* * If we broke a stack limit then SP was already updated earlier; * otherwise we update SP regardless of whether any of the stack @@ -9004,8 +9094,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) if (arm_feature(env, ARM_FEATURE_V8)) { lr = R_V7M_EXCRET_RES1_MASK | - R_V7M_EXCRET_DCRS_MASK | - R_V7M_EXCRET_FTYPE_MASK; + R_V7M_EXCRET_DCRS_MASK; /* The S bit indicates whether we should return to Secure * or NonSecure (ie our current state). * The ES bit indicates whether we're taking this exception @@ -9020,6 +9109,9 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) if (env->v7m.secure) { lr |= R_V7M_EXCRET_S_MASK; } + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { + lr |= R_V7M_EXCRET_FTYPE_MASK; + } } else { lr = R_V7M_EXCRET_RES1_MASK | R_V7M_EXCRET_S_MASK | From patchwork Tue Apr 16 12:57:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086302 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ovd5Dugt"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5FX0hc2z9s3l for ; Tue, 16 Apr 2019 23:05:20 +1000 (AEST) Received: from localhost ([127.0.0.1]:36353 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNm2-0001X9-1d for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:05:18 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34611) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfF-0004nE-Rp for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfE-0001Hj-1K for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:17 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:41751) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfC-0001FV-3r for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:15 -0400 Received: by mail-wr1-x444.google.com with SMTP id r4so26906579wrq.8 for ; Tue, 16 Apr 2019 05:58:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4RdrN7GA3r8yy/LIQmPOrXRIGWZZCxjf6XHcNWaC7So=; b=ovd5Dugtc5ym8g6PNqfZgcpHhg8AICVBnHu06SPNW74TVUkJqXw7Q4dL2WbUQG8tQZ ey30lUhD6FnhOshEJLjR+ADKuMrQy49kitMImXJbkN4U6dsZdhwmUkqYvbwxfwipKGr9 oQpK9l1yyRGBFNw6+PqqT+qbu/mDqUd8wBOKHvCayvRZwnHvqAmFlf/NYNQ42//3x36a pwUwDjv412D4HLSlZWrK3pZacVLYvmMOzHw026Oby6qbAfP0NOwsRIx0lcFoqofJSTkY ByjyOLhfTi7QQDLF0f8CZ5dPHZTgUfNXC96EagTi2wUz6ipuCanJWh7+XemBUGWrGsT+ 1Thw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4RdrN7GA3r8yy/LIQmPOrXRIGWZZCxjf6XHcNWaC7So=; b=JgcYV2DHE+R/59fo43cXb5CLuMP3Rl/v+uAJ5+2Ltqs/du6avzQEYJNZLro1lw8zBh RZZGYR90jK521K5S9dtB2fpXYUDkNk60M/e4I4DbISI5UrsoefzWQyLkAGhXqa8NAS1v iHZ05A+1kDKW7onhCtSrMz5pOqvQatiEjWganaTSVfnj7x3WY79Xuv/3wruiVyiXgVTS V/tWvWqw+4JvfBv3qCWe6L+/XRCZkBcmMXeI+GzFeIYLBm+nzUJ7Dl8Fg3eHv32xyxSe tkwdKZxkpG4DHRPVlHzJJ9czahlsvaGRVTrMTSLRUpzjz4oE7zbpVbPBmNjAovXgBNmP f+kA== X-Gm-Message-State: APjAAAVuXUHxJqJ/J6QyA9dyZvb3THzZAa2nF0P31ndYF84UEHBa0L4+ XoDMZn6Oa5yJm0e/KJLd5GeCkA== X-Google-Smtp-Source: APXvYqxXrryAM+9Mf6N9ZqhYorAGtC0xnGFAQDrlTehf6yI2CVMmAyw8TajpxRB0nkB17yWN1YHB+w== X-Received: by 2002:a5d:448b:: with SMTP id j11mr18983611wrq.218.1555419491605; Tue, 16 Apr 2019 05:58:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:29 +0100 Message-Id: <20190416125744.27770-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 11/26] target/arm: Implement v7m_update_fpccr() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Implement the code which updates the FPCCR register on an exception entry where we are going to use lazy FP stacking. We have to defer to the NVIC to determine whether the various exceptions are currently ready or not. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 14 +++++++++ hw/intc/armv7m_nvic.c | 34 ++++++++++++++++++++++ target/arm/helper.c | 67 ++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 114 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c8d78bd5b52..0e0cb6b2271 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2045,6 +2045,20 @@ void armv7m_nvic_acknowledge_irq(void *opaque); * (Ignoring -1, this is the same as the RETTOBASE value before completion.) */ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); +/** + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) + * @opaque: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Return whether an exception is "ready", i.e. whether the exception is + * enabled and is configured at a priority which would allow it to + * interrupt the current execution priority. This controls whether the + * RDY bit for it in the FPCCR is set. + */ +bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); /** * armv7m_nvic_raw_execution_priority: return the raw execution priority * @opaque: the NVIC diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5eb438f5409..53b4631dace 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -746,6 +746,40 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) return ret; } +bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) +{ + /* + * Return whether an exception is "ready", i.e. it is enabled and is + * configured at a priority which would allow it to interrupt the + * current execution priority. + * + * irq and secure have the same semantics as for armv7m_nvic_set_pending(): + * for non-banked exceptions secure is always false; for banked exceptions + * it indicates which of the exceptions is required. + */ + NVICState *s = (NVICState *)opaque; + bool banked = exc_is_banked(irq); + VecInfo *vec; + int running = nvic_exec_prio(s); + + assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); + assert(!secure || banked); + + /* + * HardFault is an odd special case: we always check against -1, + * even if we're secure and HardFault has priority -3; we never + * need to check for enabled state. + */ + if (irq == ARMV7M_EXCP_HARD) { + return running > -1; + } + + vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; + + return vec->enabled && + exc_group_prio(s, vec->prio, secure) < running; +} + /* callback when external interrupt line is changed */ static void set_irq_level(void *opaque, int n, int level) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b2174a5e61..7298f9de735 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8182,6 +8182,71 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, env->thumb = addr & 1; } +static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, + bool apply_splim) +{ + /* + * Like the pseudocode UpdateFPCCR: save state in FPCAR and FPCCR + * that we will need later in order to do lazy FP reg stacking. + */ + bool is_secure = env->v7m.secure; + void *nvic = env->nvic; + /* + * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits + * are banked and we want to update the bit in the bank for the + * current security state; and in one case we want to specifically + * update the NS banked version of a bit even if we are secure. + */ + uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; + uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; + uint32_t *fpccr = &env->v7m.fpccr[is_secure]; + bool hfrdy, bfrdy, mmrdy, ns_ufrdy, s_ufrdy, sfrdy, monrdy; + + env->v7m.fpcar[is_secure] = frameptr & ~0x7; + + if (apply_splim && arm_feature(env, ARM_FEATURE_V8)) { + bool splimviol; + uint32_t splim = v7m_sp_limit(env); + bool ign = armv7m_nvic_neg_prio_requested(nvic, is_secure) && + (env->v7m.ccr[is_secure] & R_V7M_CCR_STKOFHFNMIGN_MASK); + + splimviol = !ign && frameptr < splim; + *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); + } + + *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); + + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, S, is_secure); + + *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); + + *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, + !arm_v7m_is_handler_mode(env)); + + hfrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_HARD, false); + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, HFRDY, hfrdy); + + bfrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_BUS, false); + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, BFRDY, bfrdy); + + mmrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_MEM, is_secure); + *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); + + ns_ufrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_USAGE, false); + *fpccr_ns = FIELD_DP32(*fpccr_ns, V7M_FPCCR, UFRDY, ns_ufrdy); + + monrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_DEBUG, false); + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, MONRDY, monrdy); + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + s_ufrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_USAGE, true); + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, UFRDY, s_ufrdy); + + sfrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_SECURE, false); + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, SFRDY, sfrdy); + } +} + static bool v7m_push_stack(ARMCPU *cpu) { /* Do the "set up stack frame" part of exception entry, @@ -8329,7 +8394,7 @@ static bool v7m_push_stack(ARMCPU *cpu) } } else { /* Lazy stacking enabled, save necessary info to stack later */ - /* TODO : equivalent of UpdateFPCCR() pseudocode */ + v7m_update_fpccr(env, frameptr + 0x20, true); } } } From patchwork Tue Apr 16 12:57:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086306 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="qjaG4u+B"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5Jw0TsKz9s3l for ; Tue, 16 Apr 2019 23:08:16 +1000 (AEST) Received: from localhost ([127.0.0.1]:36415 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNor-0004C8-U9 for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:08:14 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34633) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfH-0004p0-Ox for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfF-0001KM-Re for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:19 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:52376) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfE-0001Gi-0u for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:16 -0400 Received: by mail-wm1-x342.google.com with SMTP id a184so25245569wma.2 for ; Tue, 16 Apr 2019 05:58:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bCGhrFJCaebvft5wSyxUMGmlJpa7UGyDkhV61Ort2ak=; b=qjaG4u+B8c572MSbsULByl5VX/0zRQ+L52wPypDWoh1Eot99rfJMr61cOKpUAK59QS bwjjitRG4nUQjKKpavAIdNay8oW9nJ5TiFZGhiNz9ysU6w7S4xoxPgQTPrMGIEqMdoWK fmErIhKS9Si8MDYGH5vgobYEVwBpw71GXF9OTnNCTioy/1X68id2BXNrhhUhjh00+QB1 g/WN1IuJavxstMeU/A5mDHp3ri9XPvARlUYGyeKO6rn/LmauxuE/C1wG3z1Ms5V3IYhk OdnMH46OKDVsKsx1HI1OZgGlLlfAmjB3R/JhSQF0gv8uqAuBmbi+xKE9yyFRpwiPi1EI pusA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bCGhrFJCaebvft5wSyxUMGmlJpa7UGyDkhV61Ort2ak=; b=aLqWW+WJ9wiq36rvKfIUblBiJwnFKbJAO2LaSn06AKQrfckiW7PUDWeyagnUzfOSie yWlgxxOz+sNHPU0GTI/04QlYECe/ne+xc7c4ue5Orvt6wf1WDTjMGwm/SNP4x3COkvGK aWSu74o3iAf7So1Rs7q96LnwHeINmxLKtwLzSryFbspLTkNUyOUuczGzNVrjoMuFzkCy BJP5qK/QbwPItUsBl8NziXJ8dVOF9G7PrkzgCECRWGvGb1oT4AcNrXtBMmjYoRQH6HpA FsljueztQuAAmsqBQPEr1mSUklPpze0ZhchjOopoYS1SPmB5GLn9nvo+H1ySszonWE01 5Y1A== X-Gm-Message-State: APjAAAXPoQ00j4OyQXt1oI8oUJG5qLn9nHdXXv1FDj+NHT840wmbEKbv csitrjFJnlxwHUARPjmt2WnquvFNP1g= X-Google-Smtp-Source: APXvYqy9M8IsyDCKuaiXcryzNE3LeBIw8g6c652NhSYSHtV9qFSaKp7iFIp5aL0ddVRrYzNZ8hVhbg== X-Received: by 2002:a1c:c8:: with SMTP id 191mr25804221wma.44.1555419493999; Tue, 16 Apr 2019 05:58:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:30 +0100 Message-Id: <20190416125744.27770-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 12/26] target/arm: Clear CONTROL.SFPA in BXNS and BLXNS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" For v8M floating point support, transitions from Secure to Non-secure state via BLNS and BLXNS must clear the CONTROL.SFPA bit. (This corresponds to the pseudocode BranchToNS() function.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7298f9de735..8e72e1097ce 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7824,6 +7824,9 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) /* translate.c should have made BXNS UNDEF unless we're secure */ assert(env->v7m.secure); + if (!(dest & 1)) { + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; + } switch_v7m_security_state(env, dest & 1); env->thumb = 1; env->regs[15] = dest & ~1; @@ -7881,6 +7884,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) */ write_v7m_exception(env, 1); } + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; switch_v7m_security_state(env, 0); env->thumb = 1; env->regs[15] = dest; From patchwork Tue Apr 16 12:57:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086303 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="aQXh9TLC"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5HK16KTz9s3l for ; Tue, 16 Apr 2019 23:06:53 +1000 (AEST) Received: from localhost ([127.0.0.1]:36397 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNnX-0002ro-3P for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:06:51 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34667) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfJ-0004r7-PC for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfH-0001Lw-TS for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:21 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:43399) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfF-0001I5-Qd for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:19 -0400 Received: by mail-wr1-x441.google.com with SMTP id k17so22247627wrx.10 for ; Tue, 16 Apr 2019 05:58:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1XGXCtBKeeVzqgmtbhUu5EKggmcEdNkp9mStUCKfAYg=; b=aQXh9TLCiBDKxxFyc7z9c676WM+L2EGWTfMRBCFMewS+xTqueC6QV3JY+RO/rOdQri ei1Hz8LZ7SXdlnP+0obacr6NjovfYJVVUCJtH3O3OUrUVspkV5vqZzyz0TxP8JJIaGfV 3C1s8WRE5W+InPTOebW+oCRxicrDZg5he7neg9m/AeWRvL8HjcHMuxlKamq9fJ5ZA+rG EOHaLy23Sr1Q8j4tLH5qz/BC2oX91/tzY3UW2l+0aG7re+wnwaGg8etVOEE/uoLjv7ys yFXEPIqo83/0MqzOlD3xHD8ASh01fIJyD/BLiQ832DYajG8co0IulFeWauGHHEaTCbW5 RR4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1XGXCtBKeeVzqgmtbhUu5EKggmcEdNkp9mStUCKfAYg=; b=U5+jmnfRuZ2iFrowJYtT49iM4/F5bBetmcFyCJ82NuS/DeQf26vMfaVM8yhOmJXpyc 2PaV7J1LMqujlWlK+8KR0LWB9ZGjFvdazN5vM3KwKf4sNyDObbsBJX39hiBVdV8eoyeT KHnGh0Go2Bjr2h8XV/lN8m41/rDVCGrfaRV73f2xa6Q0Xkp+7gdQ5h1CVqBZkDxNxezQ 5u7rnz0khC+/C5LI2AtvRbjWAbGJJM0QNbRHKso88tRVVRFXSqx65POzQHePgS5iWneq fTBbNeBlZyFXD4hr5nBypWRt8EPlRpY9UDhgHcrjkkQ3Shc/SFsudZoXCKu/xSnRAmfQ fEHw== X-Gm-Message-State: APjAAAUPCqhhABrcmKCc1hYX6aMugcNJ0QYxVTeNkF+jQXrkYTFs/HkH dJ/96YqUTA5b4Y3Y96yx3p4ZAA== X-Google-Smtp-Source: APXvYqwRFMBP2LN+h0ov2Of/tRKw4IqMefPh9rJJR2iTWY+3QhpIn0eg86yc4q4dCAeBTarObDlDqg== X-Received: by 2002:adf:ec0a:: with SMTP id x10mr51756800wrn.193.1555419496176; Tue, 16 Apr 2019 05:58:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:31 +0100 Message-Id: <20190416125744.27770-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 13/26] target/arm: Clean excReturn bits when tail chaining X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The TailChain() pseudocode specifies that a tail chaining exception should sanitize the excReturn all-ones bits and (if there is no FPU) the excReturn FType bits; we weren't doing this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8e72e1097ce..fe8e78fe36d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8081,6 +8081,14 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, qemu_log_mask(CPU_LOG_INT, "...taking pending %s exception %d\n", targets_secure ? "secure" : "nonsecure", exc); + if (dotailchain) { + /* Sanitize LR FType and PREFIX bits */ + if (!arm_feature(env, ARM_FEATURE_VFP)) { + lr |= R_V7M_EXCRET_FTYPE_MASK; + } + lr = deposit32(lr, 24, 8, 0xff); + } + if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_M_SECURITY) && (lr & R_V7M_EXCRET_S_MASK)) { From patchwork Tue Apr 16 12:57:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086309 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="HreNCUuv"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5NH6Jvvz9s3l for ; Tue, 16 Apr 2019 23:11:11 +1000 (AEST) Received: from localhost ([127.0.0.1]:36522 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNrh-0006l8-R6 for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:11:09 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfJ-0004r8-PB for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfI-0001M6-2A for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:21 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:36148) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfH-0001Kz-Oi for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:19 -0400 Received: by mail-wm1-x335.google.com with SMTP id h18so25327460wml.1 for ; Tue, 16 Apr 2019 05:58:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oKhQw5TgUN0CJPeTbE7gAN8kI/N1+VlPzRCCDtvAZtE=; b=HreNCUuvD0e5wQi79dWBWrQu3YZa7sNIr2l3kmLrc2xcNsq2h4683HclK6gO+ngrci JJCuYA9A+T3gDvIW5mvk/0YPo05OjNJPFsN30neivj+YJUQlyAaeqyvJ6x5QHcs/JA+Z mbwKJHL3UQ+lS5P3LS61SMqJtpC6sM3DxeS9KkXybVqskZjkVJ4vxMYljFnzXNS5wfSc e2fHGU4zj346ylL09uE5ZbVKuucmEf4ZIid7mtvQ2NSAi5qo9DHtONczqaqoDE5zLaoI glpWQUuAo2XasdZsXGjn+jq/KXlEbUCzgkNYNgjK415krxxnEYIjEFOJhAQP5hQ12jtE WZqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oKhQw5TgUN0CJPeTbE7gAN8kI/N1+VlPzRCCDtvAZtE=; b=DVjwx+7CrrksnODN3sXmSDI0FgZo1Lvk+0QWqGP02CFBsKE5Wjn0DGcGu817dDfXGF HnyAlUKrIWlYjXaXbZU9H1xSPEksSmhV7MM24jgg/QCDey8Tz8epAQuqazwjvKAki70x ZbyrYrTX1lYSG8yqDf6Conw6qeV8bBSPSGSOoRe0LGtn//oC7baDHNBblq100uw84vxQ WwWRP/MtEa6qw2YriIrderWItWx9NBmbOX9vry9NxDIMhKQ6RHO1Qa8sbjvMWIODQxVX R18Cw/oY5B1PGQCGcZyNILItMLsBjukwmgSbnHHfmuenW7tL263/DZo7mB9s+f1LOtwh AYNA== X-Gm-Message-State: APjAAAXkDd22i93gXAjGSZNiNg/VK/HTdk8xywVGAMJE+4mfT6tBt3q3 czxvFQZwAAlRjzWu5nBz+JBPYQ== X-Google-Smtp-Source: APXvYqwl95al5Y3LOtRhbHMoOQ56YCImnsEa1pPOHGSI6GwjogiYdO5Gdp59W8agAfVht11CsZdYyA== X-Received: by 2002:a1c:f204:: with SMTP id s4mr26600232wmc.51.1555419498715; Tue, 16 Apr 2019 05:58:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:32 +0100 Message-Id: <20190416125744.27770-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PATCH 14/26] target/arm: Allow for floating point in callee stack integrity check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The magic value pushed onto the callee stack as an integrity check is different if floating point is present. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fe8e78fe36d..2f6382a0b24 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7984,6 +7984,21 @@ load_fail: return false; } +static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr) +{ + /* + * Return the integrity signature value for the callee-saves + * stack frame section. @lr is the exception return payload/LR value + * whose FType bit forms bit 0 of the signature if FP is present. + */ + uint32_t sig = 0xfefa125a; + + if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) { + sig |= 1; + } + return sig; +} + static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, bool ignore_faults) { @@ -7998,6 +8013,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, bool stacked_ok; uint32_t limit; bool want_psp; + uint32_t sig; if (dotailchain) { bool mode = lr & R_V7M_EXCRET_MODE_MASK; @@ -8039,8 +8055,9 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, /* Write as much of the stack frame as we can. A write failure may * cause us to pend a derived exception. */ + sig = v7m_integrity_sig(env, lr); stacked_ok = - v7m_stack_write(cpu, frameptr, 0xfefa125b, mmu_idx, ignore_faults) && + v7m_stack_write(cpu, frameptr, sig, mmu_idx, ignore_faults) && v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, ignore_faults) && v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, @@ -8645,12 +8662,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu) if (return_to_secure && ((excret & R_V7M_EXCRET_ES_MASK) == 0 || (excret & R_V7M_EXCRET_DCRS_MASK) == 0)) { - uint32_t expected_sig = 0xfefa125b; uint32_t actual_sig; pop_ok = v7m_stack_read(cpu, &actual_sig, frameptr, mmu_idx); - if (pop_ok && expected_sig != actual_sig) { + if (pop_ok && v7m_integrity_sig(env, excret) != actual_sig) { /* Take a SecureFault on the current stack */ env->v7m.sfsr |= R_V7M_SFSR_INVIS_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); From patchwork Tue Apr 16 12:57:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086308 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="zy2uDehV"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5NG1ynGz9s4Y for ; Tue, 16 Apr 2019 23:11:10 +1000 (AEST) Received: from localhost ([127.0.0.1]:36520 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNrg-0006jY-7J for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:11:08 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34748) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfS-0004z1-AT for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfN-0001PM-K2 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:28 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:34510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfK-0001Mh-Qp for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:23 -0400 Received: by mail-wr1-x444.google.com with SMTP id p10so26961548wrq.1 for ; Tue, 16 Apr 2019 05:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=M6YsTZmkfRPAVVPXWR3cTPfqQ0kgquDwuZQ8eOlURow=; b=zy2uDehVaYwTHSSZiJm9lwlfha6VCERGNaEq3aL1RhtDHeeAISai2UtJ8IaG04ho/J g8u2qrImufA6eQWgx8q2oztya+bmFbFjlyNjfoULblZIpIVd2ZGunvAgicMOqEEXla0q ZbEtOS9BgTQs9xWB0e5C8TqKcY348tWXmOwHOKgxouZTWXnHHN4d2Cg7p+/kmFgbzffv YtBS5e+1vvQI/VBvG3C/RjHL0tOwW+LbwwWwktsf9EZdCvINYKmounrT57QRAgqmBsJL 5IJyuF3AZubx/Ct2IfyF2QtO5snD0tV6GV2mYsKYLxPSTdQRCx7OF675ZWsbF+JcK2n0 qumA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M6YsTZmkfRPAVVPXWR3cTPfqQ0kgquDwuZQ8eOlURow=; b=HecbOA60cKDQIfWamjYVbZJ/nlxjrxuPfvU92MAddOB+cKp9JCzl1vvQtNgyS0nR0Z UfGuiCHse/FWAHhn5UJWxAlrJZFqG14wK48znWpf8duPH8ljNgFZWdfxjXc/3hMzUDAE hUjDciCQK6ItxVEtoXKvoYc/q5iRrhgHAAMdHDjZSqA96sggm8F5cHfInqNAL4cRwk9e PFUeGeRyzUK4bWy1/INqUv14njDo8xhd1rF7V71WNoIObrv6t3InE7v04LvYTw9Wn1q3 eVlcUU2o8EAbqk2HLnDCKY76ViJvG7uFPKYqoYRdUTwzRokmRrqd2lo4H3s2Ft8OJszD Rcvg== X-Gm-Message-State: APjAAAXi5KYKu98K8E9PC6pfukZVfbEmsFhUS++gBAQYlYrM4Z5u8q91 +Kwvy1gRa+xN4XC5x4ZE7MLzYA== X-Google-Smtp-Source: APXvYqwrrXjXv/GHwsMBfT51lCrON5Fs65VmoE2lvBxvcv3tDGx1cEVdfL81VvvaXgUcnjIfezxVHg== X-Received: by 2002:adf:fa86:: with SMTP id h6mr50152907wrr.67.1555419500879; Tue, 16 Apr 2019 05:58:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:33 +0100 Message-Id: <20190416125744.27770-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 15/26] target/arm: Handle floating point registers in exception return X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Handle floating point registers in exception return. This corresponds to pseudocode functions ValidateExceptionReturn(), ExceptionReturn(), PopStack() and ConsumeExcStackFrame(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 142 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 141 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2f6382a0b24..0c5b0a73e95 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8452,6 +8452,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) bool rettobase = false; bool exc_secure = false; bool return_to_secure; + bool ftype; + bool restore_s16_s31; /* If we're not in Handler mode then jumps to magic exception-exit * addresses don't have magic behaviour. However for the v8M @@ -8489,6 +8491,16 @@ static void do_v7m_exception_exit(ARMCPU *cpu) excret); } + ftype = excret & R_V7M_EXCRET_FTYPE_MASK; + + if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { + qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception " + "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " + "if FPU not present\n", + excret); + ftype = true; + } + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { /* EXC_RETURN.ES validation check (R_SMFL). We must do this before * we pick which FAULTMASK to clear. @@ -8589,6 +8601,30 @@ static void do_v7m_exception_exit(ARMCPU *cpu) */ write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_secure); + /* + * Clear scratch FP values left in caller saved registers; this + * must happen before any kind of tail chaining. + */ + if ((env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_CLRONRET_MASK) && + (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { + if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) { + env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " + "stackframe: error during lazy state deactivation\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } else { + /* Clear s0..s15 and FPSCR */ + int i; + + for (i = 0; i < 16; i += 2) { + *aa32_vfp_dreg(env, i / 2) = 0; + } + vfp_set_fpscr(env, 0); + } + } + if (sfault) { env->v7m.sfsr |= R_V7M_SFSR_INVER_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); @@ -8750,8 +8786,105 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } } + if (!ftype) { + /* FP present and we need to handle it */ + if (!return_to_secure && + (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK)) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; + qemu_log_mask(CPU_LOG_INT, + "...taking SecureFault on existing stackframe: " + "Secure LSPACT set but exception return is " + "not to secure state\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } + + restore_s16_s31 = return_to_secure && + (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); + + if (env->v7m.fpccr[return_to_secure] & R_V7M_FPCCR_LSPACT_MASK) { + /* State in FPU is still valid, just clear LSPACT */ + env->v7m.fpccr[return_to_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; + } else { + int i; + uint32_t fpscr; + bool cpacr_pass, nsacr_pass; + + cpacr_pass = v7m_cpacr_pass(env, return_to_secure, + return_to_priv); + nsacr_pass = return_to_secure || + extract32(env->v7m.nsacr, 10, 1); + + if (!cpacr_pass) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + return_to_secure); + env->v7m.cfsr[return_to_secure] |= R_V7M_CFSR_NOCP_MASK; + qemu_log_mask(CPU_LOG_INT, + "...taking UsageFault on existing " + "stackframe: CPACR.CP10 prevents unstacking " + "FP regs\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } else if (!nsacr_pass) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, true); + env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_INVPC_MASK; + qemu_log_mask(CPU_LOG_INT, + "...taking Secure UsageFault on existing " + "stackframe: NSACR.CP10 prevents unstacking " + "FP regs\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } + + for (i = 0; i < (restore_s16_s31 ? 32 : 16); i += 2) { + uint32_t slo, shi; + uint64_t dn; + uint32_t faddr = frameptr + 0x20 + 4 * i; + + if (i >= 16) { + faddr += 8; /* Skip the slot for the FPSCR */ + } + + pop_ok = pop_ok && + v7m_stack_read(cpu, &slo, faddr, mmu_idx) && + v7m_stack_read(cpu, &shi, faddr + 4, mmu_idx); + + if (!pop_ok) { + break; + } + + dn = (uint64_t)shi << 32 | slo; + *aa32_vfp_dreg(env, i / 2) = dn; + } + pop_ok = pop_ok && + v7m_stack_read(cpu, &fpscr, frameptr + 0x60, mmu_idx); + if (pop_ok) { + vfp_set_fpscr(env, fpscr); + } + if (!pop_ok) { + /* + * These regs are 0 if security extension present; + * otherwise merely UNKNOWN. We zero always. + */ + for (i = 0; i < (restore_s16_s31 ? 32 : 16); i += 2) { + *aa32_vfp_dreg(env, i / 2) = 0; + } + vfp_set_fpscr(env, 0); + } + } + } + env->v7m.control[M_REG_S] = FIELD_DP32(env->v7m.control[M_REG_S], + V7M_CONTROL, FPCA, !ftype); + /* Commit to consuming the stack frame */ frameptr += 0x20; + if (!ftype) { + frameptr += 0x48; + if (restore_s16_s31) { + frameptr += 0x40; + } + } /* Undo stack alignment (the SPREALIGN bit indicates that the original * pre-exception SP was not 8-aligned and we added a padding word to * align it, so we undo this by ORing in the bit that increases it @@ -8764,7 +8897,14 @@ static void do_v7m_exception_exit(ARMCPU *cpu) *frame_sp_p = frameptr; } /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */ - xpsr_write(env, xpsr, ~XPSR_SPREALIGN); + xpsr_write(env, xpsr, ~(XPSR_SPREALIGN | XPSR_SFPA)); + + if (env->v7m.secure) { + bool sfpa = xpsr & XPSR_SFPA; + + env->v7m.control[M_REG_S] = FIELD_DP32(env->v7m.control[M_REG_S], + V7M_CONTROL, SFPA, sfpa); + } /* The restored xPSR exception field will be zero if we're * resuming in Thread mode. If that doesn't match what the From patchwork Tue Apr 16 12:57:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086307 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="A9vP0bpk"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5NB27Zsz9s3l for ; Tue, 16 Apr 2019 23:11:06 +1000 (AEST) Received: from localhost ([127.0.0.1]:36514 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNrb-0006dL-VP for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:11:04 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfQ-0004y1-Ob for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfN-0001Ph-P6 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:27 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:36439) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfL-0001Na-Mv for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:25 -0400 Received: by mail-wr1-x442.google.com with SMTP id y13so26979473wrd.3 for ; Tue, 16 Apr 2019 05:58:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tbRH/Ezbfxbs3Pgygk5ZQu6eKyrO+ofFIElvSltfNOo=; b=A9vP0bpklygXGRW0rxA0JfeHZRuzpet/z9aiLVI13QTur7CangcXFT15WZhWyGz4rD vcshJX0Yb6E6KhAPvL+/Sylnc0izQHA21p8aWkNDjephbziESyRc5Y/wUCi/OprmbyZ/ kdcfm55GuNrIPMLEqMoPTzNpmsowRD5O4Ra5Xi8+11DyxiGcAl5t4lHcLVLJfT/JFJ5+ 2q/6+5IxTb7163KpS0l3U17skby3qtc7JBxfKcjtiFbBh0bAWvjqmyiD4kRjt+nH5Wo6 YbJKse8K5Bf7YYph8nNNlnc+ovkCFS9bbUJsO/JV4eVTutCDj3I1cIBFFvazHbmezZ6I R1sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tbRH/Ezbfxbs3Pgygk5ZQu6eKyrO+ofFIElvSltfNOo=; b=bkp8VbZEV8d5mpUp32TiSBTp/SBu10EUBIWmAayyOEp3Z+7k7vv5FrJ2JEtGr9lwy+ P3T5E9UmKtX6sdaaxpIfqygGEia8qegVuWTUIrnaS1yht3PpPTjF5lUJkP7+3BWUiHBq GBZ9W0+A/vy2mNezqS41ODVkyC/M63oWZZcgiZGduwJoi6QNyf9rsVUeP3TRjrHayOEk pDUX3SYuy+IgY1l+IMonWyN0ai8n/41WZbEr3D1cNvhC4V9Wef6rBcXe1krBg5Mj3QXk PZXRE/pt+GrxXV/jOUEPjZqmoJFWATQKq6glGgZjouPG/qJh0Trt4ZcjpRZhqKikOjgi dMJg== X-Gm-Message-State: APjAAAVNz1CDUk1ie4iqFE/JNMIQUbNjh3seWtcgR4Pd6+94IsMVyIhU lj/MmA6bhQL7wPzux/9WP0OfwtDYBZc= X-Google-Smtp-Source: APXvYqxSkPDEd2caSBKIaLh1p9TG26HbNa+sKD0jXmnYtpijNzsNIimzvnMqVhgMYo4OZTzDmDPUTg== X-Received: by 2002:adf:efc1:: with SMTP id i1mr51646257wrp.199.1555419502123; Tue, 16 Apr 2019 05:58:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:34 +0100 Message-Id: <20190416125744.27770-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 16/26] target/arm: Move NS TBFLAG from bit 19 to bit 6 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Move the NS TBFLAG down from bit 19 to bit 6, which has not been used since commit c1e3781090b9d36c60 in 2015, when we started passing the entire MMU index in the TB flags rather than just a 'privilege level' bit. This rearrangement is not strictly necessary, but means that we can put M-profile-only bits next to each other rather than scattered across the flag word. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0e0cb6b2271..c436f628987 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3139,6 +3139,12 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) FIELD(TBFLAG_A32, THUMB, 0, 1) FIELD(TBFLAG_A32, VECLEN, 1, 3) FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +/* + * Indicates whether cp register reads and writes by guest code should access + * the secure or nonsecure bank of banked registers; note that this is not + * the same thing as the current security state of the processor! + */ +FIELD(TBFLAG_A32, NS, 6, 1) FIELD(TBFLAG_A32, VFPEN, 7, 1) FIELD(TBFLAG_A32, CONDEXEC, 8, 8) FIELD(TBFLAG_A32, SCTLR_B, 16, 1) @@ -3146,11 +3152,6 @@ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) * checks on the other bits at runtime */ FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) -/* Indicates whether cp register reads and writes by guest code should access - * the secure or nonsecure bank of banked registers; note that this is not - * the same thing as the current security state of the processor! - */ -FIELD(TBFLAG_A32, NS, 19, 1) /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ From patchwork Tue Apr 16 12:57:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086310 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="bvBj8Do/"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5Qz62gQz9s3l for ; Tue, 16 Apr 2019 23:13:28 +1000 (AEST) Received: from localhost ([127.0.0.1]:36538 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNts-0008Vo-VK for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:13:25 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfU-00051J-JX for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfS-0001Si-Lh for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:32 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:35634) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfR-0001OB-2u for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:30 -0400 Received: by mail-wr1-x442.google.com with SMTP id w1so26956454wrp.2 for ; Tue, 16 Apr 2019 05:58:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Tkj4srWAc4/EjY7BD+Il79S6ivdgS+b3NoUBeFSWH/s=; b=bvBj8Do/aVo7szYKVJdS0iWwv7zlN9y6RwnKkVpG5o0WfZ4oRP+MsZoRQqc/X98we1 sk7ahAnpQ1TwVnJOZw67//M3nuozxjATPzw+AIo/g9upZco1MILS4GpJmjyNFaMhQb+V l2CzMb0o3y99sPg82KvA+e0S+kMaW2rV2p8q0pPqWMrhe36FlAgvvi5YLb5y7hVIY8ue 4ikKGXxxzahIL/6mRMG3OacmegyZRWbj+Mi9oyY7Y/bBnYiCedIWw/kjcz30R3rj0+6n c72+nv2zF1fPl0g9zaBrVDQfo57Z9tMd80B6Md1R3cnd7zQfMNhregdCgtFsGxBp45oX Cd/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Tkj4srWAc4/EjY7BD+Il79S6ivdgS+b3NoUBeFSWH/s=; b=M+np46GA3Px12MWdO8H/JqbViyFNdq86dbuuabOmOkOg9AOLvG6fPLoVxIeeiKTVOo Uze8pbGkRqIOvgEJZ7Up1Zi+/4sLj2CjoLZpDclqcPg4S419SmMwWK7H+fkz4t66luwl 9hE2ttHHlaXEJsPk+DURuw8N5s3J/ooIXB/2zse0tgwpaMzn0r1+csMNprtOeek6kNhe 5gSXIhqrwy+rqZIuRzrGDigcw5iIiu77r1Z9BCEAkyetHmCBstRJC5VMZ5mZX9buHM72 kRe/DfLUEuMVjoif49tmd0GHEbYJ/IjoV9LhmJBQYUWk2j596ulnxOv1mjXyt/VEWeLb J4Zw== X-Gm-Message-State: APjAAAW4wHKKOrQ2tW1LlqEY3XIGliE8Hxjo10a0o+yJV6A1F+mKvCEy 9tpNr7yzgXcPmRY29gZitr+PA4/zYL8= X-Google-Smtp-Source: APXvYqzCjd3rGLsSL+ff9Gr9dru17N92aFNz4T+84uJH5aaXzc/cKTiiYwtOHu+usWM3agln47JFJg== X-Received: by 2002:a5d:4f8b:: with SMTP id d11mr21425562wru.150.1555419503330; Tue, 16 Apr 2019 05:58:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:35 +0100 Message-Id: <20190416125744.27770-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 17/26] target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We are close to running out of TB flags for AArch32; we could start using the cs_base word, but before we do that we can economise on our usage by sharing the same bits for the VFP VECSTRIDE field and the XScale XSCALE_CPAR field. This works because no XScale CPU ever had VFP. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++---- target/arm/cpu.c | 7 +++++++ target/arm/helper.c | 6 +++++- target/arm/translate.c | 9 +++++++-- 4 files changed, 25 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c436f628987..a4e4d17e787 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3139,6 +3139,12 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) FIELD(TBFLAG_A32, THUMB, 0, 1) FIELD(TBFLAG_A32, VECLEN, 1, 3) FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +/* + * We store the bottom two bits of the CPAR as TB flags and handle + * checks on the other bits at runtime. This shares the same bits as + * VECSTRIDE, which is OK as no XScale CPU has VFP. + */ +FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) /* * Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not @@ -3148,10 +3154,6 @@ FIELD(TBFLAG_A32, NS, 6, 1) FIELD(TBFLAG_A32, VFPEN, 7, 1) FIELD(TBFLAG_A32, CONDEXEC, 8, 8) FIELD(TBFLAG_A32, SCTLR_B, 16, 1) -/* We store the bottom two bits of the CPAR as TB flags and handle - * checks on the other bits at runtime - */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3f9c81e7e9e..dd6c4f6da8d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1035,6 +1035,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) set_feature(env, ARM_FEATURE_THUMB_DSP); } + /* + * We rely on no XScale CPU having VFP so we can use the same bits in the + * TB flags field for VECSTRIDE and XSCALE_CPAR. + */ + assert(!(arm_feature(env, ARM_FEATURE_VFP) && + arm_feature(env, ARM_FEATURE_XSCALE))); + if (arm_feature(env, ARM_FEATURE_V7) && !arm_feature(env, ARM_FEATURE_M) && !arm_feature(env, ARM_FEATURE_PMSA)) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 0c5b0a73e95..d8a9620b870 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13375,7 +13375,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } - flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); + /* Note that XSCALE_CPAR shares bits with VECSTRIDE */ + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + flags = FIELD_DP32(flags, TBFLAG_A32, + XSCALE_CPAR, env->cp15.c15_cpar); + } } flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); diff --git a/target/arm/translate.c b/target/arm/translate.c index d280b3a9a3a..9172a382c4d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13329,8 +13329,13 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); - dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); - dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + dc->vec_stride = 0; + } else { + dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); + dc->c15_cpar = 0; + } dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER); dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && regime_is_secure(env, dc->mmu_idx); From patchwork Tue Apr 16 12:57:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086311 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="q0wRlz97"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5R529mqz9s3l for ; Tue, 16 Apr 2019 23:13:37 +1000 (AEST) Received: from localhost ([127.0.0.1]:36543 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNu3-0000Ct-5O for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:13:35 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34816) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfW-00053W-Lx for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfU-0001Tb-I1 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:34 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:53927) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfS-0001P2-LE for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:30 -0400 Received: by mail-wm1-x341.google.com with SMTP id q16so25248636wmj.3 for ; Tue, 16 Apr 2019 05:58:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qUOb6S/RgXvQ6vDGgTslHclSF/T9I1n8yCzB97vIhKM=; b=q0wRlz97jWA6BRXVWBXn0RNQCwmQNMNXnmt6VfkA7h5a+rmzXCTCK98UM5rQOX408M GbcTHX80n3AVs1ybVXg5i1h6a0DuCIcTfDmnNEOzPb+8ynXyW05g0weFCA/AYzLXsYSF WK2gfJhshqVxjSS3iLRJ92tTabws8Q8mNDwSwtntR5KO65sj26UeXise783lKchmooDo TpXjqfyb5TPlhDhncTKCoIY9caokvlobJ9jCH5hnG5UUmaZjSGDm1Z6CludCUedGxRUg qVgGijTXRdvLWXgWoqplQ3IgYaPBTGWC+hOXqQdbQ76OUuyGE2wZkEP9v7NiwAi1I9Qs /bLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qUOb6S/RgXvQ6vDGgTslHclSF/T9I1n8yCzB97vIhKM=; b=Xvi0F1HPMekhIRtyZbVC3NHEcLK5scOALnIqlZyF9PEapmo4c0wzMnPi08UtNKKAF5 C41c5GCMmmCC1QVW2CafCOF+9t4CYcf7ojKQo7wIqDcJk5KfmlV/Ackg6HkU55iBzKyL zHtk1dBbpRTbNDFmXb+erLWEIu7yvjczy90VredpqTsIbH7L0IhDUKMY6lOEIMAvNZTQ BT1sop83X4UwQ/E2b07icN94Tgm6ywNnJOTkzjCvva4+aAUJlX7zfueq68OhtD5LOX08 Ne+F1SjQZSEIvPxp9mjBNT3h+gBmlr8DtYvfbuDoRXxa7wvYiU54JfXD/10zFnrSo5pn hiMw== X-Gm-Message-State: APjAAAV+h8DGgoZxZTnQKHdHillzeu8rjIu47UTo5VN4bZIcDd74mNL4 CascONMpC5uraG8LK7hl929aNA== X-Google-Smtp-Source: APXvYqyDvycWohBQGjX7DojDg2vclF+iM7R9WAF2BFBjHs7P6SVGhyDT+k9p3DSY8U0tIyx7Oy3lcA== X-Received: by 2002:a1c:1d97:: with SMTP id d145mr25767145wmd.136.1555419504688; Tue, 16 Apr 2019 05:58:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:36 +0100 Message-Id: <20190416125744.27770-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 18/26] target/arm: Set FPCCR.S when executing M-profile floating point insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The M-profile FPCCR.S bit indicates the security status of the floating point context. In the pseudocode ExecuteFPCheck() function it is unconditionally set to match the current security state whenever a floating point instruction is executed. Implement this by adding a new TB flag which tracks whether FPCCR.S is different from the current security state, so that we only need to emit the code to update it in the less-common case when it is not already set correctly. Note that we will add the handling for the other work done by ExecuteFPCheck() in later commits. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 1 + target/arm/helper.c | 5 +++++ target/arm/translate.c | 20 ++++++++++++++++++++ 4 files changed, 28 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a4e4d17e787..95924303dd5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3154,6 +3154,8 @@ FIELD(TBFLAG_A32, NS, 6, 1) FIELD(TBFLAG_A32, VFPEN, 7, 1) FIELD(TBFLAG_A32, CONDEXEC, 8, 8) FIELD(TBFLAG_A32, SCTLR_B, 16, 1) +/* For M profile only, set if FPCCR.S does not match current security state */ +FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 912cc2a4a52..26b2c29bb57 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -40,6 +40,7 @@ typedef struct DisasContext { bool v7m_handler_mode; bool v8m_secure; /* true if v8M and we're in Secure mode */ bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ + bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI * so that top level loop can generate correct syndrome information. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d8a9620b870..539da192e4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13422,6 +13422,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); } + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { + flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); + } + *pflags = flags; *cs_base = 0; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 9172a382c4d..a4fb811d6f2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3420,6 +3420,25 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) } } + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* Handle M-profile lazy FP state mechanics */ + + /* Update ownership of FP context: set FPCCR.S to match current state */ + if (s->v8m_fpccr_s_wrong) { + TCGv_i32 tmp; + + tmp = load_cpu_field(v7m.fpccr[M_REG_S]); + if (s->v8m_secure) { + tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK); + } else { + tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK); + } + store_cpu_field(tmp, v7m.fpccr[M_REG_S]); + /* Don't need to do this for any further FP insns in this TB */ + s->v8m_fpccr_s_wrong = false; + } + } + if (extract32(insn, 28, 4) == 0xf) { /* * Encodings with T=1 (Thumb) or unconditional (ARM): @@ -13340,6 +13359,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && regime_is_secure(env, dc->mmu_idx); dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK); + dc->v8m_fpccr_s_wrong = FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRONG); dc->cp_regs = cpu->cp_regs; dc->features = env->features; From patchwork Tue Apr 16 12:57:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086313 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="wbZ1IQHC"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5Tg0XDPz9s5c for ; Tue, 16 Apr 2019 23:15:51 +1000 (AEST) Received: from localhost ([127.0.0.1]:36582 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNwC-00020L-VR for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:15:49 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34859) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfY-00055u-KS for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfW-0001Uo-IN for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:36 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:53930) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfS-0001QP-Qh for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:32 -0400 Received: by mail-wm1-x344.google.com with SMTP id q16so25248754wmj.3 for ; Tue, 16 Apr 2019 05:58:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kfoRBt6+//K1FzvR7+mnI5hRYcOyIhwq+7x6ajOGyyg=; b=wbZ1IQHCG3XSS2zbIsdSHH7pT58E0st7gTwaOmW8lKu7/XCnZozsZe89jX7OjG8IjN PJCb+IRdvej/B7moHwoeuF78vZw6MOyY7ceiDa311SGt6hLoVydLgkkAD0/rtm162dWh +wpHF1PXfMFmbN+c7pvpqgFavA54AvhEu+lHZzsHwq5yzWTHIVHA1ai/TSWoVjoNtsfC t7npjurSsnvMbXzx6utWEgdBfTBGtFnqnmJOT5ZfEAlR473sEVmt5rmdEuKvuNPNBOpa WxHCgBCDU54+tXFx28pZX1HqLeGeebfTsO8olNfJrYaKi1fhdlfXF2jh45e5Zx0vTir4 53kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kfoRBt6+//K1FzvR7+mnI5hRYcOyIhwq+7x6ajOGyyg=; b=XuvUpsnKUeUSLffnfLXS4TwVKr0JLygahCl00st9/Qm2sq6AdvRFEMm5uLlwWXMNhl Ih+ItJiWJygFwoU8h3hIVULWzvCW2x1gmWNVsaoZXr3xKI9AHnWneaa8iX7tXoqolnTX ZqiRoSFgZcoJD5mDbdsADxuFSEIa+r3g9v9JYsaYbEYS9TV4qNa7j0HkBk33ox2m57AE aNO8RlUKE0zTX4MvvuyRl3L3ZkGbaSuZw2hG1oVmvs4EDG8mgWQBQTtievDgVmt3CGZl RZlkfVClZqmX92Zi/+rCU7cH3sgMqy2sR1UIXwYIndKq/sdVMJcO7bhv/3JbunitAAOa BYBg== X-Gm-Message-State: APjAAAWLOIf1mp7ZytOOCRwNmgLDfNruf3hi+jnNOKzf2DICGftH8r25 0CI3S2/SY6G3Jy7KbLwR/h+FcQ== X-Google-Smtp-Source: APXvYqy/PjVXQ/pi4yqtbK5wQVLWd46ok3ysXkECnCI612kfYLazUSdnP5s3bLYUnBzUp2PeQqiCpg== X-Received: by 2002:a1c:f204:: with SMTP id s4mr26600673wmc.51.1555419506406; Tue, 16 Apr 2019 05:58:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:37 +0100 Message-Id: <20190416125744.27770-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 19/26] target/arm: Activate M-profile floating point context when FPCCR.ASPEN is set X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The M-profile FPCCR.ASPEN bit indicates that automatic floating-point context preservation is enabled. Before executing any floating-point instruction, if FPCCR.ASPEN is set and the CONTROL FPCA/SFPA bits indicate that there is no active floating point context then we must create a new context (by initializing FPSCR and setting FPCA/SFPA to indicate that the context is now active). In the pseudocode this is handled by ExecuteFPCheck(). Implement this with a new TB flag which tracks whether we need to create a new FP context. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 1 + target/arm/helper.c | 13 +++++++++++++ target/arm/translate.c | 29 +++++++++++++++++++++++++++++ 4 files changed, 45 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 95924303dd5..500e0ab4c5d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3154,6 +3154,8 @@ FIELD(TBFLAG_A32, NS, 6, 1) FIELD(TBFLAG_A32, VFPEN, 7, 1) FIELD(TBFLAG_A32, CONDEXEC, 8, 8) FIELD(TBFLAG_A32, SCTLR_B, 16, 1) +/* For M profile only, set if we must create a new FP context */ +FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* For M profile only, set if FPCCR.S does not match current security state */ FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* For M profile only, Handler (ie not Thread) mode */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 26b2c29bb57..59b9dbd0136 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -41,6 +41,7 @@ typedef struct DisasContext { bool v8m_secure; /* true if v8M and we're in Secure mode */ bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ + bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI * so that top level loop can generate correct syndrome information. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 539da192e4e..2feb3f664fe 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13427,6 +13427,19 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); } + if (arm_feature(env, ARM_FEATURE_M) && + (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || + (env->v7m.secure && + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { + /* + * ASPEN is set, but FPCA/SFPA indicate that there is no active + * FP context; we must create a new FP context before executing + * any FP insn. + */ + flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); + } + *pflags = flags; *cs_base = 0; } diff --git a/target/arm/translate.c b/target/arm/translate.c index a4fb811d6f2..6829f975e65 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3437,6 +3437,33 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) /* Don't need to do this for any further FP insns in this TB */ s->v8m_fpccr_s_wrong = false; } + + if (s->v7m_new_fp_ctxt_needed) { + /* + * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA + * and the FPSCR. + */ + TCGv_i32 control, fpscr; + uint32_t bits = R_V7M_CONTROL_FPCA_MASK; + + fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); + gen_helper_vfp_set_fpscr(cpu_env, fpscr); + tcg_temp_free_i32(fpscr); + /* + * We don't need to arrange to end the TB, because the only + * parts of FPSCR which we cache in the TB flags are the VECLEN + * and VECSTRIDE, and those don't exist for M-profile. + */ + + if (s->v8m_secure) { + bits |= R_V7M_CONTROL_SFPA_MASK; + } + control = load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_ori_i32(control, control, bits); + store_cpu_field(control, v7m.control[M_REG_S]); + /* Don't need to do this for any further FP insns in this TB */ + s->v7m_new_fp_ctxt_needed = false; + } } if (extract32(insn, 28, 4) == 0xf) { @@ -13360,6 +13387,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) regime_is_secure(env, dc->mmu_idx); dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK); dc->v8m_fpccr_s_wrong = FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRONG); + dc->v7m_new_fp_ctxt_needed = + FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED); dc->cp_regs = cpu->cp_regs; dc->features = env->features; From patchwork Tue Apr 16 12:57:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="xQh+F+4A"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5Ty3QBxz9s7T for ; Tue, 16 Apr 2019 23:16:06 +1000 (AEST) Received: from localhost ([127.0.0.1]:36603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNwR-0002DS-8N for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:16:03 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34860) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfY-00055v-KR for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfW-0001V6-JC for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:36 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:39344) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfU-0001Qs-Fy for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:33 -0400 Received: by mail-wm1-x343.google.com with SMTP id n25so25318242wmk.4 for ; Tue, 16 Apr 2019 05:58:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Bad+ohxUQ2aXQF4pfMXnuYXIWQ2Nayau0QYhuZSUXeA=; b=xQh+F+4AbZ+JCj/OZ/rPi5WMngHxfn7bzPGmvSBmXWAksdoKPWFbXxpRxG+ubwvYzr xMuGppCtKP8bU2c0rfGv0rB6FmHFLCP8kPXniXAgn/uOVyapMzSBZq0nUbQPmUwTIFyO 9j9i/9aWuzWeNIJfun9jaWvbNk89jz9Dv7EJZAzAYMwIPEKHFMtG3vp7LlOOepW7dP5G AyFEn8yODfKJ6LtFT6c2+gumefP6ofHSDDUXhySESONyYP9IjaAAOWtbY/nHCW2N5QRh WFciEQN+3hqik5lXeP/HwyyHv0Ffyb63k54R3JCI+aiMclp3aZDgh8VjNOZZ9kcryJzT yyiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bad+ohxUQ2aXQF4pfMXnuYXIWQ2Nayau0QYhuZSUXeA=; b=juPA5JVBqcogd6FvuCDwqGKWCRHlXGxXSZ7HNBLvTZHKSfv/00WZG1xOF4f936Soip pr0rIFuf1ucD8dgI3lMQih8xBJKPPgx//gF8YhNNbO8y6Lc5Pbywx18PYJMrsCM5RLYC +Udkifxhsk9YhUDTQxsr/6MZyiKoX89VNij9wl0oXXKOHbM+kshHk0TsE04UN8AIM2bP ZifjgjLu/Ya5vlYiVffq7+AR/gdwvoD0c4Ry5uNVy3v/wyeCQMtTGONav1C48OJ9mWBm UN9J3paea2SEJuUyy1viz9eWicqjSqD7PZ21gowtXys+uWCb/iQMYUQ8/iOS0hdLN+aJ H/VQ== X-Gm-Message-State: APjAAAVSrS4Qnxn2tF6eXBH1yRp6j+orLZEP1/limjFq5U9ATf7rw2to 3/WmC6tZbjnKc4R8a93tGxpDaw== X-Google-Smtp-Source: APXvYqwCwOsyF7xm5StMQ+0Gl7Rnfk9xS5aaqHRR31UM6URdlacOLi2dhQQu/zPWFZxeQjOJYd879Q== X-Received: by 2002:a1c:80cd:: with SMTP id b196mr26034521wmd.84.1555419507531; Tue, 16 Apr 2019 05:58:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:38 +0100 Message-Id: <20190416125744.27770-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 20/26] target/arm: New helper function arm_v7m_mmu_idx_all() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add a new helper function which returns the MMU index to use for v7M, where the caller specifies all of the security state, privilege level and whether the execution priority is negative, and reimplement the existing arm_v7m_mmu_idx_for_secstate_and_priv() in terms of it. We are going to need this for the lazy-FP-stacking code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Suggestions for better function name welcome. arm_v7m_mmu_idx_for_secstate_and_priv_and_negpri() just seems way too long and unwieldy... --- target/arm/cpu.h | 7 +++++++ target/arm/helper.c | 14 +++++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 500e0ab4c5d..0a1b82dc996 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2912,6 +2912,13 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) } } +/* + * Return the MMU index for a v7M CPU with all relevant information + * manually specified. + */ +ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, + bool secstate, bool priv, bool negpri); + /* Return the MMU index for a v7M CPU in the specified security and * privilege state. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 2feb3f664fe..c8e30b40366 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13235,8 +13235,8 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, bool priv) +ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, + bool secstate, bool priv, bool negpri) { ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; @@ -13244,7 +13244,7 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, mmu_idx |= ARM_MMU_IDX_M_PRIV; } - if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { + if (negpri) { mmu_idx |= ARM_MMU_IDX_M_NEGPRI; } @@ -13255,6 +13255,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, return mmu_idx; } +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv) +{ + bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); + + return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); +} + /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) { From patchwork Tue Apr 16 12:57:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086312 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Ile/P/az"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5Sz65BFz9s3l for ; Tue, 16 Apr 2019 23:15:15 +1000 (AEST) Received: from localhost ([127.0.0.1]:36564 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNvd-0001RI-De for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:15:13 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34861) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfY-00055w-Kb for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfW-0001V0-IU for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:36 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:38422) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfS-0001Rp-Qx for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:32 -0400 Received: by mail-wr1-x429.google.com with SMTP id k11so26960934wro.5 for ; Tue, 16 Apr 2019 05:58:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UKTNZsCqpyNRif3KKld05j9boEG0kVru0ibsoluL1kE=; b=Ile/P/azeG+HQLIwK/vFRZLwwPfQ2J7nr4uSJ0Wpo9J3nLlf5JfyUsWggRhnjJJ7IF 6l0kDbb0DnDgCBJQIaWxWroAoTohw6g9F8fklLupCGPzKsIY60L3q0lwnexrW4VgHOCq KUWZourgwemqAp+4fOHd+EB9mrLkZ8xL1uogVgQRWAAqzXvr+iI0mJ7Rn3BTbu5bT9sS 63DVGHkRdsvpzktMd6lFIGGC95dylOQMOf3ag572nCE5/6JYTogiSfXT71qjnnNI3Scc C1+9SbKTFiYv5MZVllARH0wuXn3Rxrit2r04AnY+7uxK59Mq1nVAn8IV3Rq26bLZ0fAh vx5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UKTNZsCqpyNRif3KKld05j9boEG0kVru0ibsoluL1kE=; b=O5UXof+t0dfqTVo4lUBuQLpBo0nMA7UUVgegD+riAw2DR8oq5tQQ3nvUwXrrRdSC2x EE3bH48RoKln2NNBHXSAr8JMp43btQdjeoaT3nnC96/9RxN9rOrA/VuuNunJiGosWrl7 pom91kNETIOPbkcU5Jr8QjSFmvpNRrv5EjAN9aNNSx73usYiIC6EfaKafVr11j/AyTNI FQm0Vu0qaJOPWaUC1CV5Qq0DIA3jzy+RoNjCFNXbe6n4T1Ymcnmr1oHzEpdmPdigL40t dqO0aCnAjyicEYjrxPdCYYFoAitpYoV1e/S3e3kkDUgNb/eRZtKYjYZYuoPG3k/nzOIC FNDw== X-Gm-Message-State: APjAAAXNrQRbwlrrL1XQjNs0+xPtvq5tRGQ0yJVEJB31Iif23iIzRCN9 /VqneA5eXIVhaCfFBcDuoeP4VA== X-Google-Smtp-Source: APXvYqxejpR4lUFTbNapmohnz5DIsutX1aXHr+ndc8pMqAY2PUyHhGMhSBj+XK29yCd7UVyLb8037Q== X-Received: by 2002:a5d:4a8d:: with SMTP id o13mr39648953wrq.209.1555419508861; Tue, 16 Apr 2019 05:58:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:39 +0100 Message-Id: <20190416125744.27770-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PATCH 21/26] target/arm: New function armv7m_nvic_set_pending_lazyfp() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In the v7M architecture, if an exception is generated in the process of doing the lazy stacking of FP registers, the handling of possible escalation to HardFault is treated differently to the normal approach: it works based on the saved information about exception readiness that was stored in the FPCCR when the stack frame was created. Provide a new function armv7m_nvic_set_pending_lazyfp() which pends exceptions during lazy stacking, and implements this logic. This corresponds to the pseudocode TakePreserveFPException(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 12 ++++++ hw/intc/armv7m_nvic.c | 96 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0a1b82dc996..42df41b11ab 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2009,6 +2009,18 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); * a different exception). */ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); +/** + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending + * @opaque: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions + * generated in the course of lazy stacking of FP registers. + */ +void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); /** * armv7m_nvic_get_pending_irq_info: return highest priority pending * exception, and whether it targets Secure state diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 53b4631dace..fff6e694e60 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -655,6 +655,102 @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) do_armv7m_nvic_set_pending(opaque, irq, secure, true); } +void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) +{ + /* + * Pend an exception during lazy FP stacking. This differs + * from the usual exception pending because the logic for + * whether we should escalate depends on the saved context + * in the FPCCR register, not on the current state of the CPU/NVIC. + */ + NVICState *s = (NVICState *)opaque; + bool banked = exc_is_banked(irq); + VecInfo *vec; + bool targets_secure; + bool escalate = false; + /* + * We will only look at bits in fpccr if this is a banked exception + * (in which case 'secure' tells us whether it is the S or NS version). + * All the bits for the non-banked exceptions are in fpccr_s. + */ + uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; + uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; + + assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); + assert(!secure || banked); + + vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; + + targets_secure = banked ? secure : exc_targets_secure(s, irq); + + switch (irq) { + case ARMV7M_EXCP_DEBUG: + if (!(fpccr_s & R_V7M_FPCCR_MONRDY_MASK)) { + /* Ignore DebugMonitor exception */ + return; + } + break; + case ARMV7M_EXCP_MEM: + escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); + break; + case ARMV7M_EXCP_USAGE: + escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); + break; + case ARMV7M_EXCP_BUS: + escalate = !(fpccr_s & R_V7M_FPCCR_BFRDY_MASK); + break; + case ARMV7M_EXCP_SECURE: + escalate = !(fpccr_s & R_V7M_FPCCR_SFRDY_MASK); + break; + default: + g_assert_not_reached(); + } + + if (escalate) { + /* + * Escalate to HardFault: faults that initially targeted Secure + * continue to do so, even if HF normally targets NonSecure. + */ + irq = ARMV7M_EXCP_HARD; + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && + (targets_secure || + !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) { + vec = &s->sec_vectors[irq]; + } else { + vec = &s->vectors[irq]; + } + } + + if (!vec->enabled || + nvic_exec_prio(s) <= exc_group_prio(s, vec->prio, secure)) { + if (!(fpccr_s & R_V7M_FPCCR_HFRDY_MASK)) { + /* + * We want to escalate to HardFault but the context the + * FP state belongs to prevents the exception pre-empting. + */ + cpu_abort(&s->cpu->parent_obj, + "Lockup: can't escalate to HardFault during " + "lazy FP register stacking\n"); + } + } + + if (escalate) { + s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; + } + if (!vec->pending) { + vec->pending = 1; + /* + * We do not call nvic_irq_update(), because we know our caller + * is going to handle causing us to take the exception by + * raising EXCP_LAZYFP, so raising the IRQ line would be + * pointless extra work. We just need to recompute the + * priorities so that armv7m_nvic_can_take_pending_exception() + * returns the right answer. + */ + nvic_recompute_state(s); + } +} + /* Make pending IRQ active. */ void armv7m_nvic_acknowledge_irq(void *opaque) { From patchwork Tue Apr 16 12:57:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086324 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="CpPJxqaw"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5gP6Fnvz9s3l for ; Tue, 16 Apr 2019 23:24:17 +1000 (AEST) Received: from localhost ([127.0.0.1]:36706 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGO4N-0008Ey-R9 for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:24:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35019) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfe-0005Dx-Vu for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfc-0001Zy-Md for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:42 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:44715) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfa-0001SZ-HD for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:38 -0400 Received: by mail-wr1-x443.google.com with SMTP id y7so26894393wrn.11 for ; Tue, 16 Apr 2019 05:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BzHkJFvKAiz/tlfhEM+yVQrC/PFkZx9GRWTUJ1dPqLQ=; b=CpPJxqawwEkeQg2hqGYbIiLUiWSFo7xA6g6Mnh5Szd8aESdmkwQXoMu+4/UCBLcuwZ 9CaFEnnJUM7CWtrPee3AEdxoItgYVUgNjQC5l5FEuu3O4q2onhnlVLzlp0IkmR2rUfxi X9XAVjqcVrGJ7lSErXShdnRQJx78o4aTnUGJam24EEU/3WCAaxDjlIrVanodFi3oyYXE nSIAtpoj++xOyg/4dzhJBKHdPy7dXjYIlhjIL8AXi0wiRYiEG4ToqFnI+6aDL0q+AyrZ F9qOsZcGuSe/pMt88EuKrv30KrVtfGHZfRqewWpqkxOOYWMq4vCWIftuUbu03vj0ddyF /tJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BzHkJFvKAiz/tlfhEM+yVQrC/PFkZx9GRWTUJ1dPqLQ=; b=fXpzIXVt1vPN3QLJ9+ELRJMIJbR+LFmSrNDQ+9zT5Ll+/OuZeZyWVSZ8LYixdAapaz y7qFqh6Qx5H8/XxmKp1C+qitQiIOwUAMzpbXKlQ40AezC/hKt57X2hgWKS2p9jvVHpkR Z5YeWnIRk4CdarByXhU8MoTh7lc7dNPTJHZ8Ph9AlzzcKOUG9Sr+oBoicArZ2dymMeqG GNl1fsLszhKxX8/J1TDOU7vUwtMJ2ASODxs79HN8IHmbJA/RPXAlBKd40475mIgWbp5G TIw684ShMBjeNFK9GegcAlvhLEEry/4FhWG1rsTeBL6V3hBqxemS7bsdobROPFrE5OPj pY0g== X-Gm-Message-State: APjAAAXhCDv6JGfHB/4wKxxtuQajAVoEncZNe7dPscl3QbssQX5a9+Pc KHCx6BBSjMcowmLYVhqM1aYEVI0NrZ4= X-Google-Smtp-Source: APXvYqz711nJNKaGLQORO5oj3FOhJV4qO2CWShypw0x7hPHUz9CfJD+A645d3Wh5y5JADEcFPUPODQ== X-Received: by 2002:adf:f30a:: with SMTP id i10mr51156723wro.111.1555419510156; Tue, 16 Apr 2019 05:58:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:40 +0100 Message-Id: <20190416125744.27770-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 22/26] target/arm: Add lazy-FP-stacking support to v7m_stack_write() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Pushing registers to the stack for v7M needs to handle three cases: * the "normal" case where we pend exceptions * an "ignore faults" case where we set FSR bits but do not pend exceptions (this is used when we are handling some kinds of derived exception on exception entry) * a "lazy FP stacking" case, where different FSR bits are set and the exception is pended differently Implement this by changing the existing flag argument that tells us whether to ignore faults or not into an enum that specifies which of the 3 modes we should handle. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 118 +++++++++++++++++++++++++++++--------------- 1 file changed, 79 insertions(+), 39 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c8e30b40366..975ac9c6fc4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7580,8 +7580,18 @@ static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv) } } +/* + * What kind of stack write are we doing? This affects how exceptions + * generated during the stacking are treated. + */ +typedef enum StackingMode { + STACK_NORMAL, + STACK_IGNFAULTS, + STACK_LAZYFP, +} StackingMode; + static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, - ARMMMUIdx mmu_idx, bool ignfault) + ARMMMUIdx mmu_idx, StackingMode mode) { CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; @@ -7599,15 +7609,31 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, &attrs, &prot, &page_size, &fi, NULL)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { - qemu_log_mask(CPU_LOG_INT, - "...SecureFault with SFSR.AUVIOL during stacking\n"); - env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK; + if (mode == STACK_LAZYFP) { + qemu_log_mask(CPU_LOG_INT, + "...SecureFault with SFSR.LSPERR " + "during lazy stacking\n"); + env->v7m.sfsr |= R_V7M_SFSR_LSPERR_MASK; + } else { + qemu_log_mask(CPU_LOG_INT, + "...SecureFault with SFSR.AUVIOL " + "during stacking\n"); + env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK; + } + env->v7m.sfsr |= R_V7M_SFSR_SFARVALID_MASK; env->v7m.sfar = addr; exc = ARMV7M_EXCP_SECURE; exc_secure = false; } else { - qemu_log_mask(CPU_LOG_INT, "...MemManageFault with CFSR.MSTKERR\n"); - env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK; + if (mode == STACK_LAZYFP) { + qemu_log_mask(CPU_LOG_INT, + "...MemManageFault with CFSR.MLSPERR\n"); + env->v7m.cfsr[secure] |= R_V7M_CFSR_MLSPERR_MASK; + } else { + qemu_log_mask(CPU_LOG_INT, + "...MemManageFault with CFSR.MSTKERR\n"); + env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK; + } exc = ARMV7M_EXCP_MEM; exc_secure = secure; } @@ -7617,8 +7643,13 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, attrs, &txres); if (txres != MEMTX_OK) { /* BusFault trying to write the data */ - qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n"); - env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK; + if (mode == STACK_LAZYFP) { + qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.LSPERR\n"); + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_LSPERR_MASK; + } else { + qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n"); + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK; + } exc = ARMV7M_EXCP_BUS; exc_secure = false; goto pend_fault; @@ -7633,11 +7664,19 @@ pend_fault: * later if we have two derived exceptions. * The only case when we must not pend the exception but instead * throw it away is if we are doing the push of the callee registers - * and we've already generated a derived exception. Even in this - * case we will still update the fault status registers. + * and we've already generated a derived exception (this is indicated + * by the caller passing STACK_IGNFAULTS). Even in this case we will + * still update the fault status registers. */ - if (!ignfault) { + switch (mode) { + case STACK_NORMAL: armv7m_nvic_set_pending_derived(env->nvic, exc, exc_secure); + break; + case STACK_LAZYFP: + armv7m_nvic_set_pending_lazyfp(env->nvic, exc, exc_secure); + break; + case STACK_IGNFAULTS: + break; } return false; } @@ -8014,6 +8053,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, uint32_t limit; bool want_psp; uint32_t sig; + StackingMode smode = ignore_faults ? STACK_IGNFAULTS : STACK_NORMAL; if (dotailchain) { bool mode = lr & R_V7M_EXCRET_MODE_MASK; @@ -8057,23 +8097,15 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, */ sig = v7m_integrity_sig(env, lr); stacked_ok = - v7m_stack_write(cpu, frameptr, sig, mmu_idx, ignore_faults) && - v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, - ignore_faults) && - v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, - ignore_faults) && - v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx, - ignore_faults) && - v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx, - ignore_faults) && - v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx, - ignore_faults) && - v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx, - ignore_faults) && - v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx, - ignore_faults) && - v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx, - ignore_faults); + v7m_stack_write(cpu, frameptr, sig, mmu_idx, smode) && + v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, smode) && + v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, smode) && + v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx, smode) && + v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx, smode) && + v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx, smode) && + v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx, smode) && + v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx, smode) && + v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx, smode); /* Update SP regardless of whether any of the stack accesses failed. */ *frame_sp_p = frameptr; @@ -8352,14 +8384,20 @@ static bool v7m_push_stack(ARMCPU *cpu) * if it has higher priority). */ stacked_ok = stacked_ok && - v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, false) && - v7m_stack_write(cpu, frameptr + 4, env->regs[1], mmu_idx, false) && - v7m_stack_write(cpu, frameptr + 8, env->regs[2], mmu_idx, false) && - v7m_stack_write(cpu, frameptr + 12, env->regs[3], mmu_idx, false) && - v7m_stack_write(cpu, frameptr + 16, env->regs[12], mmu_idx, false) && - v7m_stack_write(cpu, frameptr + 20, env->regs[14], mmu_idx, false) && - v7m_stack_write(cpu, frameptr + 24, env->regs[15], mmu_idx, false) && - v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, false); + v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 4, env->regs[1], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 8, env->regs[2], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 12, env->regs[3], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 16, env->regs[12], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 20, env->regs[14], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 24, env->regs[15], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, STACK_NORMAL); if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) { /* FPU is active, try to save its registers */ @@ -8409,12 +8447,14 @@ static bool v7m_push_stack(ARMCPU *cpu) faddr += 8; /* skip the slot for the FPSCR */ } stacked_ok = stacked_ok && - v7m_stack_write(cpu, faddr, slo, mmu_idx, false) && - v7m_stack_write(cpu, faddr + 4, shi, mmu_idx, false); + v7m_stack_write(cpu, faddr, slo, + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, faddr + 4, shi, + mmu_idx, STACK_NORMAL); } stacked_ok = stacked_ok && v7m_stack_write(cpu, frameptr + 0x60, - vfp_get_fpscr(env), mmu_idx, false); + vfp_get_fpscr(env), mmu_idx, STACK_NORMAL); if (cpacr_pass) { for (i = 0; i < ((framesize == 0xa8) ? 32 : 16); i += 2) { *aa32_vfp_dreg(env, i / 2) = 0; From patchwork Tue Apr 16 12:57:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086317 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UoesVOvu"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5YC2WY0z9s3l for ; Tue, 16 Apr 2019 23:18:55 +1000 (AEST) Received: from localhost ([127.0.0.1]:36631 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNzB-0004Jo-9E for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:18:53 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34914) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfa-00058S-KX for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfY-0001WX-Js for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:38 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:34587) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfW-0001TH-H4 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:34 -0400 Received: by mail-wm1-x344.google.com with SMTP id r186so2294520wmf.1 for ; Tue, 16 Apr 2019 05:58:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vgFUR6xcpc3B+FPhUs+qoTJrY4/JQVuVV6lizjvsuwM=; b=UoesVOvuSQSma5E7cyukhcTuimUQWZM716eqHftc6ei1Qml7paVyX5WBXpCROSUpwv 6zRK7ZLk2i9UhVoEctgibuL28jkJO3b2bIYYaJjMayHTfWaHxQBN49kl+uOoxDuY+IBW DVW2BROcnujW27urJubHvY5BHZXgYlv7wPnEFkKTy/emDOIuWaW+BKRxDgD5afZIZNtk VENfzuoGKiKw9wr/+TEJcRwXlNctzd8/Xym+kRN3BVmX+/8TSiE4qoevxgXvEtfOw3Dj Z0TBUjAP/OvV3SNccClnoovV7N1tTmHRazndQEWwQaTWF2pN52Ozy8NfEkgPX7xN3K01 lJ0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vgFUR6xcpc3B+FPhUs+qoTJrY4/JQVuVV6lizjvsuwM=; b=KTpwxgTNGmVnNwF5D2sVFBic6PYAfJsAZNttJFvVNHA5bKOKybPHwOEmlPQ8o2HQaG 9Aalgs8cg1z71bU7i1j6ls1tvS+FUmqFqJJrr+ZuFFt30ZhHDF7Y+9FiRlsQNSZk6t0u pXeBb+SfPzCMjYh7CRBSLrona6hSTEkO3O8yeoLNCfFETC3avOqXHaWevEF+BJ37nzBr KpO8T1vkgP9I5QD3m4o1kjvDa8JdeJqGaYQJM495WgiuPwMLZUZqxheAFkD4iMxzOat5 fhO09xv8nnJq14jV00ztGY7+x6yf2qnwTaUf+1LsogmXoy3B+M9Cey3X1cEvwaUiXiJF TNGA== X-Gm-Message-State: APjAAAVTrslsSheoFRLktyzqEWvZXA1FYd/1sUi5cw+3VfXi2b3FlPE+ 7immF1foBOsQ18X1jzoQYbAEIxyM0ug= X-Google-Smtp-Source: APXvYqw0Tluqlc4dXWCfUUB9ocrnqOBoQUjavzMlTLXn1KTXgLtdaGXkyXorsJE/ZvYfYGuHH1zUUQ== X-Received: by 2002:a1c:c8:: with SMTP id 191mr25805188wma.44.1555419511380; Tue, 16 Apr 2019 05:58:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:41 +0100 Message-Id: <20190416125744.27770-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 23/26] target/arm: Implement M-profile lazy FP state preservation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The M-profile architecture floating point system supports lazy FP state preservation, where FP registers are not pushed to the stack when an exception occurs but are instead only saved if and when the first FP instruction in the exception handler is executed. Implement this in QEMU, corresponding to the check of LSPACT in the pseudocode ExecuteFPCheck(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 3 ++ target/arm/helper.h | 2 + target/arm/translate.h | 1 + target/arm/helper.c | 112 +++++++++++++++++++++++++++++++++++++++++ target/arm/translate.c | 22 ++++++++ 5 files changed, 140 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 42df41b11ab..8fd6551c6cd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -57,6 +57,7 @@ #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ +#define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ #define ARMV7M_EXCP_RESET 1 @@ -3173,6 +3174,8 @@ FIELD(TBFLAG_A32, NS, 6, 1) FIELD(TBFLAG_A32, VFPEN, 7, 1) FIELD(TBFLAG_A32, CONDEXEC, 8, 8) FIELD(TBFLAG_A32, SCTLR_B, 16, 1) +/* For M profile only, set if FPCCR.LSPACT is set */ +FIELD(TBFLAG_A32, LSPACT, 18, 1) /* For M profile only, set if we must create a new FP context */ FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* For M profile only, set if FPCCR.S does not match current security state */ diff --git a/target/arm/helper.h b/target/arm/helper.h index a09566f795c..0a3a80528c7 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -69,6 +69,8 @@ DEF_HELPER_2(v7m_blxns, void, env, i32) DEF_HELPER_3(v7m_tt, i32, env, i32, i32) +DEF_HELPER_1(v7m_preserve_fp_state, void, env) + DEF_HELPER_2(v8m_stackcheck, void, env, i32) DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32) diff --git a/target/arm/translate.h b/target/arm/translate.h index 59b9dbd0136..475d51f8ff8 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -42,6 +42,7 @@ typedef struct DisasContext { bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ + bool v7m_lspact; /* FPCCR.LSPACT set */ /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI * so that top level loop can generate correct syndrome information. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 975ac9c6fc4..c56746aafa2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7383,6 +7383,12 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) g_assert_not_reached(); } +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) +{ + /* translate.c should never generate calls here in user-only mode */ + g_assert_not_reached(); +} + uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) { /* The TT instructions can be used by unprivileged code, but in @@ -7742,6 +7748,97 @@ pend_fault: return false; } +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) +{ + /* + * Preserve FP state (because LSPACT was set and we are about + * to execute an FP instruction). This corresponds to the + * PreserveFPState() pseudocode. + * We may throw an exception if the stacking fails. + */ + ARMCPU *cpu = arm_env_get_cpu(env); + bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + bool negpri = !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK); + bool is_priv = !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK); + bool splimviol = env->v7m.fpccr[is_secure] & R_V7M_FPCCR_SPLIMVIOL_MASK; + uint32_t fpcar = env->v7m.fpcar[is_secure]; + bool stacked_ok = true; + bool ts = is_secure && (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); + bool take_exception; + + /* Take the iothread lock as we are going to touch the NVIC */ + qemu_mutex_lock_iothread(); + + /* Check the background context had access to the FPU */ + if (!v7m_cpacr_pass(env, is_secure, is_priv)) { + armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, is_secure); + env->v7m.cfsr[is_secure] |= R_V7M_CFSR_NOCP_MASK; + stacked_ok = false; + } else if (!is_secure && !extract32(env->v7m.nsacr, 10, 1)) { + armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, M_REG_S); + env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; + stacked_ok = false; + } + + if (!splimviol && stacked_ok) { + /* We only stack if the stack limit wasn't violated */ + int i; + ARMMMUIdx mmu_idx; + + mmu_idx = arm_v7m_mmu_idx_all(env, is_secure, is_priv, negpri); + for (i = 0; i < (ts ? 32 : 16); i += 2) { + uint64_t dn = *aa32_vfp_dreg(env, i / 2); + uint32_t faddr = fpcar + 4 * i; + uint32_t slo = extract64(dn, 0, 32); + uint32_t shi = extract64(dn, 32, 32); + + if (i >= 16) { + faddr += 8; /* skip the slot for the FPSCR */ + } + stacked_ok = stacked_ok && + v7m_stack_write(cpu, faddr, slo, mmu_idx, STACK_LAZYFP) && + v7m_stack_write(cpu, faddr + 4, shi, mmu_idx, STACK_LAZYFP); + } + + stacked_ok = stacked_ok && + v7m_stack_write(cpu, fpcar + 0x40, + vfp_get_fpscr(env), mmu_idx, STACK_LAZYFP); + } + + /* + * We definitely pended an exception, but it's possible that it + * might not be able to be taken now. If its priority permits us + * to take it now, then we must not update the LSPACT or FP regs, + * but instead jump out to take the exception immediately. + * If it's just pending and won't be taken until the current + * handler exits, then we do update LSPACT and the FP regs. + */ + take_exception = !stacked_ok && + armv7m_nvic_can_take_pending_exception(env->nvic); + + qemu_mutex_unlock_iothread(); + + if (take_exception) { + raise_exception_ra(env, EXCP_LAZYFP, 0, 1, GETPC()); + } + + env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; + + if (ts) { + /* Clear s0 to s31 and the FPSCR */ + int i; + + for (i = 0; i < 32; i += 2) { + *aa32_vfp_dreg(env, i / 2) = 0; + } + vfp_set_fpscr(env, 0); + } + /* + * Otherwise s0 to s15 and FPSCR are UNKNOWN; we choose to leave them + * unchanged. + */ +} + /* Write to v7M CONTROL.SPSEL bit for the specified security bank. * This may change the current stack pointer between Main and Process * stack pointers if it is done for the CONTROL register for the current @@ -9067,6 +9164,7 @@ static void arm_log_exception(int idx) [EXCP_NOCP] = "v7M NOCP UsageFault", [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", [EXCP_STKOF] = "v8M STKOF UsageFault", + [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", }; if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { @@ -9360,6 +9458,12 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) return; } break; + case EXCP_LAZYFP: + /* + * We already pended the specific exception in the NVIC in the + * v7m_preserve_fp_state() helper function. + */ + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ @@ -13488,6 +13592,14 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); } + if (arm_feature(env, ARM_FEATURE_M)) { + bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { + flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); + } + } + *pflags = flags; *cs_base = 0; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 6829f975e65..04988efca7c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3423,6 +3423,27 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) if (arm_dc_feature(s, ARM_FEATURE_M)) { /* Handle M-profile lazy FP state mechanics */ + /* Trigger lazy-state preservation if necessary */ + if (s->v7m_lspact) { + /* + * Lazy state saving affects external memory and also the NVIC, + * so we must mark it as an IO operation for icount. + */ + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_v7m_preserve_fp_state(cpu_env); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } + /* + * If the preserve_fp_state helper doesn't throw an exception + * then it will clear LSPACT; we don't need to repeat this for + * any further FP insns in this TB. + */ + s->v7m_lspact = false; + } + /* Update ownership of FP context: set FPCCR.S to match current state */ if (s->v8m_fpccr_s_wrong) { TCGv_i32 tmp; @@ -13389,6 +13410,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->v8m_fpccr_s_wrong = FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRONG); dc->v7m_new_fp_ctxt_needed = FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED); + dc->v7m_lspact = FIELD_EX32(tb_flags, TBFLAG_A32, LSPACT); dc->cp_regs = cpu->cp_regs; dc->features = env->features; From patchwork Tue Apr 16 12:57:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086321 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="fJlrEG1P"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5c913sFz9s7T for ; Tue, 16 Apr 2019 23:21:28 +1000 (AEST) Received: from localhost ([127.0.0.1]:36682 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGO1e-0006C0-Lb for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:21:26 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34967) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfc-0005BB-PC for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfa-0001Y1-KF for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:40 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:45795) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfY-0001Ty-M4 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:38 -0400 Received: by mail-wr1-x441.google.com with SMTP id s15so26896593wra.12 for ; Tue, 16 Apr 2019 05:58:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KKWm6gZFAyj+LJquTLC2CU4eM0/C0INvFXmEW6XbIt4=; b=fJlrEG1PxldDdz0NpNggkqwEfZxZmidN4DaNYt9JKqKYa8fKa9u3Ecav8KXq8slLAs j71jJw62HJKieu/mYH1Xx9QvhhHiZfnjkVWGikmSqMJxzcn8BrmvdLNSvNooy4p3uaOf /jmonvoFhuxWo/jJibtwZm0ZLw/yEbxndldo0Nu5HdWTeIyqGCseDjUE50JjFCjACEKk RJX81OZK7gM5Tx251r7F1l4ZCfUCuBla2OyhsDu6ytu0SNQcf8s9tgK6voxuA/Ielvwt TYPbc7MCIqXI1DwKL5/BvEcjrX5uDP0V62SQ0e23mvL/sx8rznq1ZUuVYxjO2K0AEIHL CdIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KKWm6gZFAyj+LJquTLC2CU4eM0/C0INvFXmEW6XbIt4=; b=tk3ENkd16em7vYQN6uXN47AV3dETPEcVEDOj1L2Q46cOmr4zZ65HL8rm+gsaK8bNCt /TC+0Zv3k5nJFmrS2KP24d/oHsLJrOJ/p9mi/TdpfmZ6SnH3dUGoO/ItJHnazvvxtgTG qsW7quwBcoKLxV6J5rFTUYoVYso6ONrZvV8yAs4/0KxIcbjPIFkpyfegk0RaSwJU5a8R LuAz0WeF8nYN4RdN9Mip/+2Oam//+cUFlbvG0jyzQdVUrZGuZ2eR8lzqOA8oTGUuNVH2 J08bt5wSVvw8Uy6MiQqmjkayu9h/l0D+KTkgnpHg3LKbuRPjAbbeEkRMVwLZhwVjqOcA wvog== X-Gm-Message-State: APjAAAVupRZJfpJvuinHEhg4wbGRze+NWn9sPSAidEEYWtWcUt3W/5eX nmmqNBslr9DQZ5iTS/5MW7ksCsvpdso= X-Google-Smtp-Source: APXvYqwapI6gh5Kacfojabhk4iwQ2LAMxgPRpTvsyqCn+6xNv9ewOyhEkyCZ3bvQhfT2iRh4uy/npA== X-Received: by 2002:adf:b6a4:: with SMTP id j36mr50715615wre.55.1555419512552; Tue, 16 Apr 2019 05:58:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:42 +0100 Message-Id: <20190416125744.27770-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 24/26] target/arm: Implement VLSTM for v7M CPUs with an FPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Implement the VLSTM instruction for v7M for the FPU present case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 + target/arm/helper.h | 2 + target/arm/helper.c | 84 ++++++++++++++++++++++++++++++++++++++++++ target/arm/translate.c | 15 +++++++- 4 files changed, 102 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8fd6551c6cd..eac194b4d5f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -58,6 +58,8 @@ #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ +#define EXCP_LSERR 21 /* v8M LSERR SecureFault */ +#define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 0a3a80528c7..62051ae6d51 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -71,6 +71,8 @@ DEF_HELPER_3(v7m_tt, i32, env, i32, i32) DEF_HELPER_1(v7m_preserve_fp_state, void, env) +DEF_HELPER_2(v7m_vlstm, void, env, i32) + DEF_HELPER_2(v8m_stackcheck, void, env, i32) DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32) diff --git a/target/arm/helper.c b/target/arm/helper.c index c56746aafa2..ad049b2d9bc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7389,6 +7389,12 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) g_assert_not_reached(); } +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) +{ + /* translate.c should never generate calls here in user-only mode */ + g_assert_not_reached(); +} + uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) { /* The TT instructions can be used by unprivileged code, but in @@ -8405,6 +8411,74 @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, } } +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) +{ + /* fptr is the value of Rn, the frame pointer we store the FP regs to */ + bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + bool lspact = env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; + + assert(env->v7m.secure); + + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { + return; + } + + /* Check access to the coprocessor is permitted */ + if (!v7m_cpacr_pass(env, true, arm_current_el(env) != 0)) { + raise_exception_ra(env, EXCP_NOCP, 0, 1, GETPC()); + } + + if (lspact) { + /* LSPACT should not be active when there is active FP state */ + raise_exception_ra(env, EXCP_LSERR, 0, 1, GETPC()); + } + + if (fptr & 7) { + raise_exception_ra(env, EXCP_UNALIGNED, 0, 1, GETPC()); + } + + /* + * Note that we do not use v7m_stack_write() here, because the + * accesses should not set the FSR bits for stacking errors if they + * fail. (In pseudocode terms, they are AccType_NORMAL, not AccType_STACK + * or AccType_LAZYFP). Faults in cpu_stl_data() will throw exceptions + * and longjmp out. + */ + if (!(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPEN_MASK)) { + bool ts = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK; + int i; + + for (i = 0; i < (ts ? 32 : 16); i += 2) { + uint64_t dn = *aa32_vfp_dreg(env, i / 2); + uint32_t faddr = fptr + 4 * i; + uint32_t slo = extract64(dn, 0, 32); + uint32_t shi = extract64(dn, 32, 32); + + if (i >= 16) { + faddr += 8; /* skip the slot for the FPSCR */ + } + cpu_stl_data(env, faddr, slo); + cpu_stl_data(env, faddr + 4, shi); + } + cpu_stl_data(env, fptr + 0x40, vfp_get_fpscr(env)); + + /* + * If TS is 0 then s0 to s15 and FPSCR are UNKNOWN; we choose to + * leave them unchanged, matching our choice in v7m_preserve_fp_state. + */ + if (ts) { + for (i = 0; i < 32; i += 2) { + *aa32_vfp_dreg(env, i / 2) = 0; + } + vfp_set_fpscr(env, 0); + } + } else { + v7m_update_fpccr(env, fptr, false); + } + + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; +} + static bool v7m_push_stack(ARMCPU *cpu) { /* Do the "set up stack frame" part of exception entry, @@ -9165,6 +9239,8 @@ static void arm_log_exception(int idx) [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", [EXCP_STKOF] = "v8M STKOF UsageFault", [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", + [EXCP_LSERR] = "v8M LSERR UsageFault", + [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", }; if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { @@ -9339,6 +9415,14 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; break; + case EXCP_LSERR: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; + break; + case EXCP_UNALIGNED: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK; + break; case EXCP_SWI: /* The PC already points to the next instruction. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); diff --git a/target/arm/translate.c b/target/arm/translate.c index 04988efca7c..db478b779a9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11817,7 +11817,20 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (!s->v8m_secure || (insn & 0x0040f0ff)) { goto illegal_op; } - /* Just NOP since FP support is not implemented */ + + if (arm_dc_feature(s, ARM_FEATURE_VFP)) { + TCGv_i32 fptr = load_reg(s, rn); + + if (extract32(insn, 20, 1)) { + /* VLLDM */ + } else { + gen_helper_v7m_vlstm(cpu_env, fptr); + } + tcg_temp_free_i32(fptr); + + /* End the TB, because we have updated FP control bits */ + s->base.is_jmp = DISAS_UPDATE; + } break; } if (arm_dc_feature(s, ARM_FEATURE_VFP) && From patchwork Tue Apr 16 12:57:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="pCeWDVg5"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5YX4MkHz9s3l for ; Tue, 16 Apr 2019 23:19:12 +1000 (AEST) Received: from localhost ([127.0.0.1]:36633 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNzS-0004We-G3 for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:19:10 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34975) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfc-0005BH-Qs for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfa-0001Yo-Qg for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:40 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:40147) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfY-0001UY-OM for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:38 -0400 Received: by mail-wr1-x42a.google.com with SMTP id h4so26944892wre.7 for ; Tue, 16 Apr 2019 05:58:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qLgEBtxDMPEzuBe7c1di3k/rR2yFAimlmfsizuzN9Vs=; b=pCeWDVg5cXABpoyA+GQjCY8a5j7WcYkOlSG2rQ3THyez8WUJWQ0B9oF0m7rm5pHc73 RhUYoJDo4hfE30a+Snh6b8FM5fXwiQMxX2VkBddhuG6ZYcyLqGEvlVLpZZ+ZSJEws+Dk 7qaf94da/NfAICDDJHEBflfWtthoHU6dRJ1K1bddVoy8aprPHGEQtDLwpymWR5oUheGA heoTdV+lH8LjzcL/j7l8LYz6XWjrs7hqkcI05Vktp8zImgnXit+EzntrkHKeIjZ+6O8V LZ1NZO3cDPRgPphuVoSWDTs2h4FMARG8IVRiS2dGleZiD/7EbhPqmG74+pgUtmMmYyN8 oFcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qLgEBtxDMPEzuBe7c1di3k/rR2yFAimlmfsizuzN9Vs=; b=Az6waESSeiZiOr0OaLbCsJB+vZ3mFFfkEZ8kvDQ9mpH7zMFkJZOEu0ot4BkV3JiSBA /ncWFnwtqOM1GV8pI77+xj451ZtXivIyHAR0ZNXa4LBqobMjuGIKqIANiYiuZf3jd9Ij y3kqcK+ATLomRGxXs6xsK4oFO4HB0gRFOZFiTdUoX9unZqXtTUE4RJ4+rE1RF/G8oWJo D21tdD+ZZrjvn7OhOVuXBUbMgGS8hkIUoVJu9QqLj5U9OOnBaSkqW+PLSJpiXoiqewMq HmoF1khVIH3GNDtHb0v9eZA8RRnqWdTEH39fubeuC74LFPwA9hjqOuFGtMGZnWFY0Yy3 SyOw== X-Gm-Message-State: APjAAAVwQ8eQ4/RCesGtGuKqsL9c8N6puB6onJ+NiNNdfwBgIkwQeVdh XoqoAqScvrpJJOA2NgvHaxwCcA== X-Google-Smtp-Source: APXvYqw2Dp4Zkodw3y1ib9jd3buSAi7zSYi2y2MC2/vZm1uq96W5KMpECXzjhNgreQnq9QRA6gXxgQ== X-Received: by 2002:adf:ce8f:: with SMTP id r15mr49993536wrn.90.1555419513913; Tue, 16 Apr 2019 05:58:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:43 +0100 Message-Id: <20190416125744.27770-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PATCH 25/26] target/arm: Implement VLLDM for v7M CPUs with an FPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Implement the VLLDM instruction for v7M for the FPU present cas. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.h | 1 + target/arm/helper.c | 54 ++++++++++++++++++++++++++++++++++++++++++ target/arm/translate.c | 2 +- 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 62051ae6d51..50cb036378b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -72,6 +72,7 @@ DEF_HELPER_3(v7m_tt, i32, env, i32, i32) DEF_HELPER_1(v7m_preserve_fp_state, void, env) DEF_HELPER_2(v7m_vlstm, void, env, i32) +DEF_HELPER_2(v7m_vlldm, void, env, i32) DEF_HELPER_2(v8m_stackcheck, void, env, i32) diff --git a/target/arm/helper.c b/target/arm/helper.c index ad049b2d9bc..4b680c379dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7395,6 +7395,12 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) g_assert_not_reached(); } +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) +{ + /* translate.c should never generate calls here in user-only mode */ + g_assert_not_reached(); +} + uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) { /* The TT instructions can be used by unprivileged code, but in @@ -8479,6 +8485,54 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; } +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) +{ + /* fptr is the value of Rn, the frame pointer we load the FP regs from */ + assert(env->v7m.secure); + + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { + return; + } + + /* Check access to the coprocessor is permitted */ + if (!v7m_cpacr_pass(env, true, arm_current_el(env) != 0)) { + raise_exception_ra(env, EXCP_NOCP, 0, 1, GETPC()); + } + + if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) { + /* State in FP is still valid */ + env->v7m.fpccr[M_REG_S] &= ~R_V7M_FPCCR_LSPACT_MASK; + } else { + bool ts = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK; + int i; + uint32_t fpscr; + + if (fptr & 7) { + raise_exception_ra(env, EXCP_UNALIGNED, 0, 1, GETPC()); + } + + for (i = 0; i < (ts ? 32 : 16); i += 2) { + uint32_t slo, shi; + uint64_t dn; + uint32_t faddr = fptr + 4 * i; + + if (i >= 16) { + faddr += 8; /* skip the slot for the FPSCR */ + } + + slo = cpu_ldl_data(env, faddr); + shi = cpu_ldl_data(env, faddr + 4); + + dn = (uint64_t) shi << 32 | slo; + *aa32_vfp_dreg(env, i / 2) = dn; + } + fpscr = cpu_ldl_data(env, fptr + 0x40); + vfp_set_fpscr(env, fpscr); + } + + env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; +} + static bool v7m_push_stack(ARMCPU *cpu) { /* Do the "set up stack frame" part of exception entry, diff --git a/target/arm/translate.c b/target/arm/translate.c index db478b779a9..5ad9923715e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11822,7 +11822,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) TCGv_i32 fptr = load_reg(s, rn); if (extract32(insn, 20, 1)) { - /* VLLDM */ + gen_helper_v7m_vlldm(cpu_env, fptr); } else { gen_helper_v7m_vlstm(cpu_env, fptr); } From patchwork Tue Apr 16 12:57:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1086316 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="g5BhKRB7"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44k5X43T8fz9s4Y for ; Tue, 16 Apr 2019 23:17:56 +1000 (AEST) Received: from localhost ([127.0.0.1]:36616 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNyD-0003eI-Ps for incoming@patchwork.ozlabs.org; Tue, 16 Apr 2019 09:17:53 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34966) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNfc-0005BA-PA for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNfa-0001Yc-Ow for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:40 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:34512) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNfY-0001Vl-Og for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:38 -0400 Received: by mail-wr1-x444.google.com with SMTP id p10so26962613wrq.1 for ; Tue, 16 Apr 2019 05:58:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tO2IbzqkFfPLxQHEQtP7KD/Py5uleD69zDN6a2d6v0s=; b=g5BhKRB7QoF5P+fGXAexdSpC1m8IYCNpc8uaDDbaLKubN4BHTVCGY3h6IB5RWIqQZA MbV0nk4g1nemo1xF1ayKqp3yRJop5eu+ERgC0mI0DrpjQQ2eE+4hJ7pBjZbzg6GplElH Kj6pOUeoCx+0P5kaz/buSy3cYm9Fc1yEjB9hMMksAw9KGWU/NoKcvVMjP4qSM+aPvEVC xArfrW0aM1oLfNFTFRkNaF/aYEH0gIC0adBh0y+SVtLsMdBQ2pIyhvNhg1NofUke05U7 5z/KAkcV6d/7FQlR7UjRNmj2HInRvIJX6xQcGaaUgGqWLekq4ecwrSfQ6HwsyZjLHXFd m3ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tO2IbzqkFfPLxQHEQtP7KD/Py5uleD69zDN6a2d6v0s=; b=MadBPL6Y4zJ5QeUJh1uPO60CtuQ1itiudLDPwGmX6n3Hz/qe9/mzwUa/+AeBaZa/W8 ei17i2+NswzQVG2RfNhl3959fPNAq0qQZVPSJhpI+gJ3WJ+QKWgkeNya6j+5xDkRtZyZ 35t//5F7rLhcMO63vJOqe69837KvodAKFpktdDsISUQsOfmGV+9pFdo98IpJpgJs4Y9A nG+KQzibuLmGiPUJb5D4aMuTWVxPWuje3/ZZP3X/oaupF58pQAtyvE7qRCSqrIu50X7Q sGN5Q6mzEXflNM+42XjKJ/9nundc4lXh6WSXHYAJg2VMFticzmFgzv2k0t2MnzbghwLa xUOw== X-Gm-Message-State: APjAAAVPZUD38euyVtLiy5abR2/WuJ5XkU9yW9TatGxTrvEaHJ97n24E BZh5dqL3WpjYU61AcX/97vPVdEjHoPs= X-Google-Smtp-Source: APXvYqwh7/cSxCAppGXQHXu3W1Z4WJSBow/CYQ2cdKHKfXAsWyggL2b4uSB8x1+qi96fCuRF66YkJQ== X-Received: by 2002:adf:f78d:: with SMTP id q13mr51758249wrp.194.1555419515116; Tue, 16 Apr 2019 05:58:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:44 +0100 Message-Id: <20190416125744.27770-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 26/26] target/arm: Enable FPU for Cortex-M4 and Cortex-M33 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Enable the FPU by default for the Cortex-M4 and Cortex-M33. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dd6c4f6da8d..00d3299e212 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1494,8 +1494,12 @@ static void cortex_m4_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr = 0x410fc240; /* r0p0 */ cpu->pmsav7_dregion = 8; + cpu->isar.mvfr0 = 0x10110021; + cpu->isar.mvfr1 = 0x11000011; + cpu->isar.mvfr2 = 0x00000000; cpu->id_pfr0 = 0x00000030; cpu->id_pfr1 = 0x00000200; cpu->id_dfr0 = 0x00100000; @@ -1522,9 +1526,13 @@ static void cortex_m33_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr = 0x410fd213; /* r0p3 */ cpu->pmsav7_dregion = 16; cpu->sau_sregion = 8; + cpu->isar.mvfr0 = 0x10110021; + cpu->isar.mvfr1 = 0x11000011; + cpu->isar.mvfr2 = 0x00000040; cpu->id_pfr0 = 0x00000030; cpu->id_pfr1 = 0x00000210; cpu->id_dfr0 = 0x00200000;